system.cc revision 10554:fe2e2f06a7c8
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include "arch/x86/bios/intelmp.hh" 41#include "arch/x86/bios/smbios.hh" 42#include "arch/x86/regs/misc.hh" 43#include "arch/x86/isa_traits.hh" 44#include "arch/x86/system.hh" 45#include "arch/vtophys.hh" 46#include "base/loader/object_file.hh" 47#include "base/loader/symtab.hh" 48#include "base/intmath.hh" 49#include "base/trace.hh" 50#include "cpu/thread_context.hh" 51#include "mem/port_proxy.hh" 52#include "params/X86System.hh" 53#include "sim/byteswap.hh" 54 55using namespace LittleEndianGuest; 56using namespace X86ISA; 57 58X86System::X86System(Params *p) : 59 System(p), smbiosTable(p->smbios_table), 60 mpFloatingPointer(p->intel_mp_pointer), 61 mpConfigTable(p->intel_mp_table), 62 rsdp(p->acpi_description_table_pointer) 63{ 64} 65 66void 67X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg, 68 SegDescriptor desc, bool longmode) 69{ 70 uint64_t base = desc.baseLow + (desc.baseHigh << 24); 71 bool honorBase = !longmode || seg == SEGMENT_REG_FS || 72 seg == SEGMENT_REG_GS || 73 seg == SEGMENT_REG_TSL || 74 seg == SYS_SEGMENT_REG_TR; 75 uint64_t limit = desc.limitLow | (desc.limitHigh << 16); 76 77 SegAttr attr = 0; 78 79 attr.dpl = desc.dpl; 80 attr.unusable = 0; 81 attr.defaultSize = desc.d; 82 attr.longMode = desc.l; 83 attr.avl = desc.avl; 84 attr.granularity = desc.g; 85 attr.present = desc.p; 86 attr.system = desc.s; 87 attr.type = desc.type; 88 if (desc.s) { 89 if (desc.type.codeOrData) { 90 // Code segment 91 attr.expandDown = 0; 92 attr.readable = desc.type.r; 93 attr.writable = 0; 94 } else { 95 // Data segment 96 attr.expandDown = desc.type.e; 97 attr.readable = 1; 98 attr.writable = desc.type.w; 99 } 100 } else { 101 attr.readable = 1; 102 attr.writable = 1; 103 attr.expandDown = 0; 104 } 105 106 tc->setMiscReg(MISCREG_SEG_BASE(seg), base); 107 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? base : 0); 108 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), limit); 109 tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr); 110} 111 112void 113X86System::initState() 114{ 115 System::initState(); 116 117 if (!kernel) 118 fatal("No kernel to load.\n"); 119 120 if (kernel->getArch() == ObjectFile::I386) 121 fatal("Loading a 32 bit x86 kernel is not supported.\n"); 122 123 ThreadContext *tc = threadContexts[0]; 124 // This is the boot strap processor (BSP). Initialize it to look like 125 // the boot loader has just turned control over to the 64 bit OS. We 126 // won't actually set up real mode or legacy protected mode descriptor 127 // tables because we aren't executing any code that would require 128 // them. We do, however toggle the control bits in the correct order 129 // while allowing consistency checks and the underlying mechansims 130 // just to be safe. 131 132 const int NumPDTs = 4; 133 134 const Addr PageMapLevel4 = 0x70000; 135 const Addr PageDirPtrTable = 0x71000; 136 const Addr PageDirTable[NumPDTs] = 137 {0x72000, 0x73000, 0x74000, 0x75000}; 138 const Addr GDTBase = 0x76000; 139 140 const int PML4Bits = 9; 141 const int PDPTBits = 9; 142 const int PDTBits = 9; 143 144 /* 145 * Set up the gdt. 146 */ 147 uint8_t numGDTEntries = 0; 148 // Place holder at selector 0 149 uint64_t nullDescriptor = 0; 150 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 151 (uint8_t *)(&nullDescriptor), 8); 152 numGDTEntries++; 153 154 SegDescriptor initDesc = 0; 155 initDesc.type.codeOrData = 0; // code or data type 156 initDesc.type.c = 0; // conforming 157 initDesc.type.r = 1; // readable 158 initDesc.dpl = 0; // privilege 159 initDesc.p = 1; // present 160 initDesc.l = 1; // longmode - 64 bit 161 initDesc.d = 0; // operand size 162 initDesc.g = 1; // granularity 163 initDesc.s = 1; // system segment 164 initDesc.limitHigh = 0xFFFF; 165 initDesc.limitLow = 0xF; 166 initDesc.baseHigh = 0x0; 167 initDesc.baseLow = 0x0; 168 169 //64 bit code segment 170 SegDescriptor csDesc = initDesc; 171 csDesc.type.codeOrData = 1; 172 csDesc.dpl = 0; 173 //Because we're dealing with a pointer and I don't think it's 174 //guaranteed that there isn't anything in a nonvirtual class between 175 //it's beginning in memory and it's actual data, we'll use an 176 //intermediary. 177 uint64_t csDescVal = csDesc; 178 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 179 (uint8_t *)(&csDescVal), 8); 180 181 numGDTEntries++; 182 183 SegSelector cs = 0; 184 cs.si = numGDTEntries - 1; 185 186 tc->setMiscReg(MISCREG_CS, (MiscReg)cs); 187 188 //32 bit data segment 189 SegDescriptor dsDesc = initDesc; 190 uint64_t dsDescVal = dsDesc; 191 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 192 (uint8_t *)(&dsDescVal), 8); 193 194 numGDTEntries++; 195 196 SegSelector ds = 0; 197 ds.si = numGDTEntries - 1; 198 199 tc->setMiscReg(MISCREG_DS, (MiscReg)ds); 200 tc->setMiscReg(MISCREG_ES, (MiscReg)ds); 201 tc->setMiscReg(MISCREG_FS, (MiscReg)ds); 202 tc->setMiscReg(MISCREG_GS, (MiscReg)ds); 203 tc->setMiscReg(MISCREG_SS, (MiscReg)ds); 204 205 tc->setMiscReg(MISCREG_TSL, 0); 206 tc->setMiscReg(MISCREG_TSG_BASE, GDTBase); 207 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 208 209 SegDescriptor tssDesc = initDesc; 210 uint64_t tssDescVal = tssDesc; 211 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 212 (uint8_t *)(&tssDescVal), 8); 213 214 numGDTEntries++; 215 216 SegSelector tss = 0; 217 tss.si = numGDTEntries - 1; 218 219 tc->setMiscReg(MISCREG_TR, (MiscReg)tss); 220 installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true); 221 222 /* 223 * Identity map the first 4GB of memory. In order to map this region 224 * of memory in long mode, there needs to be one actual page map level 225 * 4 entry which points to one page directory pointer table which 226 * points to 4 different page directory tables which are full of two 227 * megabyte pages. All of the other entries in valid tables are set 228 * to indicate that they don't pertain to anything valid and will 229 * cause a fault if used. 230 */ 231 232 // Put valid values in all of the various table entries which indicate 233 // that those entries don't point to further tables or pages. Then 234 // set the values of those entries which are needed. 235 236 // Page Map Level 4 237 238 // read/write, user, not present 239 uint64_t pml4e = X86ISA::htog(0x6); 240 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 241 physProxy.writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 242 } 243 // Point to the only PDPT 244 pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 245 physProxy.writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 246 247 // Page Directory Pointer Table 248 249 // read/write, user, not present 250 uint64_t pdpe = X86ISA::htog(0x6); 251 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 252 physProxy.writeBlob(PageDirPtrTable + offset, 253 (uint8_t *)(&pdpe), 8); 254 } 255 // Point to the PDTs 256 for (int table = 0; table < NumPDTs; table++) { 257 pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 258 physProxy.writeBlob(PageDirPtrTable + table * 8, 259 (uint8_t *)(&pdpe), 8); 260 } 261 262 // Page Directory Tables 263 264 Addr base = 0; 265 const Addr pageSize = 2 << 20; 266 for (int table = 0; table < NumPDTs; table++) { 267 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 268 // read/write, user, present, 4MB 269 uint64_t pdte = X86ISA::htog(0x87 | base); 270 physProxy.writeBlob(PageDirTable[table] + offset, 271 (uint8_t *)(&pdte), 8); 272 base += pageSize; 273 } 274 } 275 276 /* 277 * Transition from real mode all the way up to Long mode 278 */ 279 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 280 //Turn off paging. 281 cr0.pg = 0; 282 tc->setMiscReg(MISCREG_CR0, cr0); 283 //Turn on protected mode. 284 cr0.pe = 1; 285 tc->setMiscReg(MISCREG_CR0, cr0); 286 287 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 288 //Turn on pae. 289 cr4.pae = 1; 290 tc->setMiscReg(MISCREG_CR4, cr4); 291 292 //Point to the page tables. 293 tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 294 295 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 296 //Enable long mode. 297 efer.lme = 1; 298 tc->setMiscReg(MISCREG_EFER, efer); 299 300 //Start using longmode segments. 301 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 302 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 303 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 304 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 305 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 306 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 307 308 //Activate long mode. 309 cr0.pg = 1; 310 tc->setMiscReg(MISCREG_CR0, cr0); 311 312 tc->pcState(tc->getSystemPtr()->kernelEntry); 313 314 // We should now be in long mode. Yay! 315 316 Addr ebdaPos = 0xF0000; 317 Addr fixed, table; 318 319 //Write out the SMBios/DMI table 320 writeOutSMBiosTable(ebdaPos, fixed, table); 321 ebdaPos += (fixed + table); 322 ebdaPos = roundUp(ebdaPos, 16); 323 324 //Write out the Intel MP Specification configuration table 325 writeOutMPTable(ebdaPos, fixed, table); 326 ebdaPos += (fixed + table); 327} 328 329void 330X86System::writeOutSMBiosTable(Addr header, 331 Addr &headerSize, Addr &structSize, Addr table) 332{ 333 // If the table location isn't specified, just put it after the header. 334 // The header size as of the 2.5 SMBios specification is 0x1F bytes 335 if (!table) 336 table = header + 0x1F; 337 smbiosTable->setTableAddr(table); 338 339 smbiosTable->writeOut(physProxy, header, headerSize, structSize); 340 341 // Do some bounds checking to make sure we at least didn't step on 342 // ourselves. 343 assert(header > table || header + headerSize <= table); 344 assert(table > header || table + structSize <= header); 345} 346 347void 348X86System::writeOutMPTable(Addr fp, 349 Addr &fpSize, Addr &tableSize, Addr table) 350{ 351 // If the table location isn't specified and it exists, just put 352 // it after the floating pointer. The fp size as of the 1.4 Intel MP 353 // specification is 0x10 bytes. 354 if (mpConfigTable) { 355 if (!table) 356 table = fp + 0x10; 357 mpFloatingPointer->setTableAddr(table); 358 } 359 360 fpSize = mpFloatingPointer->writeOut(physProxy, fp); 361 if (mpConfigTable) 362 tableSize = mpConfigTable->writeOut(physProxy, table); 363 else 364 tableSize = 0; 365 366 // Do some bounds checking to make sure we at least didn't step on 367 // ourselves and the fp structure was the size we thought it was. 368 assert(fp > table || fp + fpSize <= table); 369 assert(table > fp || table + tableSize <= fp); 370 assert(fpSize == 0x10); 371} 372 373 374X86System::~X86System() 375{ 376 delete smbiosTable; 377} 378 379X86System * 380X86SystemParams::create() 381{ 382 return new X86System(this); 383} 384