misc.hh revision 5135
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_MISCREGS_HH__ 59#define __ARCH_X86_MISCREGS_HH__ 60 61#include "arch/x86/x86_traits.hh" 62#include "base/bitunion.hh" 63 64//These get defined in some system headers (at least termbits.h). That confuses 65//things here significantly. 66#undef CR0 67#undef CR2 68#undef CR3 69 70namespace X86ISA 71{ 72 enum CondFlagBit { 73 CFBit = 1 << 0, 74 PFBit = 1 << 2, 75 ECFBit = 1 << 3, 76 AFBit = 1 << 4, 77 EZFBit = 1 << 5, 78 ZFBit = 1 << 6, 79 SFBit = 1 << 7, 80 DFBit = 1 << 10, 81 OFBit = 1 << 11 82 }; 83 84 enum MiscRegIndex 85 { 86 // Control registers 87 // Most of these are invalid. 88 MISCREG_CR_BASE, 89 MISCREG_CR0 = MISCREG_CR_BASE, 90 MISCREG_CR1, 91 MISCREG_CR2, 92 MISCREG_CR3, 93 MISCREG_CR4, 94 MISCREG_CR5, 95 MISCREG_CR6, 96 MISCREG_CR7, 97 MISCREG_CR8, 98 MISCREG_CR9, 99 MISCREG_CR10, 100 MISCREG_CR11, 101 MISCREG_CR12, 102 MISCREG_CR13, 103 MISCREG_CR14, 104 MISCREG_CR15, 105 106 // Debug registers 107 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 108 MISCREG_DR0 = MISCREG_DR_BASE, 109 MISCREG_DR1, 110 MISCREG_DR2, 111 MISCREG_DR3, 112 MISCREG_DR4, 113 MISCREG_DR5, 114 MISCREG_DR6, 115 MISCREG_DR7, 116 117 // Flags register 118 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 119 120 // Extended feature enable register 121 MISCREG_EFER, 122 123 // Segment selectors 124 MISCREG_SEG_SEL_BASE, 125 MISCREG_ES = MISCREG_SEG_SEL_BASE, 126 MISCREG_CS, 127 MISCREG_SS, 128 MISCREG_DS, 129 MISCREG_FS, 130 MISCREG_GS, 131 132 // Hidden segment base field 133 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments, 134 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 135 MISCREG_CS_BASE, 136 MISCREG_SS_BASE, 137 MISCREG_DS_BASE, 138 MISCREG_FS_BASE, 139 MISCREG_GS_BASE, 140 141 // Hidden segment limit field 142 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments, 143 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 144 MISCREG_CS_LIMIT, 145 MISCREG_SS_LIMIT, 146 MISCREG_DS_LIMIT, 147 MISCREG_FS_LIMIT, 148 MISCREG_GS_LIMIT, 149 150 // Hidden segment limit attributes 151 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments, 152 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 153 MISCREG_CS_ATTR, 154 MISCREG_SS_ATTR, 155 MISCREG_DS_ATTR, 156 MISCREG_FS_ATTR, 157 MISCREG_GS_ATTR, 158 159 // System segment selectors 160 MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments, 161 MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE, 162 MISCREG_TR, 163 164 // Hidden system segment base field 165 MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments, 166 MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE, 167 MISCREG_TR_BASE, 168 MISCREG_GDTR_BASE, 169 MISCREG_IDTR_BASE, 170 171 // Hidden system segment limit field 172 MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments, 173 MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE, 174 MISCREG_TR_LIMIT, 175 MISCREG_GDTR_LIMIT, 176 MISCREG_IDTR_LIMIT, 177 178 // Hidden system segment attribute field 179 MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments, 180 MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE, 181 MISCREG_TR_ATTR, 182 183 // Floating point control registers 184 MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments, 185 186 //XXX Add "Model-Specific Registers" 187 188 NUM_MISCREGS 189 }; 190 191 static inline MiscRegIndex 192 MISCREG_CR(int index) 193 { 194 return (MiscRegIndex)(MISCREG_CR_BASE + index); 195 } 196 197 static inline MiscRegIndex 198 MISCREG_DR(int index) 199 { 200 return (MiscRegIndex)(MISCREG_DR_BASE + index); 201 } 202 203 static inline MiscRegIndex 204 MISCREG_SEG_SEL(int index) 205 { 206 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 207 } 208 209 static inline MiscRegIndex 210 MISCREG_SEG_BASE(int index) 211 { 212 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 213 } 214 215 static inline MiscRegIndex 216 MISCREG_SEG_LIMIT(int index) 217 { 218 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 219 } 220 221 static inline MiscRegIndex 222 MISCREG_SEG_ATTR(int index) 223 { 224 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 225 } 226 227 static inline MiscRegIndex 228 MISCREG_SYSSEG_SEL(int index) 229 { 230 return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index); 231 } 232 233 static inline MiscRegIndex 234 MISCREG_SYSSEG_BASE(int index) 235 { 236 return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index); 237 } 238 239 static inline MiscRegIndex 240 MISCREG_SYSSEG_LIMIT(int index) 241 { 242 return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index); 243 } 244 245 static inline MiscRegIndex 246 MISCREG_SYSSEG_ATTR(int index) 247 { 248 return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index); 249 } 250 251 /** 252 * A type to describe the condition code bits of the RFLAGS register, 253 * plus two flags, EZF and ECF, which are only visible to microcode. 254 */ 255 BitUnion64(CCFlagBits) 256 Bitfield<11> OF; 257 Bitfield<7> SF; 258 Bitfield<6> ZF; 259 Bitfield<5> EZF; 260 Bitfield<4> AF; 261 Bitfield<3> ECF; 262 Bitfield<2> PF; 263 Bitfield<0> CF; 264 EndBitUnion(CCFlagBits) 265 266 /** 267 * RFLAGS 268 */ 269 BitUnion64(RFLAGS) 270 Bitfield<21> ID; // ID Flag 271 Bitfield<20> VIP; // Virtual Interrupt Pending 272 Bitfield<19> VIF; // Virtual Interrupt Flag 273 Bitfield<18> AC; // Alignment Check 274 Bitfield<17> VM; // Virtual-8086 Mode 275 Bitfield<16> RF; // Resume Flag 276 Bitfield<14> NT; // Nested Task 277 Bitfield<13, 12> IOPL; // I/O Privilege Level 278 Bitfield<11> OF; // Overflow Flag 279 Bitfield<10> DF; // Direction Flag 280 Bitfield<9> IF; // Interrupt Flag 281 Bitfield<8> TF; // Trap Flag 282 Bitfield<7> SF; // Sign Flag 283 Bitfield<6> ZF; // Zero Flag 284 Bitfield<4> AF; // Auxiliary Flag 285 Bitfield<2> PF; // Parity Flag 286 Bitfield<0> CF; // Carry Flag 287 EndBitUnion(RFLAGS) 288 289 /** 290 * Control registers 291 */ 292 BitUnion64(CR0) 293 Bitfield<31> PG; // Paging 294 Bitfield<30> CD; // Cache Disable 295 Bitfield<29> NW; // Not Writethrough 296 Bitfield<18> AM; // Alignment Mask 297 Bitfield<16> WP; // Write Protect 298 Bitfield<5> NE; // Numeric Error 299 Bitfield<4> ET; // Extension Type 300 Bitfield<3> TS; // Task Switched 301 Bitfield<2> EM; // Emulation 302 Bitfield<1> MP; // Monitor Coprocessor 303 Bitfield<0> PE; // Protection Enabled 304 EndBitUnion(CR0) 305 306 // Page Fault Virtual Address 307 BitUnion64(CR2) 308 Bitfield<31, 0> legacy; 309 EndBitUnion(CR2) 310 311 BitUnion64(CR3) 312 Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table 313 // Base Address 314 Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table 315 // Base Address 316 Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table 317 // Base Address 318 Bitfield<4> PCD; // Page-Level Cache Disable 319 Bitfield<3> PWT; // Page-Level Writethrough 320 EndBitUnion(CR3) 321 322 BitUnion64(CR4) 323 Bitfield<10> OSXMMEXCPT; // Operating System Unmasked 324 // Exception Support 325 Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support 326 Bitfield<8> PCE; // Performance-Monitoring Counter Enable 327 Bitfield<7> PGE; // Page-Global Enable 328 Bitfield<6> MCE; // Machine Check Enable 329 Bitfield<5> PAE; // Physical-Address Extension 330 Bitfield<4> PSE; // Page Size Extensions 331 Bitfield<3> DE; // Debugging Extensions 332 Bitfield<2> TSD; // Time Stamp Disable 333 Bitfield<1> PVI; // Protected-Mode Virtual Interrupts 334 Bitfield<0> VME; // Virtual-8086 Mode Extensions 335 EndBitUnion(CR4) 336 337 BitUnion64(CR8) 338 Bitfield<3, 0> TPR; // Task Priority Register 339 EndBitUnion(CR4) 340 341 /** 342 * Segment Selector 343 */ 344 BitUnion64(SegSelector) 345 Bitfield<15, 3> SI; // Selector Index 346 Bitfield<2> TI; // Table Indicator 347 Bitfield<1, 0> RPL; // Requestor Privilege Level 348 EndBitUnion(SegSelector) 349 350 /** 351 * Segment Descriptors 352 */ 353 354 BitUnion64(SegDescriptor) 355 Bitfield<63, 56> baseHigh; 356 Bitfield<39, 16> baseLow; 357 Bitfield<55> G; // Granularity 358 Bitfield<54> D; // Default Operand Size 359 Bitfield<54> B; // Default Operand Size 360 Bitfield<53> L; // Long Attribute Bit 361 Bitfield<52> AVL; // Available To Software 362 Bitfield<51, 48> limitHigh; 363 Bitfield<15, 0> limitLow; 364 Bitfield<47> P; // Present 365 Bitfield<46, 45> DPL; // Descriptor Privilege-Level 366 Bitfield<44> S; // System 367 SubBitUnion(type, 43, 40) 368 // Specifies whether this descriptor is for code or data. 369 Bitfield<43> codeOrData; 370 371 // These bit fields are for code segments 372 Bitfield<42> C; // Conforming 373 Bitfield<41> R; // Readable 374 375 // These bit fields are for data segments 376 Bitfield<42> E; // Expand-Down 377 Bitfield<41> W; // Writable 378 379 // This is used for both code and data segments. 380 Bitfield<40> A; // Accessed 381 EndSubBitUnion(type) 382 EndBitUnion(SegDescriptor) 383 384 BitUnion64(GateDescriptor) 385 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 386 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 387 Bitfield<31, 16> selector; // Target Code-Segment Selector 388 Bitfield<47> P; // Present 389 Bitfield<46, 45> DPL; // Descriptor Privilege-Level 390 Bitfield<43, 40> type; 391 Bitfield<36, 32> count; // Parameter Count 392 EndBitUnion(GateDescriptor) 393 394 /** 395 * Descriptor-Table Registers 396 */ 397 BitUnion64(GDTR) 398 EndBitUnion(GDTR) 399 400 BitUnion64(IDTR) 401 EndBitUnion(IDTR) 402 403 BitUnion64(LDTR) 404 EndBitUnion(LDTR) 405 406 /** 407 * Task Register 408 */ 409 BitUnion64(TR) 410 EndBitUnion(TR) 411}; 412 413#endif // __ARCH_X86_INTREGS_HH__ 414