float.hh revision 6343
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IN NO EVENT SHALL THE COPYRIGHT 472995SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 482995SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 492995SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 502995SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 512995SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 522995SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 533025Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 543025Ssaidi@eecs.umich.edu * 553025Ssaidi@eecs.umich.edu * Authors: Gabe Black 562710SN/A */ 572710SN/A 582710SN/A#ifndef __ARCH_X86_FLOATREGS_HH__ 592710SN/A#define __ARCH_X86_FLOATREGS_HH__ 602710SN/A 612710SN/A#include "arch/x86/x86_traits.hh" 622710SN/A#include "base/bitunion.hh" 632934SN/A 642934SN/Anamespace X86ISA 652934SN/A{ 662953SN/A enum FloatRegIndex 672934SN/A { 682934SN/A // MMX/X87 registers 692934SN/A FLOATREG_MMX_BASE, 702953SN/A FLOATREG_FPR_BASE = FLOATREG_MMX_BASE, 712934SN/A FLOATREG_MMX0 = FLOATREG_MMX_BASE, 722934SN/A FLOATREG_MMX1, 732934SN/A FLOATREG_MMX2, 742953SN/A FLOATREG_MMX3, 752566SN/A FLOATREG_MMX4, 763005Sstever@eecs.umich.edu FLOATREG_MMX5, 773005Sstever@eecs.umich.edu FLOATREG_MMX6, 782995SN/A FLOATREG_MMX7, 792995SN/A 802995SN/A FLOATREG_FPR0 = FLOATREG_FPR_BASE, 812995SN/A FLOATREG_FPR1, 822995SN/A FLOATREG_FPR2, 832995SN/A FLOATREG_FPR3, 842995SN/A FLOATREG_FPR4, 852995SN/A FLOATREG_FPR5, 862917SN/A FLOATREG_FPR6, 872995SN/A FLOATREG_FPR7, 883005Sstever@eecs.umich.edu 892995SN/A FLOATREG_XMM_BASE = FLOATREG_MMX_BASE + NumMMXRegs, 903005Sstever@eecs.umich.edu FLOATREG_XMM0_LOW = FLOATREG_XMM_BASE, 913005Sstever@eecs.umich.edu FLOATREG_XMM0_HIGH, 923005Sstever@eecs.umich.edu FLOATREG_XMM1_LOW, 933005Sstever@eecs.umich.edu FLOATREG_XMM1_HIGH, 943005Sstever@eecs.umich.edu FLOATREG_XMM2_LOW, 953005Sstever@eecs.umich.edu FLOATREG_XMM2_HIGH, 963050Sstever@eecs.umich.edu FLOATREG_XMM3_LOW, 973005Sstever@eecs.umich.edu FLOATREG_XMM3_HIGH, 983005Sstever@eecs.umich.edu FLOATREG_XMM4_LOW, 993005Sstever@eecs.umich.edu FLOATREG_XMM4_HIGH, 1003050Sstever@eecs.umich.edu FLOATREG_XMM5_LOW, 1013025Ssaidi@eecs.umich.edu FLOATREG_XMM5_HIGH, 1023005Sstever@eecs.umich.edu FLOATREG_XMM6_LOW, 1033005Sstever@eecs.umich.edu FLOATREG_XMM6_HIGH, 1043005Sstever@eecs.umich.edu FLOATREG_XMM7_LOW, 1053005Sstever@eecs.umich.edu FLOATREG_XMM7_HIGH, 1063005Sstever@eecs.umich.edu FLOATREG_XMM8_LOW, 1073050Sstever@eecs.umich.edu FLOATREG_XMM8_HIGH, 1083005Sstever@eecs.umich.edu FLOATREG_XMM9_LOW, 1093005Sstever@eecs.umich.edu FLOATREG_XMM9_HIGH, 1103005Sstever@eecs.umich.edu FLOATREG_XMM10_LOW, 1112566SN/A FLOATREG_XMM10_HIGH, 1122710SN/A FLOATREG_XMM11_LOW, 1132710SN/A FLOATREG_XMM11_HIGH, 1142917SN/A FLOATREG_XMM12_LOW, 1153046Sstever@eecs.umich.edu FLOATREG_XMM12_HIGH, 1162948SN/A FLOATREG_XMM13_LOW, 1172948SN/A FLOATREG_XMM13_HIGH, 1182948SN/A FLOATREG_XMM14_LOW, 1193046Sstever@eecs.umich.edu FLOATREG_XMM14_HIGH, 1202917SN/A FLOATREG_XMM15_LOW, 1213046Sstever@eecs.umich.edu FLOATREG_XMM15_HIGH, 1223022Shsul@eecs.umich.edu 1233046Sstever@eecs.umich.edu FLOATREG_MICROFP_BASE = FLOATREG_XMM_BASE + 2 * NumXMMRegs, 1243022Shsul@eecs.umich.edu FLOATREG_MICROFP0 = FLOATREG_MICROFP_BASE, 1253022Shsul@eecs.umich.edu FLOATREG_MICROFP1, 1263046Sstever@eecs.umich.edu FLOATREG_MICROFP2, 1273133Shsul@eecs.umich.edu FLOATREG_MICROFP3, 1283133Shsul@eecs.umich.edu FLOATREG_MICROFP4, 1293133Shsul@eecs.umich.edu FLOATREG_MICROFP5, 1303133Shsul@eecs.umich.edu FLOATREG_MICROFP6, 1312710SN/A FLOATREG_MICROFP7, 1322740SN/A 133 NUM_FLOATREGS = FLOATREG_MICROFP_BASE + NumMicroFpRegs 134 }; 135 136 static inline FloatRegIndex 137 FLOATREG_MMX(int index) 138 { 139 return (FloatRegIndex)(FLOATREG_MMX_BASE + index); 140 } 141 142 static inline FloatRegIndex 143 FLOATREG_FPR(int index) 144 { 145 return (FloatRegIndex)(FLOATREG_FPR_BASE + index); 146 } 147 148 static inline FloatRegIndex 149 FLOATREG_XMM_LOW(int index) 150 { 151 return (FloatRegIndex)(FLOATREG_XMM_BASE + 2 * index); 152 } 153 154 static inline FloatRegIndex 155 FLOATREG_XMM_HIGH(int index) 156 { 157 return (FloatRegIndex)(FLOATREG_XMM_BASE + 2 * index + 1); 158 } 159 160 static inline FloatRegIndex 161 FLOATREG_MICROFP(int index) 162 { 163 return (FloatRegIndex)(FLOATREG_MICROFP_BASE + index); 164 } 165 166 static inline FloatRegIndex 167 FLOATREG_STACK(int index, int top) 168 { 169 return FLOATREG_FPR((top + index + 8) % 8); 170 } 171}; 172 173#endif // __ARCH_X86_FLOATREGS_HH__ 174