registers.hh revision 9918:2c7219e2d999
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2007 The Hewlett-Packard Development Company 37414SAli.Saidi@ARM.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47414SAli.Saidi@ARM.com * All rights reserved. 57414SAli.Saidi@ARM.com * 67414SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77414SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87414SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97414SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107414SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117414SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127414SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137414SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 146019Shines@cs.fsu.edu * 156019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 166019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 176019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 186019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 196019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 216019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 226019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 236019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 246019Shines@cs.fsu.edu * this software without specific prior written permission. 256019Shines@cs.fsu.edu * 266019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 276019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 286019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 296019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 306019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 316019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 326019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 336019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 346019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 356019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 366019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 376019Shines@cs.fsu.edu * 386019Shines@cs.fsu.edu * Authors: Gabe Black 396019Shines@cs.fsu.edu */ 406019Shines@cs.fsu.edu 417414SAli.Saidi@ARM.com#ifndef __ARCH_X86_REGISTERS_HH__ 426019Shines@cs.fsu.edu#define __ARCH_X86_REGISTERS_HH__ 436019Shines@cs.fsu.edu 4411793Sbrandon.potter@amd.com#include "arch/x86/generated/max_inst_regs.hh" 4511793Sbrandon.potter@amd.com#include "arch/x86/regs/int.hh" 466019Shines@cs.fsu.edu#include "arch/x86/regs/misc.hh" 476019Shines@cs.fsu.edu#include "arch/x86/x86_traits.hh" 486019Shines@cs.fsu.edu 496019Shines@cs.fsu.edunamespace X86ISA 506019Shines@cs.fsu.edu{ 516019Shines@cs.fsu.eduusing X86ISAInst::MaxInstSrcRegs; 528232Snate@binkert.orgusing X86ISAInst::MaxInstDestRegs; 536019Shines@cs.fsu.eduusing X86ISAInst::MaxMiscDestRegs; 5411854Sbrandon.potter@amd.comconst int NumMiscRegs = NUM_MISCREGS; 557678Sgblack@eecs.umich.edu 566019Shines@cs.fsu.educonst int NumIntArchRegs = NUM_INTREGS; 5711800Sbrandon.potter@amd.comconst int NumIntRegs = 586019Shines@cs.fsu.edu NumIntArchRegs + NumMicroIntRegs + 596019Shines@cs.fsu.edu NumPseudoIntRegs + NumImplicitIntRegs; 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.edu// Each 128 bit xmm register is broken into two effective 64 bit registers. 626019Shines@cs.fsu.edu// Add 8 for the indices that are mapped over the fp stack 6311851Sbrandon.potter@amd.comconst int NumFloatRegs = 6411851Sbrandon.potter@amd.com NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8; 6511851Sbrandon.potter@amd.com 666019Shines@cs.fsu.edu// These enumerate all the registers for dependence tracking. 6710037SARM gem5 Developersenum DependenceTags { 6810037SARM gem5 Developers // FP_Reg_Base must be large enough to be bigger than any integer 6911851Sbrandon.potter@amd.com // register index which has the IntFoldBit (1 << 6) set. To be safe 7011851Sbrandon.potter@amd.com // we just start at (1 << 7) == 128. 7111851Sbrandon.potter@amd.com FP_Reg_Base = 128, 7210037SARM gem5 Developers Misc_Reg_Base = FP_Reg_Base + NumFloatRegs, 736400Sgblack@eecs.umich.edu Max_Reg_Index = Misc_Reg_Base + NumMiscRegs 746019Shines@cs.fsu.edu}; 756019Shines@cs.fsu.edu 766019Shines@cs.fsu.edu// semantically meaningful register indices 776019Shines@cs.fsu.edu//There is no such register in X86 786019Shines@cs.fsu.educonst int ZeroReg = NUM_INTREGS; 796019Shines@cs.fsu.educonst int StackPointerReg = INTREG_RSP; 8010318Sandreas.hansson@arm.com//X86 doesn't seem to have a link register 816019Shines@cs.fsu.educonst int ReturnAddressReg = 0; 826019Shines@cs.fsu.educonst int ReturnValueReg = INTREG_RAX; 8311386Ssteve.reinhardt@amd.comconst int FramePointerReg = INTREG_RBP; 846019Shines@cs.fsu.edu 856019Shines@cs.fsu.edu// Some OS syscalls use a second register (rdx) to return a second 8611851Sbrandon.potter@amd.com// value 8711851Sbrandon.potter@amd.comconst int SyscallPseudoReturnReg = INTREG_RDX; 8811851Sbrandon.potter@amd.com 8910037SARM gem5 Developerstypedef uint64_t IntReg; 9010037SARM gem5 Developers//XXX Should this be a 128 bit structure for XMM memory ops? 9110037SARM gem5 Developerstypedef uint64_t LargestRead; 9210037SARM gem5 Developerstypedef uint64_t MiscReg; 9310037SARM gem5 Developers 9410037SARM gem5 Developers//These floating point types are correct for mmx, but not 9510037SARM gem5 Developers//technically for x87 (80 bits) or at all for xmm (128 bits) 9610037SARM gem5 Developerstypedef double FloatReg; 9710318Sandreas.hansson@arm.comtypedef uint64_t FloatRegBits; 9810037SARM gem5 Developerstypedef union 9910037SARM gem5 Developers{ 10011386Ssteve.reinhardt@amd.com IntReg intReg; 10110037SARM gem5 Developers FloatReg fpReg; 10210037SARM gem5 Developers MiscReg ctrlReg; 1036019Shines@cs.fsu.edu} AnyReg; 10411851Sbrandon.potter@amd.com 1056019Shines@cs.fsu.edutypedef uint16_t RegIndex; 10611851Sbrandon.potter@amd.com 10710318Sandreas.hansson@arm.com} // namespace X86ISA 1087640Sgblack@eecs.umich.edu 1097640Sgblack@eecs.umich.edu#endif // __ARCH_X86_REGFILE_HH__ 1107640Sgblack@eecs.umich.edu