registers.hh revision 9917
14120SN/A/*
24120SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company
39917Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
44120SN/A * All rights reserved.
54120SN/A *
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374120SN/A *
384120SN/A * Authors: Gabe Black
394120SN/A */
404120SN/A
416329Sgblack@eecs.umich.edu#ifndef __ARCH_X86_REGISTERS_HH__
426329Sgblack@eecs.umich.edu#define __ARCH_X86_REGISTERS_HH__
436216SN/A
448961Sgblack@eecs.umich.edu#include "arch/x86/generated/max_inst_regs.hh"
457629Sgblack@eecs.umich.edu#include "arch/x86/regs/int.hh"
467629Sgblack@eecs.umich.edu#include "arch/x86/regs/misc.hh"
476315SN/A#include "arch/x86/x86_traits.hh"
484137SN/A
494120SN/Anamespace X86ISA
504120SN/A{
516329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstSrcRegs;
526329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstDestRegs;
539046SAli.Saidi@ARM.comusing X86ISAInst::MaxMiscDestRegs;
546329Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS;
556313SN/A
566329Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_INTREGS;
576329Sgblack@eecs.umich.educonst int NumIntRegs =
586329Sgblack@eecs.umich.edu    NumIntArchRegs + NumMicroIntRegs +
596329Sgblack@eecs.umich.edu    NumPseudoIntRegs + NumImplicitIntRegs;
606319SN/A
619917Ssteve.reinhardt@amd.com// Each 128 bit xmm register is broken into two effective 64 bit registers.
629917Ssteve.reinhardt@amd.com// Add 8 for the indices that are mapped over the fp stack
636329Sgblack@eecs.umich.educonst int NumFloatRegs =
649917Ssteve.reinhardt@amd.com    NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
656315SN/A
666329Sgblack@eecs.umich.edu// These enumerate all the registers for dependence tracking.
676329Sgblack@eecs.umich.eduenum DependenceTags {
689917Ssteve.reinhardt@amd.com    // FP_Base_DepTag must be large enough to be bigger than any integer
699917Ssteve.reinhardt@amd.com    // register index which has the IntFoldBit (1 << 6) set.  To be safe
709917Ssteve.reinhardt@amd.com    // we just start at (1 << 7) == 128.
716329Sgblack@eecs.umich.edu    FP_Base_DepTag = 128,
729917Ssteve.reinhardt@amd.com    Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs,
737649Sminkyu.jeong@arm.com    Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
746329Sgblack@eecs.umich.edu};
754137SN/A
766329Sgblack@eecs.umich.edu// semantically meaningful register indices
776329Sgblack@eecs.umich.edu//There is no such register in X86
786329Sgblack@eecs.umich.educonst int ZeroReg = NUM_INTREGS;
796329Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_RSP;
806329Sgblack@eecs.umich.edu//X86 doesn't seem to have a link register
816329Sgblack@eecs.umich.educonst int ReturnAddressReg = 0;
826329Sgblack@eecs.umich.educonst int ReturnValueReg = INTREG_RAX;
836329Sgblack@eecs.umich.educonst int FramePointerReg = INTREG_RBP;
844137SN/A
856329Sgblack@eecs.umich.edu// Some OS syscalls use a second register (rdx) to return a second
866329Sgblack@eecs.umich.edu// value
876329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = INTREG_RDX;
886329Sgblack@eecs.umich.edu
896329Sgblack@eecs.umich.edutypedef uint64_t IntReg;
906329Sgblack@eecs.umich.edu//XXX Should this be a 128 bit structure for XMM memory ops?
916329Sgblack@eecs.umich.edutypedef uint64_t LargestRead;
926329Sgblack@eecs.umich.edutypedef uint64_t MiscReg;
936329Sgblack@eecs.umich.edu
946329Sgblack@eecs.umich.edu//These floating point types are correct for mmx, but not
956329Sgblack@eecs.umich.edu//technically for x87 (80 bits) or at all for xmm (128 bits)
966329Sgblack@eecs.umich.edutypedef double FloatReg;
976329Sgblack@eecs.umich.edutypedef uint64_t FloatRegBits;
986329Sgblack@eecs.umich.edutypedef union
996329Sgblack@eecs.umich.edu{
1006329Sgblack@eecs.umich.edu    IntReg intReg;
1016329Sgblack@eecs.umich.edu    FloatReg fpReg;
1026329Sgblack@eecs.umich.edu    MiscReg ctrlReg;
1036329Sgblack@eecs.umich.edu} AnyReg;
1046329Sgblack@eecs.umich.edu
1056329Sgblack@eecs.umich.edutypedef uint16_t RegIndex;
1064137SN/A
1077811Ssteve.reinhardt@amd.com} // namespace X86ISA
1084120SN/A
1094120SN/A#endif // __ARCH_X86_REGFILE_HH__
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