registers.hh revision 7629
12089SN/A/* 22022SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company 35268Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55268Sksewell@umich.edu * The license below extends only to copyright in the software and shall 65268Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75268Sksewell@umich.edu * property including but not limited to intellectual property relating 85268Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95268Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105268Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115268Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125268Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135268Sksewell@umich.edu * 145268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 155268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 165268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 175268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 185268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 195268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 205268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 215268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 225268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 235268Sksewell@umich.edu * this software without specific prior written permission. 245268Sksewell@umich.edu * 255268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332706Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342022SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352022SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612234Sgabeblack@google.com * 372022SN/A * Authors: Gabe Black 382022SN/A */ 392022SN/A 402022SN/A#ifndef __ARCH_X86_REGISTERS_HH__ 412022SN/A#define __ARCH_X86_REGISTERS_HH__ 422022SN/A 432022SN/A#include "arch/x86/max_inst_regs.hh" 442022SN/A#include "arch/x86/regs/int.hh" 452022SN/A#include "arch/x86/regs/misc.hh" 462686Sksewell@umich.edu#include "arch/x86/x86_traits.hh" 472022SN/A 482022SN/Anamespace X86ISA 492022SN/A{ 502686Sksewell@umich.eduusing X86ISAInst::MaxInstSrcRegs; 512022SN/Ausing X86ISAInst::MaxInstDestRegs; 522022SN/Aconst int NumMiscArchRegs = NUM_MISCREGS; 532022SN/Aconst int NumMiscRegs = NUM_MISCREGS; 542022SN/A 5510184SCurtis.Dunham@arm.comconst int NumIntArchRegs = NUM_INTREGS; 562022SN/Aconst int NumIntRegs = 572022SN/A NumIntArchRegs + NumMicroIntRegs + 582022SN/A NumPseudoIntRegs + NumImplicitIntRegs; 592022SN/A 602022SN/A//Each 128 bit xmm register is broken into two effective 64 bit registers. 612686Sksewell@umich.educonst int NumFloatRegs = 622022SN/A NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; 632022SN/Aconst int NumFloatArchRegs = NumFloatRegs + 8; 6412234Sgabeblack@google.com 6512234Sgabeblack@google.com// These enumerate all the registers for dependence tracking. 662022SN/Aenum DependenceTags { 672239SN/A //There are 16 microcode registers at the moment. This is an 682022SN/A //unusually large constant to make sure there isn't overflow. 692022SN/A FP_Base_DepTag = 128, 702022SN/A Ctrl_Base_DepTag = 712022SN/A FP_Base_DepTag + 722239SN/A //mmx/x87 registers 732022SN/A 8 + 745222Sksewell@umich.edu //xmm registers 755222Sksewell@umich.edu 16 * 2 + 762104SN/A //The microcode fp registers 775222Sksewell@umich.edu 8 + 782022SN/A //The indices that are mapped over the fp stack 792022SN/A 8 802022SN/A}; 812022SN/A 822022SN/A// semantically meaningful register indices 832022SN/A//There is no such register in X86 842022SN/Aconst int ZeroReg = NUM_INTREGS; 852022SN/Aconst int StackPointerReg = INTREG_RSP; 862022SN/A//X86 doesn't seem to have a link register 872022SN/Aconst int ReturnAddressReg = 0; 882022SN/Aconst int ReturnValueReg = INTREG_RAX; 892022SN/Aconst int FramePointerReg = INTREG_RBP; 902022SN/A 912022SN/A// Some OS syscalls use a second register (rdx) to return a second 922022SN/A// value 932935Sksewell@umich.educonst int SyscallPseudoReturnReg = INTREG_RDX; 942083SN/A 953951Sgblack@eecs.umich.edutypedef uint64_t IntReg; 962022SN/A//XXX Should this be a 128 bit structure for XMM memory ops? 972022SN/Atypedef uint64_t LargestRead; 982022SN/Atypedef uint64_t MiscReg; 992022SN/A 1002022SN/A//These floating point types are correct for mmx, but not 101//technically for x87 (80 bits) or at all for xmm (128 bits) 102typedef double FloatReg; 103typedef uint64_t FloatRegBits; 104typedef union 105{ 106 IntReg intReg; 107 FloatReg fpReg; 108 MiscReg ctrlReg; 109} AnyReg; 110 111typedef uint16_t RegIndex; 112 113}; // namespace X86ISA 114 115#endif // __ARCH_X86_REGFILE_HH__ 116