pseudo_inst.cc revision 11877 
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Alexandru Dutu
29 */
30
31#include "arch/x86/pseudo_inst.hh"
32
33#include "arch/x86/system.hh"
34#include "cpu/thread_context.hh"
35#include "debug/PseudoInst.hh"
36#include "mem/se_translating_port_proxy.hh"
37#include "sim/process.hh"
38
39using namespace X86ISA;
40
41namespace X86ISA {
42
43/*
44 * This function is executed when the simulation is executing the syscall
45 * handler in System Emulation mode.
46 */
47void
48m5Syscall(ThreadContext *tc)
49{
50    DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n");
51
52    Fault fault;
53    tc->syscall(tc->readIntReg(INTREG_RAX), &fault);
54
55    MiscReg rflags = tc->readMiscReg(MISCREG_RFLAGS);
56    rflags &= ~(1 << 16);
57    tc->setMiscReg(MISCREG_RFLAGS, rflags);
58}
59
60/*
61 * This function is executed when the simulation is executing the pagefault
62 * handler in System Emulation mode.
63 */
64void
65m5PageFault(ThreadContext *tc)
66{
67    DPRINTF(PseudoInst, "PseudoInst::m5PageFault()\n");
68
69    Process *p = tc->getProcessPtr();
70    if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) {
71        SETranslatingPortProxy proxy = tc->getMemProxy();
72        // at this point we should have 6 values on the interrupt stack
73        int size = 6;
74        uint64_t is[size];
75        // reading the interrupt handler stack
76        proxy.readBlob(ISTVirtAddr + PageBytes - size*sizeof(uint64_t),
77                       (uint8_t *)&is, sizeof(is));
78        panic("Page fault at addr %#x\n\tInterrupt handler stack:\n"
79                "\tss: %#x\n"
80                "\trsp: %#x\n"
81                "\trflags: %#x\n"
82                "\tcs: %#x\n"
83                "\trip: %#x\n"
84                "\terr_code: %#x\n",
85                tc->readMiscReg(MISCREG_CR2),
86                is[5], is[4], is[3], is[2], is[1], is[0]);
87   }
88}
89
90} // namespace X86ISA
91