pseudo_inst.cc revision 11793
1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Alexandru Dutu 29 */ 30 31#include "arch/x86/pseudo_inst.hh" 32 33#include "arch/x86/system.hh" 34#include "debug/PseudoInst.hh" 35#include "sim/process.hh" 36#include "sim/system.hh" 37 38using namespace X86ISA; 39 40namespace X86ISA { 41 42/* 43 * This function is executed when the simulation is executing the syscall 44 * handler in System Emulation mode. 45 */ 46void 47m5Syscall(ThreadContext *tc) 48{ 49 DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n"); 50 51 tc->syscall(tc->readIntReg(INTREG_RAX)); 52 MiscReg rflags = tc->readMiscReg(MISCREG_RFLAGS); 53 rflags &= ~(1 << 16); 54 tc->setMiscReg(MISCREG_RFLAGS, rflags); 55} 56 57/* 58 * This function is executed when the simulation is executing the pagefault 59 * handler in System Emulation mode. 60 */ 61void 62m5PageFault(ThreadContext *tc) 63{ 64 DPRINTF(PseudoInst, "PseudoInst::m5PageFault()\n"); 65 66 Process *p = tc->getProcessPtr(); 67 if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) { 68 SETranslatingPortProxy proxy = tc->getMemProxy(); 69 // at this point we should have 6 values on the interrupt stack 70 int size = 6; 71 uint64_t is[size]; 72 // reading the interrupt handler stack 73 proxy.readBlob(ISTVirtAddr + PageBytes - size*sizeof(uint64_t), 74 (uint8_t *)&is, sizeof(is)); 75 panic("Page fault at addr %#x\n\tInterrupt handler stack:\n" 76 "\tss: %#x\n" 77 "\trsp: %#x\n" 78 "\trflags: %#x\n" 79 "\tcs: %#x\n" 80 "\trip: %#x\n" 81 "\terr_code: %#x\n", 82 tc->readMiscReg(MISCREG_CR2), 83 is[5], is[4], is[3], is[2], is[1], is[0]); 84 } 85} 86 87} // namespace X86ISA 88