pseudo_inst.cc revision 14024
110553Salexandru.dutu@amd.com/* 210553Salexandru.dutu@amd.com * Copyright (c) 2014 Advanced Micro Devices, Inc. 310553Salexandru.dutu@amd.com * All rights reserved. 410553Salexandru.dutu@amd.com * 510553Salexandru.dutu@amd.com * Redistribution and use in source and binary forms, with or without 610553Salexandru.dutu@amd.com * modification, are permitted provided that the following conditions are 710553Salexandru.dutu@amd.com * met: redistributions of source code must retain the above copyright 810553Salexandru.dutu@amd.com * notice, this list of conditions and the following disclaimer; 910553Salexandru.dutu@amd.com * redistributions in binary form must reproduce the above copyright 1010553Salexandru.dutu@amd.com * notice, this list of conditions and the following disclaimer in the 1110553Salexandru.dutu@amd.com * documentation and/or other materials provided with the distribution; 1210553Salexandru.dutu@amd.com * neither the name of the copyright holders nor the names of its 1310553Salexandru.dutu@amd.com * contributors may be used to endorse or promote products derived from 1410553Salexandru.dutu@amd.com * this software without specific prior written permission. 1510553Salexandru.dutu@amd.com * 1610553Salexandru.dutu@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710553Salexandru.dutu@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810553Salexandru.dutu@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910553Salexandru.dutu@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010553Salexandru.dutu@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110553Salexandru.dutu@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210553Salexandru.dutu@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310553Salexandru.dutu@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410553Salexandru.dutu@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510553Salexandru.dutu@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610553Salexandru.dutu@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710553Salexandru.dutu@amd.com * 2810553Salexandru.dutu@amd.com * Authors: Alexandru Dutu 2910553Salexandru.dutu@amd.com */ 3010553Salexandru.dutu@amd.com 3110553Salexandru.dutu@amd.com#include "arch/x86/pseudo_inst.hh" 3211793Sbrandon.potter@amd.com 3311659Salexandru.dutu@amd.com#include "arch/x86/system.hh" 3411800Sbrandon.potter@amd.com#include "cpu/thread_context.hh" 3510553Salexandru.dutu@amd.com#include "debug/PseudoInst.hh" 3611800Sbrandon.potter@amd.com#include "mem/se_translating_port_proxy.hh" 3710553Salexandru.dutu@amd.com#include "sim/process.hh" 3810553Salexandru.dutu@amd.com 3910553Salexandru.dutu@amd.comusing namespace X86ISA; 4010553Salexandru.dutu@amd.com 4110553Salexandru.dutu@amd.comnamespace X86ISA { 4210553Salexandru.dutu@amd.com 4310553Salexandru.dutu@amd.com/* 4410553Salexandru.dutu@amd.com * This function is executed when the simulation is executing the syscall 4510553Salexandru.dutu@amd.com * handler in System Emulation mode. 4610553Salexandru.dutu@amd.com */ 4710553Salexandru.dutu@amd.comvoid 4810553Salexandru.dutu@amd.comm5Syscall(ThreadContext *tc) 4910553Salexandru.dutu@amd.com{ 5010553Salexandru.dutu@amd.com DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n"); 5110553Salexandru.dutu@amd.com 5211877Sbrandon.potter@amd.com Fault fault; 5311877Sbrandon.potter@amd.com tc->syscall(tc->readIntReg(INTREG_RAX), &fault); 5411877Sbrandon.potter@amd.com 5513613Sgabeblack@google.com RegVal rflags = tc->readMiscReg(MISCREG_RFLAGS); 5610553Salexandru.dutu@amd.com rflags &= ~(1 << 16); 5710553Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_RFLAGS, rflags); 5810553Salexandru.dutu@amd.com} 5910553Salexandru.dutu@amd.com 6010553Salexandru.dutu@amd.com/* 6110553Salexandru.dutu@amd.com * This function is executed when the simulation is executing the pagefault 6210553Salexandru.dutu@amd.com * handler in System Emulation mode. 6310553Salexandru.dutu@amd.com */ 6410553Salexandru.dutu@amd.comvoid 6510553Salexandru.dutu@amd.comm5PageFault(ThreadContext *tc) 6610553Salexandru.dutu@amd.com{ 6710553Salexandru.dutu@amd.com DPRINTF(PseudoInst, "PseudoInst::m5PageFault()\n"); 6810553Salexandru.dutu@amd.com 6910553Salexandru.dutu@amd.com Process *p = tc->getProcessPtr(); 7010553Salexandru.dutu@amd.com if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) { 7114024Sgabeblack@google.com PortProxy &proxy = tc->getVirtProxy(); 7211659Salexandru.dutu@amd.com // at this point we should have 6 values on the interrupt stack 7311659Salexandru.dutu@amd.com int size = 6; 7411659Salexandru.dutu@amd.com uint64_t is[size]; 7511659Salexandru.dutu@amd.com // reading the interrupt handler stack 7614010Sgabeblack@google.com proxy.readBlob(ISTVirtAddr + PageBytes - size * sizeof(uint64_t), 7714010Sgabeblack@google.com &is, sizeof(is)); 7811659Salexandru.dutu@amd.com panic("Page fault at addr %#x\n\tInterrupt handler stack:\n" 7911659Salexandru.dutu@amd.com "\tss: %#x\n" 8011659Salexandru.dutu@amd.com "\trsp: %#x\n" 8111659Salexandru.dutu@amd.com "\trflags: %#x\n" 8211659Salexandru.dutu@amd.com "\tcs: %#x\n" 8311659Salexandru.dutu@amd.com "\trip: %#x\n" 8411659Salexandru.dutu@amd.com "\terr_code: %#x\n", 8511659Salexandru.dutu@amd.com tc->readMiscReg(MISCREG_CR2), 8611659Salexandru.dutu@amd.com is[5], is[4], is[3], is[2], is[1], is[0]); 8711659Salexandru.dutu@amd.com } 8810553Salexandru.dutu@amd.com} 8910553Salexandru.dutu@amd.com 9010553Salexandru.dutu@amd.com} // namespace X86ISA 91