process.cc revision 12458
110152Satgutier@umich.edu/* 210152Satgutier@umich.edu * Copyright (c) 2014 Advanced Micro Devices, Inc. 310152Satgutier@umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 410152Satgutier@umich.edu * All rights reserved. 510152Satgutier@umich.edu * 610152Satgutier@umich.edu * The license below extends only to copyright in the software and shall 710152Satgutier@umich.edu * not be construed as granting a license to any other intellectual 810152Satgutier@umich.edu * property including but not limited to intellectual property relating 910152Satgutier@umich.edu * to a hardware implementation of the functionality of the software 1010152Satgutier@umich.edu * licensed hereunder. You may use the software subject to the license 1110152Satgutier@umich.edu * terms below provided that you ensure that this notice is replicated 1210152Satgutier@umich.edu * unmodified and in its entirety in all distributions of the software, 1310152Satgutier@umich.edu * modified or unmodified, in source code or in binary form. 1410152Satgutier@umich.edu * 1510152Satgutier@umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 1610152Satgutier@umich.edu * All rights reserved. 1710152Satgutier@umich.edu * 1810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 1910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 2010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 2110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 2210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 2310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 2410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 2510233Syasuko.eckert@amd.com * neither the name of the copyright holders nor the names of its 2610233Syasuko.eckert@amd.com * contributors may be used to endorse or promote products derived from 2710152Satgutier@umich.edu * this software without specific prior written permission. 2810152Satgutier@umich.edu * 2910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910152Satgutier@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010152Satgutier@umich.edu * 4110152Satgutier@umich.edu * Authors: Gabe Black 4210152Satgutier@umich.edu * Ali Saidi 4310152Satgutier@umich.edu */ 4410152Satgutier@umich.edu 4510152Satgutier@umich.edu#include "arch/x86/process.hh" 4610152Satgutier@umich.edu 4710152Satgutier@umich.edu#include <string> 4810152Satgutier@umich.edu#include <vector> 4910152Satgutier@umich.edu 5010152Satgutier@umich.edu#include "arch/x86/isa_traits.hh" 5110152Satgutier@umich.edu#include "arch/x86/regs/misc.hh" 5210152Satgutier@umich.edu#include "arch/x86/regs/segment.hh" 5310152Satgutier@umich.edu#include "arch/x86/system.hh" 5410152Satgutier@umich.edu#include "arch/x86/types.hh" 5510152Satgutier@umich.edu#include "base/loader/elf_object.hh" 5610152Satgutier@umich.edu#include "base/loader/object_file.hh" 5710152Satgutier@umich.edu#include "base/logging.hh" 5810152Satgutier@umich.edu#include "base/trace.hh" 5910152Satgutier@umich.edu#include "cpu/thread_context.hh" 6010152Satgutier@umich.edu#include "debug/Stack.hh" 6110152Satgutier@umich.edu#include "mem/multi_level_page_table.hh" 6210152Satgutier@umich.edu#include "mem/page_table.hh" 6310152Satgutier@umich.edu#include "params/Process.hh" 6410232Syasuko.eckert@amd.com#include "sim/aux_vector.hh" 6510152Satgutier@umich.edu#include "sim/process_impl.hh" 6610232Syasuko.eckert@amd.com#include "sim/syscall_desc.hh" 6710232Syasuko.eckert@amd.com#include "sim/syscall_return.hh" 6810152Satgutier@umich.edu#include "sim/system.hh" 6910232Syasuko.eckert@amd.com 7010232Syasuko.eckert@amd.comusing namespace std; 7110152Satgutier@umich.eduusing namespace X86ISA; 7210232Syasuko.eckert@amd.com 7310152Satgutier@umich.edustatic const int ArgumentReg[] = { 7410152Satgutier@umich.edu INTREG_RDI, 7510152Satgutier@umich.edu INTREG_RSI, 7610232Syasuko.eckert@amd.com INTREG_RDX, 7710152Satgutier@umich.edu // This argument register is r10 for syscalls and rcx for C. 7810152Satgutier@umich.edu INTREG_R10W, 79 // INTREG_RCX, 80 INTREG_R8W, 81 INTREG_R9W 82}; 83 84static const int NumArgumentRegs M5_VAR_USED = 85 sizeof(ArgumentReg) / sizeof(const int); 86 87static const int ArgumentReg32[] = { 88 INTREG_EBX, 89 INTREG_ECX, 90 INTREG_EDX, 91 INTREG_ESI, 92 INTREG_EDI, 93 INTREG_EBP 94}; 95 96static const int NumArgumentRegs32 M5_VAR_USED = 97 sizeof(ArgumentReg) / sizeof(const int); 98 99X86Process::X86Process(ProcessParams *params, ObjectFile *objFile, 100 SyscallDesc *_syscallDescs, int _numSyscallDescs) 101 : Process(params, params->useArchPT ? 102 static_cast<EmulationPageTable *>( 103 new ArchPageTable( 104 params->name, params->pid, 105 params->system, PageBytes, 106 PageTableLayout)) : 107 new EmulationPageTable(params->name, params->pid, 108 PageBytes), 109 objFile), 110 syscallDescs(_syscallDescs), numSyscallDescs(_numSyscallDescs) 111{ 112} 113 114void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, 115 Process *p, TheISA::IntReg flags) 116{ 117 Process::clone(old_tc, new_tc, p, flags); 118 X86Process *process = (X86Process*)p; 119 *process = *this; 120} 121 122X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile, 123 SyscallDesc *_syscallDescs, int _numSyscallDescs) 124 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs) 125{ 126 127 vsyscallPage.base = 0xffffffffff600000ULL; 128 vsyscallPage.size = PageBytes; 129 vsyscallPage.vtimeOffset = 0x400; 130 vsyscallPage.vgettimeofdayOffset = 0x0; 131 132 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 133 objFile->bssSize(), PageBytes); 134 Addr stack_base = 0x7FFFFFFFF000ULL; 135 Addr max_stack_size = 8 * 1024 * 1024; 136 Addr next_thread_stack_base = stack_base - max_stack_size; 137 Addr mmap_end = 0x7FFFF7FFF000ULL; 138 139 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 140 next_thread_stack_base, mmap_end); 141} 142 143void 144I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault) 145{ 146 TheISA::PCState pc = tc->pcState(); 147 Addr eip = pc.pc(); 148 if (eip >= vsyscallPage.base && 149 eip < vsyscallPage.base + vsyscallPage.size) { 150 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset); 151 tc->pcState(pc); 152 } 153 X86Process::syscall(callnum, tc, fault); 154} 155 156 157I386Process::I386Process(ProcessParams *params, ObjectFile *objFile, 158 SyscallDesc *_syscallDescs, int _numSyscallDescs) 159 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs) 160{ 161 _gdtStart = ULL(0xffffd000); 162 _gdtSize = PageBytes; 163 164 vsyscallPage.base = 0xffffe000ULL; 165 vsyscallPage.size = PageBytes; 166 vsyscallPage.vsyscallOffset = 0x400; 167 vsyscallPage.vsysexitOffset = 0x410; 168 169 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 170 objFile->bssSize(), PageBytes); 171 Addr stack_base = _gdtStart; 172 Addr max_stack_size = 8 * 1024 * 1024; 173 Addr next_thread_stack_base = stack_base - max_stack_size; 174 Addr mmap_end = 0xB7FFF000ULL; 175 176 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 177 next_thread_stack_base, mmap_end); 178} 179 180SyscallDesc* 181X86Process::getDesc(int callnum) 182{ 183 if (callnum < 0 || callnum >= numSyscallDescs) 184 return NULL; 185 return &syscallDescs[callnum]; 186} 187 188void 189X86_64Process::initState() 190{ 191 X86Process::initState(); 192 193 argsInit(PageBytes); 194 195 // Set up the vsyscall page for this process. 196 allocateMem(vsyscallPage.base, vsyscallPage.size); 197 uint8_t vtimeBlob[] = { 198 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax 199 0x0f,0x05, // syscall 200 0xc3 // retq 201 }; 202 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset, 203 vtimeBlob, sizeof(vtimeBlob)); 204 205 uint8_t vgettimeofdayBlob[] = { 206 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax 207 0x0f,0x05, // syscall 208 0xc3 // retq 209 }; 210 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset, 211 vgettimeofdayBlob, sizeof(vgettimeofdayBlob)); 212 213 if (kvmInSE) { 214 PortProxy physProxy = system->physProxy; 215 216 Addr syscallCodePhysAddr = system->allocPhysPages(1); 217 Addr gdtPhysAddr = system->allocPhysPages(1); 218 Addr idtPhysAddr = system->allocPhysPages(1); 219 Addr istPhysAddr = system->allocPhysPages(1); 220 Addr tssPhysAddr = system->allocPhysPages(1); 221 Addr pfHandlerPhysAddr = system->allocPhysPages(1); 222 223 /* 224 * Set up the gdt. 225 */ 226 uint8_t numGDTEntries = 0; 227 uint64_t nullDescriptor = 0; 228 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 229 (uint8_t *)(&nullDescriptor), 8); 230 numGDTEntries++; 231 232 SegDescriptor initDesc = 0; 233 initDesc.type.codeOrData = 0; // code or data type 234 initDesc.type.c = 0; // conforming 235 initDesc.type.r = 1; // readable 236 initDesc.dpl = 0; // privilege 237 initDesc.p = 1; // present 238 initDesc.l = 1; // longmode - 64 bit 239 initDesc.d = 0; // operand size 240 initDesc.g = 1; // granularity 241 initDesc.s = 1; // system segment 242 initDesc.limitHigh = 0xFFFF; 243 initDesc.limitLow = 0xF; 244 initDesc.baseHigh = 0x0; 245 initDesc.baseLow = 0x0; 246 247 //64 bit code segment 248 SegDescriptor csLowPLDesc = initDesc; 249 csLowPLDesc.type.codeOrData = 1; 250 csLowPLDesc.dpl = 0; 251 uint64_t csLowPLDescVal = csLowPLDesc; 252 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 253 (uint8_t *)(&csLowPLDescVal), 8); 254 255 numGDTEntries++; 256 257 SegSelector csLowPL = 0; 258 csLowPL.si = numGDTEntries - 1; 259 csLowPL.rpl = 0; 260 261 //64 bit data segment 262 SegDescriptor dsLowPLDesc = initDesc; 263 dsLowPLDesc.type.codeOrData = 0; 264 dsLowPLDesc.dpl = 0; 265 uint64_t dsLowPLDescVal = dsLowPLDesc; 266 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 267 (uint8_t *)(&dsLowPLDescVal), 8); 268 269 numGDTEntries++; 270 271 SegSelector dsLowPL = 0; 272 dsLowPL.si = numGDTEntries - 1; 273 dsLowPL.rpl = 0; 274 275 //64 bit data segment 276 SegDescriptor dsDesc = initDesc; 277 dsDesc.type.codeOrData = 0; 278 dsDesc.dpl = 3; 279 uint64_t dsDescVal = dsDesc; 280 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 281 (uint8_t *)(&dsDescVal), 8); 282 283 numGDTEntries++; 284 285 SegSelector ds = 0; 286 ds.si = numGDTEntries - 1; 287 ds.rpl = 3; 288 289 //64 bit code segment 290 SegDescriptor csDesc = initDesc; 291 csDesc.type.codeOrData = 1; 292 csDesc.dpl = 3; 293 uint64_t csDescVal = csDesc; 294 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 295 (uint8_t *)(&csDescVal), 8); 296 297 numGDTEntries++; 298 299 SegSelector cs = 0; 300 cs.si = numGDTEntries - 1; 301 cs.rpl = 3; 302 303 SegSelector scall = 0; 304 scall.si = csLowPL.si; 305 scall.rpl = 0; 306 307 SegSelector sret = 0; 308 sret.si = dsLowPL.si; 309 sret.rpl = 3; 310 311 /* In long mode the TSS has been extended to 16 Bytes */ 312 TSSlow TSSDescLow = 0; 313 TSSDescLow.type = 0xB; 314 TSSDescLow.dpl = 0; // Privelege level 0 315 TSSDescLow.p = 1; // Present 316 TSSDescLow.g = 1; // Page granularity 317 TSSDescLow.limitHigh = 0xF; 318 TSSDescLow.limitLow = 0xFFFF; 319 TSSDescLow.baseLow = bits(TSSVirtAddr, 23, 0); 320 TSSDescLow.baseHigh = bits(TSSVirtAddr, 31, 24); 321 322 TSShigh TSSDescHigh = 0; 323 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32); 324 325 struct TSSDesc { 326 uint64_t low; 327 uint64_t high; 328 } tssDescVal = {TSSDescLow, TSSDescHigh}; 329 330 physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 331 (uint8_t *)(&tssDescVal), sizeof(tssDescVal)); 332 333 numGDTEntries++; 334 335 SegSelector tssSel = 0; 336 tssSel.si = numGDTEntries - 1; 337 338 uint64_t tss_base_addr = (TSSDescHigh.base << 32) | 339 (TSSDescLow.baseHigh << 24) | 340 TSSDescLow.baseLow; 341 uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16); 342 343 SegAttr tss_attr = 0; 344 345 tss_attr.type = TSSDescLow.type; 346 tss_attr.dpl = TSSDescLow.dpl; 347 tss_attr.present = TSSDescLow.p; 348 tss_attr.granularity = TSSDescLow.g; 349 tss_attr.unusable = 0; 350 351 for (int i = 0; i < contextIds.size(); i++) { 352 ThreadContext * tc = system->getThreadContext(contextIds[i]); 353 354 tc->setMiscReg(MISCREG_CS, cs); 355 tc->setMiscReg(MISCREG_DS, ds); 356 tc->setMiscReg(MISCREG_ES, ds); 357 tc->setMiscReg(MISCREG_FS, ds); 358 tc->setMiscReg(MISCREG_GS, ds); 359 tc->setMiscReg(MISCREG_SS, ds); 360 361 // LDT 362 tc->setMiscReg(MISCREG_TSL, 0); 363 SegAttr tslAttr = 0; 364 tslAttr.present = 1; 365 tslAttr.type = 2; 366 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr); 367 368 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 369 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 370 371 tc->setMiscReg(MISCREG_TR, tssSel); 372 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr); 373 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0); 374 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit); 375 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr); 376 377 //Start using longmode segments. 378 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 379 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 380 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 381 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 382 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 383 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 384 385 Efer efer = 0; 386 efer.sce = 1; // Enable system call extensions. 387 efer.lme = 1; // Enable long mode. 388 efer.lma = 1; // Activate long mode. 389 efer.nxe = 0; // Enable nx support. 390 efer.svme = 1; // Enable svm support for now. 391 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor. 392 tc->setMiscReg(MISCREG_EFER, efer); 393 394 //Set up the registers that describe the operating mode. 395 CR0 cr0 = 0; 396 cr0.pg = 1; // Turn on paging. 397 cr0.cd = 0; // Don't disable caching. 398 cr0.nw = 0; // This is bit is defined to be ignored. 399 cr0.am = 1; // No alignment checking 400 cr0.wp = 1; // Supervisor mode can write read only pages 401 cr0.ne = 1; 402 cr0.et = 1; // This should always be 1 403 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 404 // would be pointless. 405 cr0.em = 0; // Allow x87 instructions to execute natively. 406 cr0.mp = 1; // This doesn't really matter, but the manual suggests 407 // setting it to one. 408 cr0.pe = 1; // We're definitely in protected mode. 409 tc->setMiscReg(MISCREG_CR0, cr0); 410 411 CR0 cr2 = 0; 412 tc->setMiscReg(MISCREG_CR2, cr2); 413 414 CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr(); 415 tc->setMiscReg(MISCREG_CR3, cr3); 416 417 CR4 cr4 = 0; 418 //Turn on pae. 419 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States 420 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception 421 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support 422 cr4.pce = 0; // Performance-Monitoring Counter Enable 423 cr4.pge = 0; // Page-Global Enable 424 cr4.mce = 0; // Machine Check Enable 425 cr4.pae = 1; // Physical-Address Extension 426 cr4.pse = 0; // Page Size Extensions 427 cr4.de = 0; // Debugging Extensions 428 cr4.tsd = 0; // Time Stamp Disable 429 cr4.pvi = 0; // Protected-Mode Virtual Interrupts 430 cr4.vme = 0; // Virtual-8086 Mode Extensions 431 432 tc->setMiscReg(MISCREG_CR4, cr4); 433 434 CR4 cr8 = 0; 435 tc->setMiscReg(MISCREG_CR8, cr8); 436 437 tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 438 439 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900); 440 441 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 442 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff); 443 444 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr); 445 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 446 447 /* enabling syscall and sysret */ 448 MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32); 449 tc->setMiscReg(MISCREG_STAR, star); 450 MiscReg lstar = (MiscReg)syscallCodeVirtAddr; 451 tc->setMiscReg(MISCREG_LSTAR, lstar); 452 MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF 453 tc->setMiscReg(MISCREG_SF_MASK, sfmask); 454 } 455 456 /* Set up the content of the TSS and write it to physical memory. */ 457 458 struct { 459 uint32_t reserved0; // +00h 460 uint32_t RSP0_low; // +04h 461 uint32_t RSP0_high; // +08h 462 uint32_t RSP1_low; // +0Ch 463 uint32_t RSP1_high; // +10h 464 uint32_t RSP2_low; // +14h 465 uint32_t RSP2_high; // +18h 466 uint32_t reserved1; // +1Ch 467 uint32_t reserved2; // +20h 468 uint32_t IST1_low; // +24h 469 uint32_t IST1_high; // +28h 470 uint32_t IST2_low; // +2Ch 471 uint32_t IST2_high; // +30h 472 uint32_t IST3_low; // +34h 473 uint32_t IST3_high; // +38h 474 uint32_t IST4_low; // +3Ch 475 uint32_t IST4_high; // +40h 476 uint32_t IST5_low; // +44h 477 uint32_t IST5_high; // +48h 478 uint32_t IST6_low; // +4Ch 479 uint32_t IST6_high; // +50h 480 uint32_t IST7_low; // +54h 481 uint32_t IST7_high; // +58h 482 uint32_t reserved3; // +5Ch 483 uint32_t reserved4; // +60h 484 uint16_t reserved5; // +64h 485 uint16_t IO_MapBase; // +66h 486 } tss; 487 488 /** setting Interrupt Stack Table */ 489 uint64_t IST_start = ISTVirtAddr + PageBytes; 490 tss.IST1_low = IST_start; 491 tss.IST1_high = IST_start >> 32; 492 tss.RSP0_low = tss.IST1_low; 493 tss.RSP0_high = tss.IST1_high; 494 tss.RSP1_low = tss.IST1_low; 495 tss.RSP1_high = tss.IST1_high; 496 tss.RSP2_low = tss.IST1_low; 497 tss.RSP2_high = tss.IST1_high; 498 physProxy.writeBlob(tssPhysAddr, (uint8_t *)(&tss), sizeof(tss)); 499 500 /* Setting IDT gates */ 501 GateDescriptorLow PFGateLow = 0; 502 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16); 503 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0); 504 PFGateLow.selector = csLowPL; 505 PFGateLow.p = 1; 506 PFGateLow.dpl = 0; 507 PFGateLow.type = 0xe; // gate interrupt type 508 PFGateLow.IST = 0; // setting IST to 0 and using RSP0 509 510 GateDescriptorHigh PFGateHigh = 0; 511 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32); 512 513 struct { 514 uint64_t low; 515 uint64_t high; 516 } PFGate = {PFGateLow, PFGateHigh}; 517 518 physProxy.writeBlob(idtPhysAddr + 0xE0, 519 (uint8_t *)(&PFGate), sizeof(PFGate)); 520 521 /* System call handler */ 522 uint8_t syscallBlob[] = { 523 // mov %rax, (0xffffc90000005600) 524 0x48, 0xa3, 0x00, 0x60, 0x00, 525 0x00, 0x00, 0xc9, 0xff, 0xff, 526 // sysret 527 0x48, 0x0f, 0x07 528 }; 529 530 physProxy.writeBlob(syscallCodePhysAddr, 531 syscallBlob, sizeof(syscallBlob)); 532 533 /** Page fault handler */ 534 uint8_t faultBlob[] = { 535 // mov %rax, (0xffffc90000005700) 536 0x48, 0xa3, 0x00, 0x61, 0x00, 537 0x00, 0x00, 0xc9, 0xff, 0xff, 538 // add $0x8, %rsp # skip error 539 0x48, 0x83, 0xc4, 0x08, 540 // iretq 541 0x48, 0xcf 542 }; 543 544 physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob)); 545 546 MultiLevelPageTable<PageTableOps> *pt = 547 dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable); 548 549 /* Syscall handler */ 550 pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false); 551 /* GDT */ 552 pt->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false); 553 /* IDT */ 554 pt->map(IDTVirtAddr, idtPhysAddr, PageBytes, false); 555 /* TSS */ 556 pt->map(TSSVirtAddr, tssPhysAddr, PageBytes, false); 557 /* IST */ 558 pt->map(ISTVirtAddr, istPhysAddr, PageBytes, false); 559 /* PF handler */ 560 pt->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false); 561 /* MMIO region for m5ops */ 562 pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false); 563 } else { 564 for (int i = 0; i < contextIds.size(); i++) { 565 ThreadContext * tc = system->getThreadContext(contextIds[i]); 566 567 SegAttr dataAttr = 0; 568 dataAttr.dpl = 3; 569 dataAttr.unusable = 0; 570 dataAttr.defaultSize = 1; 571 dataAttr.longMode = 1; 572 dataAttr.avl = 0; 573 dataAttr.granularity = 1; 574 dataAttr.present = 1; 575 dataAttr.type = 3; 576 dataAttr.writable = 1; 577 dataAttr.readable = 1; 578 dataAttr.expandDown = 0; 579 dataAttr.system = 1; 580 581 // Initialize the segment registers. 582 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 583 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 584 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 585 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 586 } 587 588 SegAttr csAttr = 0; 589 csAttr.dpl = 3; 590 csAttr.unusable = 0; 591 csAttr.defaultSize = 0; 592 csAttr.longMode = 1; 593 csAttr.avl = 0; 594 csAttr.granularity = 1; 595 csAttr.present = 1; 596 csAttr.type = 10; 597 csAttr.writable = 0; 598 csAttr.readable = 1; 599 csAttr.expandDown = 0; 600 csAttr.system = 1; 601 602 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 603 604 Efer efer = 0; 605 efer.sce = 1; // Enable system call extensions. 606 efer.lme = 1; // Enable long mode. 607 efer.lma = 1; // Activate long mode. 608 efer.nxe = 1; // Enable nx support. 609 efer.svme = 0; // Disable svm support for now. It isn't implemented. 610 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 611 tc->setMiscReg(MISCREG_EFER, efer); 612 613 // Set up the registers that describe the operating mode. 614 CR0 cr0 = 0; 615 cr0.pg = 1; // Turn on paging. 616 cr0.cd = 0; // Don't disable caching. 617 cr0.nw = 0; // This is bit is defined to be ignored. 618 cr0.am = 0; // No alignment checking 619 cr0.wp = 0; // Supervisor mode can write read only pages 620 cr0.ne = 1; 621 cr0.et = 1; // This should always be 1 622 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 623 // would be pointless. 624 cr0.em = 0; // Allow x87 instructions to execute natively. 625 cr0.mp = 1; // This doesn't really matter, but the manual suggests 626 // setting it to one. 627 cr0.pe = 1; // We're definitely in protected mode. 628 tc->setMiscReg(MISCREG_CR0, cr0); 629 630 tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 631 } 632 } 633} 634 635void 636I386Process::initState() 637{ 638 X86Process::initState(); 639 640 argsInit(PageBytes); 641 642 /* 643 * Set up a GDT for this process. The whole GDT wouldn't really be for 644 * this process, but the only parts we care about are. 645 */ 646 allocateMem(_gdtStart, _gdtSize); 647 uint64_t zero = 0; 648 assert(_gdtSize % sizeof(zero) == 0); 649 for (Addr gdtCurrent = _gdtStart; 650 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) { 651 initVirtMem.write(gdtCurrent, zero); 652 } 653 654 // Set up the vsyscall page for this process. 655 allocateMem(vsyscallPage.base, vsyscallPage.size); 656 uint8_t vsyscallBlob[] = { 657 0x51, // push %ecx 658 0x52, // push %edp 659 0x55, // push %ebp 660 0x89, 0xe5, // mov %esp, %ebp 661 0x0f, 0x34 // sysenter 662 }; 663 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset, 664 vsyscallBlob, sizeof(vsyscallBlob)); 665 666 uint8_t vsysexitBlob[] = { 667 0x5d, // pop %ebp 668 0x5a, // pop %edx 669 0x59, // pop %ecx 670 0xc3 // ret 671 }; 672 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset, 673 vsysexitBlob, sizeof(vsysexitBlob)); 674 675 for (int i = 0; i < contextIds.size(); i++) { 676 ThreadContext * tc = system->getThreadContext(contextIds[i]); 677 678 SegAttr dataAttr = 0; 679 dataAttr.dpl = 3; 680 dataAttr.unusable = 0; 681 dataAttr.defaultSize = 1; 682 dataAttr.longMode = 0; 683 dataAttr.avl = 0; 684 dataAttr.granularity = 1; 685 dataAttr.present = 1; 686 dataAttr.type = 3; 687 dataAttr.writable = 1; 688 dataAttr.readable = 1; 689 dataAttr.expandDown = 0; 690 dataAttr.system = 1; 691 692 // Initialize the segment registers. 693 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 694 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 695 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 696 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 697 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB); 698 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1)); 699 } 700 701 SegAttr csAttr = 0; 702 csAttr.dpl = 3; 703 csAttr.unusable = 0; 704 csAttr.defaultSize = 1; 705 csAttr.longMode = 0; 706 csAttr.avl = 0; 707 csAttr.granularity = 1; 708 csAttr.present = 1; 709 csAttr.type = 0xa; 710 csAttr.writable = 0; 711 csAttr.readable = 1; 712 csAttr.expandDown = 0; 713 csAttr.system = 1; 714 715 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 716 717 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart); 718 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart); 719 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1); 720 721 // Set the LDT selector to 0 to deactivate it. 722 tc->setMiscRegNoEffect(MISCREG_TSL, 0); 723 724 Efer efer = 0; 725 efer.sce = 1; // Enable system call extensions. 726 efer.lme = 1; // Enable long mode. 727 efer.lma = 0; // Deactivate long mode. 728 efer.nxe = 1; // Enable nx support. 729 efer.svme = 0; // Disable svm support for now. It isn't implemented. 730 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 731 tc->setMiscReg(MISCREG_EFER, efer); 732 733 // Set up the registers that describe the operating mode. 734 CR0 cr0 = 0; 735 cr0.pg = 1; // Turn on paging. 736 cr0.cd = 0; // Don't disable caching. 737 cr0.nw = 0; // This is bit is defined to be ignored. 738 cr0.am = 0; // No alignment checking 739 cr0.wp = 0; // Supervisor mode can write read only pages 740 cr0.ne = 1; 741 cr0.et = 1; // This should always be 1 742 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 743 // would be pointless. 744 cr0.em = 0; // Allow x87 instructions to execute natively. 745 cr0.mp = 1; // This doesn't really matter, but the manual suggests 746 // setting it to one. 747 cr0.pe = 1; // We're definitely in protected mode. 748 tc->setMiscReg(MISCREG_CR0, cr0); 749 750 tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 751 } 752} 753 754template<class IntType> 755void 756X86Process::argsInit(int pageSize, 757 std::vector<AuxVector<IntType> > extraAuxvs) 758{ 759 int intSize = sizeof(IntType); 760 761 typedef AuxVector<IntType> auxv_t; 762 std::vector<auxv_t> auxv = extraAuxvs; 763 764 string filename; 765 if (argv.size() < 1) 766 filename = ""; 767 else 768 filename = argv[0]; 769 770 // We want 16 byte alignment 771 uint64_t align = 16; 772 773 // Patch the ld_bias for dynamic executables. 774 updateBias(); 775 776 // load object file into target memory 777 objFile->loadSections(initVirtMem); 778 779 enum X86CpuFeature { 780 X86_OnboardFPU = 1 << 0, 781 X86_VirtualModeExtensions = 1 << 1, 782 X86_DebuggingExtensions = 1 << 2, 783 X86_PageSizeExtensions = 1 << 3, 784 785 X86_TimeStampCounter = 1 << 4, 786 X86_ModelSpecificRegisters = 1 << 5, 787 X86_PhysicalAddressExtensions = 1 << 6, 788 X86_MachineCheckExtensions = 1 << 7, 789 790 X86_CMPXCHG8Instruction = 1 << 8, 791 X86_OnboardAPIC = 1 << 9, 792 X86_SYSENTER_SYSEXIT = 1 << 11, 793 794 X86_MemoryTypeRangeRegisters = 1 << 12, 795 X86_PageGlobalEnable = 1 << 13, 796 X86_MachineCheckArchitecture = 1 << 14, 797 X86_CMOVInstruction = 1 << 15, 798 799 X86_PageAttributeTable = 1 << 16, 800 X86_36BitPSEs = 1 << 17, 801 X86_ProcessorSerialNumber = 1 << 18, 802 X86_CLFLUSHInstruction = 1 << 19, 803 804 X86_DebugTraceStore = 1 << 21, 805 X86_ACPIViaMSR = 1 << 22, 806 X86_MultimediaExtensions = 1 << 23, 807 808 X86_FXSAVE_FXRSTOR = 1 << 24, 809 X86_StreamingSIMDExtensions = 1 << 25, 810 X86_StreamingSIMDExtensions2 = 1 << 26, 811 X86_CPUSelfSnoop = 1 << 27, 812 813 X86_HyperThreading = 1 << 28, 814 X86_AutomaticClockControl = 1 << 29, 815 X86_IA64Processor = 1 << 30 816 }; 817 818 // Setup the auxiliary vectors. These will already have endian 819 // conversion. Auxiliary vectors are loaded only for elf formatted 820 // executables; the auxv is responsible for passing information from 821 // the OS to the interpreter. 822 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 823 if (elfObject) { 824 uint64_t features = 825 X86_OnboardFPU | 826 X86_VirtualModeExtensions | 827 X86_DebuggingExtensions | 828 X86_PageSizeExtensions | 829 X86_TimeStampCounter | 830 X86_ModelSpecificRegisters | 831 X86_PhysicalAddressExtensions | 832 X86_MachineCheckExtensions | 833 X86_CMPXCHG8Instruction | 834 X86_OnboardAPIC | 835 X86_SYSENTER_SYSEXIT | 836 X86_MemoryTypeRangeRegisters | 837 X86_PageGlobalEnable | 838 X86_MachineCheckArchitecture | 839 X86_CMOVInstruction | 840 X86_PageAttributeTable | 841 X86_36BitPSEs | 842// X86_ProcessorSerialNumber | 843 X86_CLFLUSHInstruction | 844// X86_DebugTraceStore | 845// X86_ACPIViaMSR | 846 X86_MultimediaExtensions | 847 X86_FXSAVE_FXRSTOR | 848 X86_StreamingSIMDExtensions | 849 X86_StreamingSIMDExtensions2 | 850// X86_CPUSelfSnoop | 851// X86_HyperThreading | 852// X86_AutomaticClockControl | 853// X86_IA64Processor | 854 0; 855 856 // Bits which describe the system hardware capabilities 857 // XXX Figure out what these should be 858 auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 859 // The system page size 860 auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes)); 861 // Frequency at which times() increments 862 // Defined to be 100 in the kernel source. 863 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 864 // This is the virtual address of the program header tables if they 865 // appear in the executable image. 866 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 867 // This is the size of a program header entry from the elf file. 868 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 869 // This is the number of program headers from the original elf file. 870 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 871 // This is the base address of the ELF interpreter; it should be 872 // zero for static executables or contain the base address for 873 // dynamic executables. 874 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 875 // XXX Figure out what this should be. 876 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 877 // The entry point to the program 878 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 879 // Different user and group IDs 880 auxv.push_back(auxv_t(M5_AT_UID, uid())); 881 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 882 auxv.push_back(auxv_t(M5_AT_GID, gid())); 883 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 884 // Whether to enable "secure mode" in the executable 885 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 886 // The address of 16 "random" bytes. 887 auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 888 // The name of the program 889 auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 890 // The platform string 891 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 892 } 893 894 // Figure out how big the initial stack needs to be 895 896 // A sentry NULL void pointer at the top of the stack. 897 int sentry_size = intSize; 898 899 // This is the name of the file which is present on the initial stack 900 // It's purpose is to let the user space linker examine the original file. 901 int file_name_size = filename.size() + 1; 902 903 const int numRandomBytes = 16; 904 int aux_data_size = numRandomBytes; 905 906 string platform = "x86_64"; 907 aux_data_size += platform.size() + 1; 908 909 int env_data_size = 0; 910 for (int i = 0; i < envp.size(); ++i) 911 env_data_size += envp[i].size() + 1; 912 int arg_data_size = 0; 913 for (int i = 0; i < argv.size(); ++i) 914 arg_data_size += argv[i].size() + 1; 915 916 // The info_block needs to be padded so its size is a multiple of the 917 // alignment mask. Also, it appears that there needs to be at least some 918 // padding, so if the size is already a multiple, we need to increase it 919 // anyway. 920 int base_info_block_size = 921 sentry_size + file_name_size + env_data_size + arg_data_size; 922 923 int info_block_size = roundUp(base_info_block_size, align); 924 925 int info_block_padding = info_block_size - base_info_block_size; 926 927 // Each auxiliary vector is two 8 byte words 928 int aux_array_size = intSize * 2 * (auxv.size() + 1); 929 930 int envp_array_size = intSize * (envp.size() + 1); 931 int argv_array_size = intSize * (argv.size() + 1); 932 933 int argc_size = intSize; 934 935 // Figure out the size of the contents of the actual initial frame 936 int frame_size = 937 aux_array_size + 938 envp_array_size + 939 argv_array_size + 940 argc_size; 941 942 // There needs to be padding after the auxiliary vector data so that the 943 // very bottom of the stack is aligned properly. 944 int partial_size = frame_size + aux_data_size; 945 int aligned_partial_size = roundUp(partial_size, align); 946 int aux_padding = aligned_partial_size - partial_size; 947 948 int space_needed = 949 info_block_size + 950 aux_data_size + 951 aux_padding + 952 frame_size; 953 954 Addr stack_base = memState->getStackBase(); 955 956 Addr stack_min = stack_base - space_needed; 957 stack_min = roundDown(stack_min, align); 958 959 unsigned stack_size = stack_base - stack_min; 960 stack_size = roundUp(stack_size, pageSize); 961 memState->setStackSize(stack_size); 962 963 // map memory 964 Addr stack_end = roundDown(stack_base - stack_size, pageSize); 965 966 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size); 967 allocateMem(stack_end, stack_size); 968 969 // map out initial stack contents 970 IntType sentry_base = stack_base - sentry_size; 971 IntType file_name_base = sentry_base - file_name_size; 972 IntType env_data_base = file_name_base - env_data_size; 973 IntType arg_data_base = env_data_base - arg_data_size; 974 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size; 975 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding; 976 IntType envp_array_base = auxv_array_base - envp_array_size; 977 IntType argv_array_base = envp_array_base - argv_array_size; 978 IntType argc_base = argv_array_base - argc_size; 979 980 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 981 DPRINTF(Stack, "0x%x - file name\n", file_name_base); 982 DPRINTF(Stack, "0x%x - env data\n", env_data_base); 983 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 984 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 985 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 986 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 987 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 988 DPRINTF(Stack, "0x%x - argc \n", argc_base); 989 DPRINTF(Stack, "0x%x - stack min\n", stack_min); 990 991 // write contents to stack 992 993 // figure out argc 994 IntType argc = argv.size(); 995 IntType guestArgc = X86ISA::htog(argc); 996 997 // Write out the sentry void * 998 IntType sentry_NULL = 0; 999 initVirtMem.writeBlob(sentry_base, (uint8_t*)&sentry_NULL, sentry_size); 1000 1001 // Write the file name 1002 initVirtMem.writeString(file_name_base, filename.c_str()); 1003 1004 // Fix up the aux vectors which point to data 1005 assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM); 1006 auxv[auxv.size() - 3].a_val = aux_data_base; 1007 assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN); 1008 auxv[auxv.size() - 2].a_val = argv_array_base; 1009 assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM); 1010 auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes; 1011 1012 1013 // Copy the aux stuff 1014 for (int x = 0; x < auxv.size(); x++) { 1015 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 1016 (uint8_t*)&(auxv[x].a_type), intSize); 1017 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 1018 (uint8_t*)&(auxv[x].a_val), intSize); 1019 } 1020 // Write out the terminating zeroed auxiliary vector 1021 const uint64_t zero = 0; 1022 initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize, 1023 (uint8_t*)&zero, intSize); 1024 initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize, 1025 (uint8_t*)&zero, intSize); 1026 1027 initVirtMem.writeString(aux_data_base, platform.c_str()); 1028 1029 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1030 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1031 1032 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 1033 1034 ThreadContext *tc = system->getThreadContext(contextIds[0]); 1035 // Set the stack pointer register 1036 tc->setIntReg(StackPointerReg, stack_min); 1037 1038 // There doesn't need to be any segment base added in since we're dealing 1039 // with the flat segmentation model. 1040 tc->pcState(getStartPC()); 1041 1042 // Align the "stack_min" to a page boundary. 1043 memState->setStackMin(roundDown(stack_min, pageSize)); 1044} 1045 1046void 1047X86_64Process::argsInit(int pageSize) 1048{ 1049 std::vector<AuxVector<uint64_t> > extraAuxvs; 1050 extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR, 1051 vsyscallPage.base)); 1052 X86Process::argsInit<uint64_t>(pageSize, extraAuxvs); 1053} 1054 1055void 1056I386Process::argsInit(int pageSize) 1057{ 1058 std::vector<AuxVector<uint32_t> > extraAuxvs; 1059 //Tell the binary where the vsyscall part of the vsyscall page is. 1060 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO, 1061 vsyscallPage.base + vsyscallPage.vsyscallOffset)); 1062 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR, 1063 vsyscallPage.base)); 1064 X86Process::argsInit<uint32_t>(pageSize, extraAuxvs); 1065} 1066 1067void 1068X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval) 1069{ 1070 tc->setIntReg(INTREG_RAX, retval.encodedValue()); 1071} 1072 1073X86ISA::IntReg 1074X86_64Process::getSyscallArg(ThreadContext *tc, int &i) 1075{ 1076 assert(i < NumArgumentRegs); 1077 return tc->readIntReg(ArgumentReg[i++]); 1078} 1079 1080void 1081X86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 1082{ 1083 assert(i < NumArgumentRegs); 1084 return tc->setIntReg(ArgumentReg[i], val); 1085} 1086 1087void 1088X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, 1089 Process *p, TheISA::IntReg flags) 1090{ 1091 X86Process::clone(old_tc, new_tc, p, flags); 1092 ((X86_64Process*)p)->vsyscallPage = vsyscallPage; 1093} 1094 1095X86ISA::IntReg 1096I386Process::getSyscallArg(ThreadContext *tc, int &i) 1097{ 1098 assert(i < NumArgumentRegs32); 1099 return tc->readIntReg(ArgumentReg32[i++]); 1100} 1101 1102X86ISA::IntReg 1103I386Process::getSyscallArg(ThreadContext *tc, int &i, int width) 1104{ 1105 assert(width == 32 || width == 64); 1106 assert(i < NumArgumentRegs); 1107 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32); 1108 if (width == 64) 1109 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32); 1110 return retVal; 1111} 1112 1113void 1114I386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 1115{ 1116 assert(i < NumArgumentRegs); 1117 return tc->setIntReg(ArgumentReg[i], val); 1118} 1119 1120void 1121I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, 1122 Process *p, TheISA::IntReg flags) 1123{ 1124 X86Process::clone(old_tc, new_tc, p, flags); 1125 ((I386Process*)p)->vsyscallPage = vsyscallPage; 1126} 1127