process.cc revision 11800:54436a1784dc
1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2007 The Hewlett-Packard Development Company 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2003-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Gabe Black 42 * Ali Saidi 43 */ 44 45#include "arch/x86/process.hh" 46 47#include "arch/x86/isa_traits.hh" 48#include "arch/x86/regs/misc.hh" 49#include "arch/x86/regs/segment.hh" 50#include "arch/x86/system.hh" 51#include "arch/x86/types.hh" 52#include "base/loader/elf_object.hh" 53#include "base/loader/object_file.hh" 54#include "base/misc.hh" 55#include "base/trace.hh" 56#include "cpu/thread_context.hh" 57#include "debug/Stack.hh" 58#include "mem/multi_level_page_table.hh" 59#include "mem/page_table.hh" 60#include "sim/process_impl.hh" 61#include "sim/syscall_desc.hh" 62#include "sim/syscall_return.hh" 63#include "sim/system.hh" 64 65using namespace std; 66using namespace X86ISA; 67 68static const int ArgumentReg[] = { 69 INTREG_RDI, 70 INTREG_RSI, 71 INTREG_RDX, 72 //This argument register is r10 for syscalls and rcx for C. 73 INTREG_R10W, 74 //INTREG_RCX, 75 INTREG_R8W, 76 INTREG_R9W 77}; 78 79static const int NumArgumentRegs M5_VAR_USED = 80 sizeof(ArgumentReg) / sizeof(const int); 81 82static const int ArgumentReg32[] = { 83 INTREG_EBX, 84 INTREG_ECX, 85 INTREG_EDX, 86 INTREG_ESI, 87 INTREG_EDI, 88 INTREG_EBP 89}; 90 91static const int NumArgumentRegs32 M5_VAR_USED = 92 sizeof(ArgumentReg) / sizeof(const int); 93 94X86LiveProcess::X86LiveProcess(LiveProcessParams * params, ObjectFile *objFile, 95 SyscallDesc *_syscallDescs, int _numSyscallDescs) : 96 LiveProcess(params, objFile), syscallDescs(_syscallDescs), 97 numSyscallDescs(_numSyscallDescs) 98{ 99 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 100 brk_point = roundUp(brk_point, PageBytes); 101} 102 103X86_64LiveProcess::X86_64LiveProcess(LiveProcessParams *params, 104 ObjectFile *objFile, SyscallDesc *_syscallDescs, 105 int _numSyscallDescs) : 106 X86LiveProcess(params, objFile, _syscallDescs, _numSyscallDescs) 107{ 108 109 vsyscallPage.base = 0xffffffffff600000ULL; 110 vsyscallPage.size = PageBytes; 111 vsyscallPage.vtimeOffset = 0x400; 112 vsyscallPage.vgettimeofdayOffset = 0x0; 113 114 // Set up stack. On X86_64 Linux, stack goes from the top of memory 115 // downward, less the hole for the kernel address space plus one page 116 // for undertermined purposes. 117 stack_base = (Addr)0x7FFFFFFFF000ULL; 118 119 // Set pointer for next thread stack. Reserve 8M for main stack. 120 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 121 122 // "mmap_base" is a function which defines where mmap region starts in 123 // the process address space. 124 // mmap_base: PAGE_ALIGN(TASK_SIZE-MIN_GAP-mmap_rnd()) 125 // TASK_SIZE: (1<<47)-PAGE_SIZE 126 // MIN_GAP: 128*1024*1024+stack_maxrandom_size() 127 // We do not use any address space layout randomization in gem5 128 // therefore the random fields become zero; the smallest gap space was 129 // chosen but gap could potentially be much larger. 130 mmap_end = (Addr)0x7FFFF7FFF000ULL; 131} 132 133void 134I386LiveProcess::syscall(int64_t callnum, ThreadContext *tc) 135{ 136 TheISA::PCState pc = tc->pcState(); 137 Addr eip = pc.pc(); 138 if (eip >= vsyscallPage.base && 139 eip < vsyscallPage.base + vsyscallPage.size) { 140 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset); 141 tc->pcState(pc); 142 } 143 X86LiveProcess::syscall(callnum, tc); 144} 145 146 147I386LiveProcess::I386LiveProcess(LiveProcessParams *params, 148 ObjectFile *objFile, SyscallDesc *_syscallDescs, 149 int _numSyscallDescs) : 150 X86LiveProcess(params, objFile, _syscallDescs, _numSyscallDescs) 151{ 152 _gdtStart = ULL(0xffffd000); 153 _gdtSize = PageBytes; 154 155 vsyscallPage.base = 0xffffe000ULL; 156 vsyscallPage.size = PageBytes; 157 vsyscallPage.vsyscallOffset = 0x400; 158 vsyscallPage.vsysexitOffset = 0x410; 159 160 stack_base = _gdtStart; 161 162 // Set pointer for next thread stack. Reserve 8M for main stack. 163 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 164 165 // "mmap_base" is a function which defines where mmap region starts in 166 // the process address space. 167 // mmap_base: PAGE_ALIGN(TASK_SIZE-MIN_GAP-mmap_rnd()) 168 // TASK_SIZE: 0xC0000000 169 // MIN_GAP: 128*1024*1024+stack_maxrandom_size() 170 // We do not use any address space layout randomization in gem5 171 // therefore the random fields become zero; the smallest gap space was 172 // chosen but gap could potentially be much larger. 173 mmap_end = (Addr)0xB7FFF000ULL; 174} 175 176SyscallDesc* 177X86LiveProcess::getDesc(int callnum) 178{ 179 if (callnum < 0 || callnum >= numSyscallDescs) 180 return NULL; 181 return &syscallDescs[callnum]; 182} 183 184void 185X86_64LiveProcess::initState() 186{ 187 X86LiveProcess::initState(); 188 189 argsInit(sizeof(uint64_t), PageBytes); 190 191 // Set up the vsyscall page for this process. 192 allocateMem(vsyscallPage.base, vsyscallPage.size); 193 uint8_t vtimeBlob[] = { 194 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax 195 0x0f,0x05, // syscall 196 0xc3 // retq 197 }; 198 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset, 199 vtimeBlob, sizeof(vtimeBlob)); 200 201 uint8_t vgettimeofdayBlob[] = { 202 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax 203 0x0f,0x05, // syscall 204 0xc3 // retq 205 }; 206 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset, 207 vgettimeofdayBlob, sizeof(vgettimeofdayBlob)); 208 209 if (kvmInSE) { 210 PortProxy physProxy = system->physProxy; 211 212 /* 213 * Set up the gdt. 214 */ 215 uint8_t numGDTEntries = 0; 216 uint64_t nullDescriptor = 0; 217 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 218 (uint8_t *)(&nullDescriptor), 8); 219 numGDTEntries++; 220 221 SegDescriptor initDesc = 0; 222 initDesc.type.codeOrData = 0; // code or data type 223 initDesc.type.c = 0; // conforming 224 initDesc.type.r = 1; // readable 225 initDesc.dpl = 0; // privilege 226 initDesc.p = 1; // present 227 initDesc.l = 1; // longmode - 64 bit 228 initDesc.d = 0; // operand size 229 initDesc.g = 1; // granularity 230 initDesc.s = 1; // system segment 231 initDesc.limitHigh = 0xFFFF; 232 initDesc.limitLow = 0xF; 233 initDesc.baseHigh = 0x0; 234 initDesc.baseLow = 0x0; 235 236 //64 bit code segment 237 SegDescriptor csLowPLDesc = initDesc; 238 csLowPLDesc.type.codeOrData = 1; 239 csLowPLDesc.dpl = 0; 240 uint64_t csLowPLDescVal = csLowPLDesc; 241 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 242 (uint8_t *)(&csLowPLDescVal), 8); 243 244 numGDTEntries++; 245 246 SegSelector csLowPL = 0; 247 csLowPL.si = numGDTEntries - 1; 248 csLowPL.rpl = 0; 249 250 //64 bit data segment 251 SegDescriptor dsLowPLDesc = initDesc; 252 dsLowPLDesc.type.codeOrData = 0; 253 dsLowPLDesc.dpl = 0; 254 uint64_t dsLowPLDescVal = dsLowPLDesc; 255 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 256 (uint8_t *)(&dsLowPLDescVal), 8); 257 258 numGDTEntries++; 259 260 SegSelector dsLowPL = 0; 261 dsLowPL.si = numGDTEntries - 1; 262 dsLowPL.rpl = 0; 263 264 //64 bit data segment 265 SegDescriptor dsDesc = initDesc; 266 dsDesc.type.codeOrData = 0; 267 dsDesc.dpl = 3; 268 uint64_t dsDescVal = dsDesc; 269 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 270 (uint8_t *)(&dsDescVal), 8); 271 272 numGDTEntries++; 273 274 SegSelector ds = 0; 275 ds.si = numGDTEntries - 1; 276 ds.rpl = 3; 277 278 //64 bit code segment 279 SegDescriptor csDesc = initDesc; 280 csDesc.type.codeOrData = 1; 281 csDesc.dpl = 3; 282 uint64_t csDescVal = csDesc; 283 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 284 (uint8_t *)(&csDescVal), 8); 285 286 numGDTEntries++; 287 288 SegSelector cs = 0; 289 cs.si = numGDTEntries - 1; 290 cs.rpl = 3; 291 292 SegSelector scall = 0; 293 scall.si = csLowPL.si; 294 scall.rpl = 0; 295 296 SegSelector sret = 0; 297 sret.si = dsLowPL.si; 298 sret.rpl = 3; 299 300 /* In long mode the TSS has been extended to 16 Bytes */ 301 TSSlow TSSDescLow = 0; 302 TSSDescLow.type = 0xB; 303 TSSDescLow.dpl = 0; // Privelege level 0 304 TSSDescLow.p = 1; // Present 305 TSSDescLow.g = 1; // Page granularity 306 TSSDescLow.limitHigh = 0xF; 307 TSSDescLow.limitLow = 0xFFFF; 308 TSSDescLow.baseLow = bits(TSSVirtAddr, 23, 0); 309 TSSDescLow.baseHigh = bits(TSSVirtAddr, 31, 24); 310 311 TSShigh TSSDescHigh = 0; 312 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32); 313 314 struct TSSDesc { 315 uint64_t low; 316 uint64_t high; 317 } tssDescVal = {TSSDescLow, TSSDescHigh}; 318 319 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 320 (uint8_t *)(&tssDescVal), sizeof(tssDescVal)); 321 322 numGDTEntries++; 323 324 SegSelector tssSel = 0; 325 tssSel.si = numGDTEntries - 1; 326 327 uint64_t tss_base_addr = (TSSDescHigh.base << 32) | 328 (TSSDescLow.baseHigh << 24) | 329 TSSDescLow.baseLow; 330 uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16); 331 332 SegAttr tss_attr = 0; 333 334 tss_attr.type = TSSDescLow.type; 335 tss_attr.dpl = TSSDescLow.dpl; 336 tss_attr.present = TSSDescLow.p; 337 tss_attr.granularity = TSSDescLow.g; 338 tss_attr.unusable = 0; 339 340 for (int i = 0; i < contextIds.size(); i++) { 341 ThreadContext * tc = system->getThreadContext(contextIds[i]); 342 343 tc->setMiscReg(MISCREG_CS, cs); 344 tc->setMiscReg(MISCREG_DS, ds); 345 tc->setMiscReg(MISCREG_ES, ds); 346 tc->setMiscReg(MISCREG_FS, ds); 347 tc->setMiscReg(MISCREG_GS, ds); 348 tc->setMiscReg(MISCREG_SS, ds); 349 350 // LDT 351 tc->setMiscReg(MISCREG_TSL, 0); 352 SegAttr tslAttr = 0; 353 tslAttr.present = 1; 354 tslAttr.type = 2; 355 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr); 356 357 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 358 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 359 360 tc->setMiscReg(MISCREG_TR, tssSel); 361 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr); 362 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0); 363 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit); 364 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr); 365 366 //Start using longmode segments. 367 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 368 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 369 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 370 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 371 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 372 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 373 374 Efer efer = 0; 375 efer.sce = 1; // Enable system call extensions. 376 efer.lme = 1; // Enable long mode. 377 efer.lma = 1; // Activate long mode. 378 efer.nxe = 0; // Enable nx support. 379 efer.svme = 1; // Enable svm support for now. 380 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor. 381 tc->setMiscReg(MISCREG_EFER, efer); 382 383 //Set up the registers that describe the operating mode. 384 CR0 cr0 = 0; 385 cr0.pg = 1; // Turn on paging. 386 cr0.cd = 0; // Don't disable caching. 387 cr0.nw = 0; // This is bit is defined to be ignored. 388 cr0.am = 1; // No alignment checking 389 cr0.wp = 1; // Supervisor mode can write read only pages 390 cr0.ne = 1; 391 cr0.et = 1; // This should always be 1 392 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 393 // would be pointless. 394 cr0.em = 0; // Allow x87 instructions to execute natively. 395 cr0.mp = 1; // This doesn't really matter, but the manual suggests 396 // setting it to one. 397 cr0.pe = 1; // We're definitely in protected mode. 398 tc->setMiscReg(MISCREG_CR0, cr0); 399 400 CR0 cr2 = 0; 401 tc->setMiscReg(MISCREG_CR2, cr2); 402 403 CR3 cr3 = pageTablePhysAddr; 404 tc->setMiscReg(MISCREG_CR3, cr3); 405 406 CR4 cr4 = 0; 407 //Turn on pae. 408 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States 409 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception 410 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support 411 cr4.pce = 0; // Performance-Monitoring Counter Enable 412 cr4.pge = 0; // Page-Global Enable 413 cr4.mce = 0; // Machine Check Enable 414 cr4.pae = 1; // Physical-Address Extension 415 cr4.pse = 0; // Page Size Extensions 416 cr4.de = 0; // Debugging Extensions 417 cr4.tsd = 0; // Time Stamp Disable 418 cr4.pvi = 0; // Protected-Mode Virtual Interrupts 419 cr4.vme = 0; // Virtual-8086 Mode Extensions 420 421 tc->setMiscReg(MISCREG_CR4, cr4); 422 423 CR4 cr8 = 0; 424 tc->setMiscReg(MISCREG_CR8, cr8); 425 426 const Addr PageMapLevel4 = pageTablePhysAddr; 427 //Point to the page tables. 428 tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 429 430 tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 431 432 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900); 433 434 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 435 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff); 436 437 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr); 438 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 439 440 /* enabling syscall and sysret */ 441 MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32); 442 tc->setMiscReg(MISCREG_STAR, star); 443 MiscReg lstar = (MiscReg)syscallCodeVirtAddr; 444 tc->setMiscReg(MISCREG_LSTAR, lstar); 445 MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF 446 tc->setMiscReg(MISCREG_SF_MASK, sfmask); 447 } 448 449 /* Set up the content of the TSS and write it to physical memory. */ 450 451 struct { 452 uint32_t reserved0; // +00h 453 uint32_t RSP0_low; // +04h 454 uint32_t RSP0_high; // +08h 455 uint32_t RSP1_low; // +0Ch 456 uint32_t RSP1_high; // +10h 457 uint32_t RSP2_low; // +14h 458 uint32_t RSP2_high; // +18h 459 uint32_t reserved1; // +1Ch 460 uint32_t reserved2; // +20h 461 uint32_t IST1_low; // +24h 462 uint32_t IST1_high; // +28h 463 uint32_t IST2_low; // +2Ch 464 uint32_t IST2_high; // +30h 465 uint32_t IST3_low; // +34h 466 uint32_t IST3_high; // +38h 467 uint32_t IST4_low; // +3Ch 468 uint32_t IST4_high; // +40h 469 uint32_t IST5_low; // +44h 470 uint32_t IST5_high; // +48h 471 uint32_t IST6_low; // +4Ch 472 uint32_t IST6_high; // +50h 473 uint32_t IST7_low; // +54h 474 uint32_t IST7_high; // +58h 475 uint32_t reserved3; // +5Ch 476 uint32_t reserved4; // +60h 477 uint16_t reserved5; // +64h 478 uint16_t IO_MapBase; // +66h 479 } tss; 480 481 /** setting Interrupt Stack Table */ 482 uint64_t IST_start = ISTVirtAddr + PageBytes; 483 tss.IST1_low = IST_start; 484 tss.IST1_high = IST_start >> 32; 485 tss.RSP0_low = tss.IST1_low; 486 tss.RSP0_high = tss.IST1_high; 487 tss.RSP1_low = tss.IST1_low; 488 tss.RSP1_high = tss.IST1_high; 489 tss.RSP2_low = tss.IST1_low; 490 tss.RSP2_high = tss.IST1_high; 491 physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss)); 492 493 /* Setting IDT gates */ 494 GateDescriptorLow PFGateLow = 0; 495 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16); 496 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0); 497 PFGateLow.selector = csLowPL; 498 PFGateLow.p = 1; 499 PFGateLow.dpl = 0; 500 PFGateLow.type = 0xe; // gate interrupt type 501 PFGateLow.IST = 0; // setting IST to 0 and using RSP0 502 503 GateDescriptorHigh PFGateHigh = 0; 504 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32); 505 506 struct { 507 uint64_t low; 508 uint64_t high; 509 } PFGate = {PFGateLow, PFGateHigh}; 510 511 physProxy.writeBlob(IDTPhysAddr + 0xE0, 512 (uint8_t *)(&PFGate), sizeof(PFGate)); 513 514 /* System call handler */ 515 uint8_t syscallBlob[] = { 516 // mov %rax, (0xffffc90000005600) 517 0x48, 0xa3, 0x00, 0x60, 0x00, 518 0x00, 0x00, 0xc9, 0xff, 0xff, 519 // sysret 520 0x48, 0x0f, 0x07 521 }; 522 523 physProxy.writeBlob(syscallCodePhysAddr, 524 syscallBlob, sizeof(syscallBlob)); 525 526 /** Page fault handler */ 527 uint8_t faultBlob[] = { 528 // mov %rax, (0xffffc90000005700) 529 0x48, 0xa3, 0x00, 0x61, 0x00, 530 0x00, 0x00, 0xc9, 0xff, 0xff, 531 // add $0x8, %rsp # skip error 532 0x48, 0x83, 0xc4, 0x08, 533 // iretq 534 0x48, 0xcf 535 }; 536 537 physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob)); 538 539 MultiLevelPageTable<PageTableOps> *pt = 540 dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable); 541 542 /* Syscall handler */ 543 pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false); 544 /* GDT */ 545 pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false); 546 /* IDT */ 547 pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false); 548 /* TSS */ 549 pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false); 550 /* IST */ 551 pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false); 552 /* PF handler */ 553 pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false); 554 /* MMIO region for m5ops */ 555 pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false); 556 } else { 557 for (int i = 0; i < contextIds.size(); i++) { 558 ThreadContext * tc = system->getThreadContext(contextIds[i]); 559 560 SegAttr dataAttr = 0; 561 dataAttr.dpl = 3; 562 dataAttr.unusable = 0; 563 dataAttr.defaultSize = 1; 564 dataAttr.longMode = 1; 565 dataAttr.avl = 0; 566 dataAttr.granularity = 1; 567 dataAttr.present = 1; 568 dataAttr.type = 3; 569 dataAttr.writable = 1; 570 dataAttr.readable = 1; 571 dataAttr.expandDown = 0; 572 dataAttr.system = 1; 573 574 //Initialize the segment registers. 575 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 576 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 577 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 578 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 579 } 580 581 SegAttr csAttr = 0; 582 csAttr.dpl = 3; 583 csAttr.unusable = 0; 584 csAttr.defaultSize = 0; 585 csAttr.longMode = 1; 586 csAttr.avl = 0; 587 csAttr.granularity = 1; 588 csAttr.present = 1; 589 csAttr.type = 10; 590 csAttr.writable = 0; 591 csAttr.readable = 1; 592 csAttr.expandDown = 0; 593 csAttr.system = 1; 594 595 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 596 597 Efer efer = 0; 598 efer.sce = 1; // Enable system call extensions. 599 efer.lme = 1; // Enable long mode. 600 efer.lma = 1; // Activate long mode. 601 efer.nxe = 1; // Enable nx support. 602 efer.svme = 0; // Disable svm support for now. It isn't implemented. 603 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 604 tc->setMiscReg(MISCREG_EFER, efer); 605 606 //Set up the registers that describe the operating mode. 607 CR0 cr0 = 0; 608 cr0.pg = 1; // Turn on paging. 609 cr0.cd = 0; // Don't disable caching. 610 cr0.nw = 0; // This is bit is defined to be ignored. 611 cr0.am = 0; // No alignment checking 612 cr0.wp = 0; // Supervisor mode can write read only pages 613 cr0.ne = 1; 614 cr0.et = 1; // This should always be 1 615 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 616 // would be pointless. 617 cr0.em = 0; // Allow x87 instructions to execute natively. 618 cr0.mp = 1; // This doesn't really matter, but the manual suggests 619 // setting it to one. 620 cr0.pe = 1; // We're definitely in protected mode. 621 tc->setMiscReg(MISCREG_CR0, cr0); 622 623 tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 624 } 625 } 626} 627 628void 629I386LiveProcess::initState() 630{ 631 X86LiveProcess::initState(); 632 633 argsInit(sizeof(uint32_t), PageBytes); 634 635 /* 636 * Set up a GDT for this process. The whole GDT wouldn't really be for 637 * this process, but the only parts we care about are. 638 */ 639 allocateMem(_gdtStart, _gdtSize); 640 uint64_t zero = 0; 641 assert(_gdtSize % sizeof(zero) == 0); 642 for (Addr gdtCurrent = _gdtStart; 643 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) { 644 initVirtMem.write(gdtCurrent, zero); 645 } 646 647 // Set up the vsyscall page for this process. 648 allocateMem(vsyscallPage.base, vsyscallPage.size); 649 uint8_t vsyscallBlob[] = { 650 0x51, // push %ecx 651 0x52, // push %edp 652 0x55, // push %ebp 653 0x89, 0xe5, // mov %esp, %ebp 654 0x0f, 0x34 // sysenter 655 }; 656 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset, 657 vsyscallBlob, sizeof(vsyscallBlob)); 658 659 uint8_t vsysexitBlob[] = { 660 0x5d, // pop %ebp 661 0x5a, // pop %edx 662 0x59, // pop %ecx 663 0xc3 // ret 664 }; 665 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset, 666 vsysexitBlob, sizeof(vsysexitBlob)); 667 668 for (int i = 0; i < contextIds.size(); i++) { 669 ThreadContext * tc = system->getThreadContext(contextIds[i]); 670 671 SegAttr dataAttr = 0; 672 dataAttr.dpl = 3; 673 dataAttr.unusable = 0; 674 dataAttr.defaultSize = 1; 675 dataAttr.longMode = 0; 676 dataAttr.avl = 0; 677 dataAttr.granularity = 1; 678 dataAttr.present = 1; 679 dataAttr.type = 3; 680 dataAttr.writable = 1; 681 dataAttr.readable = 1; 682 dataAttr.expandDown = 0; 683 dataAttr.system = 1; 684 685 //Initialize the segment registers. 686 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 687 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 688 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 689 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 690 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB); 691 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1)); 692 } 693 694 SegAttr csAttr = 0; 695 csAttr.dpl = 3; 696 csAttr.unusable = 0; 697 csAttr.defaultSize = 1; 698 csAttr.longMode = 0; 699 csAttr.avl = 0; 700 csAttr.granularity = 1; 701 csAttr.present = 1; 702 csAttr.type = 0xa; 703 csAttr.writable = 0; 704 csAttr.readable = 1; 705 csAttr.expandDown = 0; 706 csAttr.system = 1; 707 708 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 709 710 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart); 711 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart); 712 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1); 713 714 // Set the LDT selector to 0 to deactivate it. 715 tc->setMiscRegNoEffect(MISCREG_TSL, 0); 716 717 Efer efer = 0; 718 efer.sce = 1; // Enable system call extensions. 719 efer.lme = 1; // Enable long mode. 720 efer.lma = 0; // Deactivate long mode. 721 efer.nxe = 1; // Enable nx support. 722 efer.svme = 0; // Disable svm support for now. It isn't implemented. 723 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 724 tc->setMiscReg(MISCREG_EFER, efer); 725 726 //Set up the registers that describe the operating mode. 727 CR0 cr0 = 0; 728 cr0.pg = 1; // Turn on paging. 729 cr0.cd = 0; // Don't disable caching. 730 cr0.nw = 0; // This is bit is defined to be ignored. 731 cr0.am = 0; // No alignment checking 732 cr0.wp = 0; // Supervisor mode can write read only pages 733 cr0.ne = 1; 734 cr0.et = 1; // This should always be 1 735 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 736 // would be pointless. 737 cr0.em = 0; // Allow x87 instructions to execute natively. 738 cr0.mp = 1; // This doesn't really matter, but the manual suggests 739 // setting it to one. 740 cr0.pe = 1; // We're definitely in protected mode. 741 tc->setMiscReg(MISCREG_CR0, cr0); 742 743 tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 744 } 745} 746 747template<class IntType> 748void 749X86LiveProcess::argsInit(int pageSize, 750 std::vector<AuxVector<IntType> > extraAuxvs) 751{ 752 int intSize = sizeof(IntType); 753 754 typedef AuxVector<IntType> auxv_t; 755 std::vector<auxv_t> auxv = extraAuxvs; 756 757 string filename; 758 if (argv.size() < 1) 759 filename = ""; 760 else 761 filename = argv[0]; 762 763 //We want 16 byte alignment 764 uint64_t align = 16; 765 766 // Patch the ld_bias for dynamic executables. 767 updateBias(); 768 769 // load object file into target memory 770 objFile->loadSections(initVirtMem); 771 772 enum X86CpuFeature { 773 X86_OnboardFPU = 1 << 0, 774 X86_VirtualModeExtensions = 1 << 1, 775 X86_DebuggingExtensions = 1 << 2, 776 X86_PageSizeExtensions = 1 << 3, 777 778 X86_TimeStampCounter = 1 << 4, 779 X86_ModelSpecificRegisters = 1 << 5, 780 X86_PhysicalAddressExtensions = 1 << 6, 781 X86_MachineCheckExtensions = 1 << 7, 782 783 X86_CMPXCHG8Instruction = 1 << 8, 784 X86_OnboardAPIC = 1 << 9, 785 X86_SYSENTER_SYSEXIT = 1 << 11, 786 787 X86_MemoryTypeRangeRegisters = 1 << 12, 788 X86_PageGlobalEnable = 1 << 13, 789 X86_MachineCheckArchitecture = 1 << 14, 790 X86_CMOVInstruction = 1 << 15, 791 792 X86_PageAttributeTable = 1 << 16, 793 X86_36BitPSEs = 1 << 17, 794 X86_ProcessorSerialNumber = 1 << 18, 795 X86_CLFLUSHInstruction = 1 << 19, 796 797 X86_DebugTraceStore = 1 << 21, 798 X86_ACPIViaMSR = 1 << 22, 799 X86_MultimediaExtensions = 1 << 23, 800 801 X86_FXSAVE_FXRSTOR = 1 << 24, 802 X86_StreamingSIMDExtensions = 1 << 25, 803 X86_StreamingSIMDExtensions2 = 1 << 26, 804 X86_CPUSelfSnoop = 1 << 27, 805 806 X86_HyperThreading = 1 << 28, 807 X86_AutomaticClockControl = 1 << 29, 808 X86_IA64Processor = 1 << 30 809 }; 810 811 // Setup the auxiliary vectors. These will already have endian 812 // conversion. Auxiliary vectors are loaded only for elf formatted 813 // executables; the auxv is responsible for passing information from 814 // the OS to the interpreter. 815 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 816 if (elfObject) { 817 uint64_t features = 818 X86_OnboardFPU | 819 X86_VirtualModeExtensions | 820 X86_DebuggingExtensions | 821 X86_PageSizeExtensions | 822 X86_TimeStampCounter | 823 X86_ModelSpecificRegisters | 824 X86_PhysicalAddressExtensions | 825 X86_MachineCheckExtensions | 826 X86_CMPXCHG8Instruction | 827 X86_OnboardAPIC | 828 X86_SYSENTER_SYSEXIT | 829 X86_MemoryTypeRangeRegisters | 830 X86_PageGlobalEnable | 831 X86_MachineCheckArchitecture | 832 X86_CMOVInstruction | 833 X86_PageAttributeTable | 834 X86_36BitPSEs | 835// X86_ProcessorSerialNumber | 836 X86_CLFLUSHInstruction | 837// X86_DebugTraceStore | 838// X86_ACPIViaMSR | 839 X86_MultimediaExtensions | 840 X86_FXSAVE_FXRSTOR | 841 X86_StreamingSIMDExtensions | 842 X86_StreamingSIMDExtensions2 | 843// X86_CPUSelfSnoop | 844// X86_HyperThreading | 845// X86_AutomaticClockControl | 846// X86_IA64Processor | 847 0; 848 849 //Bits which describe the system hardware capabilities 850 //XXX Figure out what these should be 851 auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 852 //The system page size 853 auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes)); 854 //Frequency at which times() increments 855 //Defined to be 100 in the kernel source. 856 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 857 // This is the virtual address of the program header tables if they 858 // appear in the executable image. 859 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 860 // This is the size of a program header entry from the elf file. 861 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 862 // This is the number of program headers from the original elf file. 863 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 864 // This is the base address of the ELF interpreter; it should be 865 // zero for static executables or contain the base address for 866 // dynamic executables. 867 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 868 //XXX Figure out what this should be. 869 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 870 //The entry point to the program 871 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 872 //Different user and group IDs 873 auxv.push_back(auxv_t(M5_AT_UID, uid())); 874 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 875 auxv.push_back(auxv_t(M5_AT_GID, gid())); 876 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 877 //Whether to enable "secure mode" in the executable 878 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 879 //The address of 16 "random" bytes. 880 auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 881 //The name of the program 882 auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 883 //The platform string 884 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 885 } 886 887 //Figure out how big the initial stack needs to be 888 889 // A sentry NULL void pointer at the top of the stack. 890 int sentry_size = intSize; 891 892 //This is the name of the file which is present on the initial stack 893 //It's purpose is to let the user space linker examine the original file. 894 int file_name_size = filename.size() + 1; 895 896 const int numRandomBytes = 16; 897 int aux_data_size = numRandomBytes; 898 899 string platform = "x86_64"; 900 aux_data_size += platform.size() + 1; 901 902 int env_data_size = 0; 903 for (int i = 0; i < envp.size(); ++i) 904 env_data_size += envp[i].size() + 1; 905 int arg_data_size = 0; 906 for (int i = 0; i < argv.size(); ++i) 907 arg_data_size += argv[i].size() + 1; 908 909 //The info_block needs to be padded so it's size is a multiple of the 910 //alignment mask. Also, it appears that there needs to be at least some 911 //padding, so if the size is already a multiple, we need to increase it 912 //anyway. 913 int base_info_block_size = 914 sentry_size + file_name_size + env_data_size + arg_data_size; 915 916 int info_block_size = roundUp(base_info_block_size, align); 917 918 int info_block_padding = info_block_size - base_info_block_size; 919 920 //Each auxilliary vector is two 8 byte words 921 int aux_array_size = intSize * 2 * (auxv.size() + 1); 922 923 int envp_array_size = intSize * (envp.size() + 1); 924 int argv_array_size = intSize * (argv.size() + 1); 925 926 int argc_size = intSize; 927 928 //Figure out the size of the contents of the actual initial frame 929 int frame_size = 930 aux_array_size + 931 envp_array_size + 932 argv_array_size + 933 argc_size; 934 935 //There needs to be padding after the auxiliary vector data so that the 936 //very bottom of the stack is aligned properly. 937 int partial_size = frame_size + aux_data_size; 938 int aligned_partial_size = roundUp(partial_size, align); 939 int aux_padding = aligned_partial_size - partial_size; 940 941 int space_needed = 942 info_block_size + 943 aux_data_size + 944 aux_padding + 945 frame_size; 946 947 stack_min = stack_base - space_needed; 948 stack_min = roundDown(stack_min, align); 949 stack_size = roundUp(stack_base - stack_min, pageSize); 950 951 // map memory 952 Addr stack_end = roundDown(stack_base - stack_size, pageSize); 953 954 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size); 955 allocateMem(stack_end, stack_size); 956 957 // map out initial stack contents 958 IntType sentry_base = stack_base - sentry_size; 959 IntType file_name_base = sentry_base - file_name_size; 960 IntType env_data_base = file_name_base - env_data_size; 961 IntType arg_data_base = env_data_base - arg_data_size; 962 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size; 963 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding; 964 IntType envp_array_base = auxv_array_base - envp_array_size; 965 IntType argv_array_base = envp_array_base - argv_array_size; 966 IntType argc_base = argv_array_base - argc_size; 967 968 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 969 DPRINTF(Stack, "0x%x - file name\n", file_name_base); 970 DPRINTF(Stack, "0x%x - env data\n", env_data_base); 971 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 972 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 973 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 974 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 975 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 976 DPRINTF(Stack, "0x%x - argc \n", argc_base); 977 DPRINTF(Stack, "0x%x - stack min\n", stack_min); 978 979 // write contents to stack 980 981 // figure out argc 982 IntType argc = argv.size(); 983 IntType guestArgc = X86ISA::htog(argc); 984 985 //Write out the sentry void * 986 IntType sentry_NULL = 0; 987 initVirtMem.writeBlob(sentry_base, 988 (uint8_t*)&sentry_NULL, sentry_size); 989 990 //Write the file name 991 initVirtMem.writeString(file_name_base, filename.c_str()); 992 993 //Fix up the aux vectors which point to data 994 assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM); 995 auxv[auxv.size() - 3].a_val = aux_data_base; 996 assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN); 997 auxv[auxv.size() - 2].a_val = argv_array_base; 998 assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM); 999 auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes; 1000 1001 //Copy the aux stuff 1002 for (int x = 0; x < auxv.size(); x++) { 1003 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 1004 (uint8_t*)&(auxv[x].a_type), intSize); 1005 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 1006 (uint8_t*)&(auxv[x].a_val), intSize); 1007 } 1008 //Write out the terminating zeroed auxilliary vector 1009 const uint64_t zero = 0; 1010 initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize, 1011 (uint8_t*)&zero, intSize); 1012 initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize, 1013 (uint8_t*)&zero, intSize); 1014 1015 initVirtMem.writeString(aux_data_base, platform.c_str()); 1016 1017 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1018 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1019 1020 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 1021 1022 ThreadContext *tc = system->getThreadContext(contextIds[0]); 1023 //Set the stack pointer register 1024 tc->setIntReg(StackPointerReg, stack_min); 1025 1026 // There doesn't need to be any segment base added in since we're dealing 1027 // with the flat segmentation model. 1028 tc->pcState(getStartPC()); 1029 1030 //Align the "stack_min" to a page boundary. 1031 stack_min = roundDown(stack_min, pageSize); 1032 1033// num_processes++; 1034} 1035 1036void 1037X86_64LiveProcess::argsInit(int intSize, int pageSize) 1038{ 1039 std::vector<AuxVector<uint64_t> > extraAuxvs; 1040 extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR, 1041 vsyscallPage.base)); 1042 X86LiveProcess::argsInit<uint64_t>(pageSize, extraAuxvs); 1043} 1044 1045void 1046I386LiveProcess::argsInit(int intSize, int pageSize) 1047{ 1048 std::vector<AuxVector<uint32_t> > extraAuxvs; 1049 //Tell the binary where the vsyscall part of the vsyscall page is. 1050 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO, 1051 vsyscallPage.base + vsyscallPage.vsyscallOffset)); 1052 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR, 1053 vsyscallPage.base)); 1054 X86LiveProcess::argsInit<uint32_t>(pageSize, extraAuxvs); 1055} 1056 1057void 1058X86LiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn retval) 1059{ 1060 tc->setIntReg(INTREG_RAX, retval.encodedValue()); 1061} 1062 1063X86ISA::IntReg 1064X86_64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 1065{ 1066 assert(i < NumArgumentRegs); 1067 return tc->readIntReg(ArgumentReg[i++]); 1068} 1069 1070void 1071X86_64LiveProcess::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 1072{ 1073 assert(i < NumArgumentRegs); 1074 return tc->setIntReg(ArgumentReg[i], val); 1075} 1076 1077X86ISA::IntReg 1078I386LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 1079{ 1080 assert(i < NumArgumentRegs32); 1081 return tc->readIntReg(ArgumentReg32[i++]); 1082} 1083 1084X86ISA::IntReg 1085I386LiveProcess::getSyscallArg(ThreadContext *tc, int &i, int width) 1086{ 1087 assert(width == 32 || width == 64); 1088 assert(i < NumArgumentRegs); 1089 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32); 1090 if (width == 64) 1091 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32); 1092 return retVal; 1093} 1094 1095void 1096I386LiveProcess::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 1097{ 1098 assert(i < NumArgumentRegs); 1099 return tc->setIntReg(ArgumentReg[i], val); 1100} 1101