process.cc revision 13613
14166Sgblack@eecs.umich.edu/* 210554Salexandru.dutu@amd.com * Copyright (c) 2014 Advanced Micro Devices, Inc. 37087Snate@binkert.org * Copyright (c) 2007 The Hewlett-Packard Development Company 47087Snate@binkert.org * All rights reserved. 57087Snate@binkert.org * 67087Snate@binkert.org * The license below extends only to copyright in the software and shall 77087Snate@binkert.org * not be construed as granting a license to any other intellectual 87087Snate@binkert.org * property including but not limited to intellectual property relating 97087Snate@binkert.org * to a hardware implementation of the functionality of the software 107087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 117087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 127087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 137087Snate@binkert.org * modified or unmodified, in source code or in binary form. 147087Snate@binkert.org * 154166Sgblack@eecs.umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 164166Sgblack@eecs.umich.edu * All rights reserved. 174166Sgblack@eecs.umich.edu * 184166Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 194166Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 204166Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 214166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 224166Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 234166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 244166Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 254166Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 264166Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 274166Sgblack@eecs.umich.edu * this software without specific prior written permission. 284166Sgblack@eecs.umich.edu * 294166Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304166Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314166Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324166Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334166Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344166Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354166Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364166Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374166Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384166Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394166Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404166Sgblack@eecs.umich.edu * 414166Sgblack@eecs.umich.edu * Authors: Gabe Black 424166Sgblack@eecs.umich.edu * Ali Saidi 434166Sgblack@eecs.umich.edu */ 444166Sgblack@eecs.umich.edu 4511793Sbrandon.potter@amd.com#include "arch/x86/process.hh" 4611793Sbrandon.potter@amd.com 4711854Sbrandon.potter@amd.com#include <string> 4811854Sbrandon.potter@amd.com#include <vector> 4911854Sbrandon.potter@amd.com 5011793Sbrandon.potter@amd.com#include "arch/x86/isa_traits.hh" 518229Snate@binkert.org#include "arch/x86/regs/misc.hh" 528229Snate@binkert.org#include "arch/x86/regs/segment.hh" 5310554Salexandru.dutu@amd.com#include "arch/x86/system.hh" 544166Sgblack@eecs.umich.edu#include "arch/x86/types.hh" 558229Snate@binkert.org#include "base/loader/elf_object.hh" 564166Sgblack@eecs.umich.edu#include "base/loader/object_file.hh" 5712334Sgabeblack@google.com#include "base/logging.hh" 585004Sgblack@eecs.umich.edu#include "base/trace.hh" 594166Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 608232Snate@binkert.org#include "debug/Stack.hh" 6110554Salexandru.dutu@amd.com#include "mem/multi_level_page_table.hh" 624166Sgblack@eecs.umich.edu#include "mem/page_table.hh" 6312431Sgabeblack@google.com#include "params/Process.hh" 6411854Sbrandon.potter@amd.com#include "sim/aux_vector.hh" 654434Ssaidi@eecs.umich.edu#include "sim/process_impl.hh" 6611794Sbrandon.potter@amd.com#include "sim/syscall_desc.hh" 6711800Sbrandon.potter@amd.com#include "sim/syscall_return.hh" 684166Sgblack@eecs.umich.edu#include "sim/system.hh" 694166Sgblack@eecs.umich.edu 704166Sgblack@eecs.umich.eduusing namespace std; 714166Sgblack@eecs.umich.eduusing namespace X86ISA; 724166Sgblack@eecs.umich.edu 735958Sgblack@eecs.umich.edustatic const int ArgumentReg[] = { 745958Sgblack@eecs.umich.edu INTREG_RDI, 755958Sgblack@eecs.umich.edu INTREG_RSI, 765958Sgblack@eecs.umich.edu INTREG_RDX, 7711906SBrandon.Potter@amd.com // This argument register is r10 for syscalls and rcx for C. 785958Sgblack@eecs.umich.edu INTREG_R10W, 7911906SBrandon.Potter@amd.com // INTREG_RCX, 805958Sgblack@eecs.umich.edu INTREG_R8W, 815958Sgblack@eecs.umich.edu INTREG_R9W 825958Sgblack@eecs.umich.edu}; 8311704Santhony.gutierrez@amd.com 8411704Santhony.gutierrez@amd.comstatic const int NumArgumentRegs M5_VAR_USED = 8511704Santhony.gutierrez@amd.com sizeof(ArgumentReg) / sizeof(const int); 8611704Santhony.gutierrez@amd.com 875959Sgblack@eecs.umich.edustatic const int ArgumentReg32[] = { 885959Sgblack@eecs.umich.edu INTREG_EBX, 895959Sgblack@eecs.umich.edu INTREG_ECX, 905959Sgblack@eecs.umich.edu INTREG_EDX, 915959Sgblack@eecs.umich.edu INTREG_ESI, 925959Sgblack@eecs.umich.edu INTREG_EDI, 9311385Sbrandon.potter@amd.com INTREG_EBP 945959Sgblack@eecs.umich.edu}; 9511704Santhony.gutierrez@amd.com 9611704Santhony.gutierrez@amd.comstatic const int NumArgumentRegs32 M5_VAR_USED = 9711704Santhony.gutierrez@amd.com sizeof(ArgumentReg) / sizeof(const int); 984166Sgblack@eecs.umich.edu 9912460Sgabeblack@google.comtemplate class MultiLevelPageTable<LongModePTE<47, 39>, 10012460Sgabeblack@google.com LongModePTE<38, 30>, 10112460Sgabeblack@google.com LongModePTE<29, 21>, 10212460Sgabeblack@google.com LongModePTE<20, 12> >; 10312460Sgabeblack@google.comtypedef MultiLevelPageTable<LongModePTE<47, 39>, 10412460Sgabeblack@google.com LongModePTE<38, 30>, 10512460Sgabeblack@google.com LongModePTE<29, 21>, 10612460Sgabeblack@google.com LongModePTE<20, 12> > ArchPageTable; 10712460Sgabeblack@google.com 10812431Sgabeblack@google.comX86Process::X86Process(ProcessParams *params, ObjectFile *objFile, 10911851Sbrandon.potter@amd.com SyscallDesc *_syscallDescs, int _numSyscallDescs) 11012431Sgabeblack@google.com : Process(params, params->useArchPT ? 11112448Sgabeblack@google.com static_cast<EmulationPageTable *>( 11212460Sgabeblack@google.com new ArchPageTable(params->name, params->pid, 11312460Sgabeblack@google.com params->system, PageBytes)) : 11412448Sgabeblack@google.com new EmulationPageTable(params->name, params->pid, 11512448Sgabeblack@google.com PageBytes), 11612431Sgabeblack@google.com objFile), 11712431Sgabeblack@google.com syscallDescs(_syscallDescs), numSyscallDescs(_numSyscallDescs) 1184166Sgblack@eecs.umich.edu{ 11911886Sbrandon.potter@amd.com} 12011886Sbrandon.potter@amd.com 12111886Sbrandon.potter@amd.comvoid X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, 12213613Sgabeblack@google.com Process *p, RegVal flags) 12311886Sbrandon.potter@amd.com{ 12411886Sbrandon.potter@amd.com Process::clone(old_tc, new_tc, p, flags); 12511886Sbrandon.potter@amd.com X86Process *process = (X86Process*)p; 12611886Sbrandon.potter@amd.com *process = *this; 1275956Sgblack@eecs.umich.edu} 1284166Sgblack@eecs.umich.edu 12911851Sbrandon.potter@amd.comX86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile, 13011851Sbrandon.potter@amd.com SyscallDesc *_syscallDescs, int _numSyscallDescs) 13111851Sbrandon.potter@amd.com : X86Process(params, objFile, _syscallDescs, _numSyscallDescs) 1325956Sgblack@eecs.umich.edu{ 1336709Svince@csl.cornell.edu 1346709Svince@csl.cornell.edu vsyscallPage.base = 0xffffffffff600000ULL; 13510318Sandreas.hansson@arm.com vsyscallPage.size = PageBytes; 1366709Svince@csl.cornell.edu vsyscallPage.vtimeOffset = 0x400; 1379679Smjleven@sandia.gov vsyscallPage.vgettimeofdayOffset = 0x0; 1386709Svince@csl.cornell.edu 13911905SBrandon.Potter@amd.com Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 14011905SBrandon.Potter@amd.com objFile->bssSize(), PageBytes); 14111905SBrandon.Potter@amd.com Addr stack_base = 0x7FFFFFFFF000ULL; 14211905SBrandon.Potter@amd.com Addr max_stack_size = 8 * 1024 * 1024; 14311905SBrandon.Potter@amd.com Addr next_thread_stack_base = stack_base - max_stack_size; 14411905SBrandon.Potter@amd.com Addr mmap_end = 0x7FFFF7FFF000ULL; 1454166Sgblack@eecs.umich.edu 14611905SBrandon.Potter@amd.com memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 14711905SBrandon.Potter@amd.com next_thread_stack_base, mmap_end); 1484166Sgblack@eecs.umich.edu} 1494166Sgblack@eecs.umich.edu 1505973Sgblack@eecs.umich.eduvoid 15111877Sbrandon.potter@amd.comI386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault) 1525973Sgblack@eecs.umich.edu{ 1537720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 1547720Sgblack@eecs.umich.edu Addr eip = pc.pc(); 1555973Sgblack@eecs.umich.edu if (eip >= vsyscallPage.base && 1565973Sgblack@eecs.umich.edu eip < vsyscallPage.base + vsyscallPage.size) { 1577720Sgblack@eecs.umich.edu pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset); 1587720Sgblack@eecs.umich.edu tc->pcState(pc); 1595973Sgblack@eecs.umich.edu } 16011877Sbrandon.potter@amd.com X86Process::syscall(callnum, tc, fault); 1615973Sgblack@eecs.umich.edu} 1625973Sgblack@eecs.umich.edu 1635973Sgblack@eecs.umich.edu 16411851Sbrandon.potter@amd.comI386Process::I386Process(ProcessParams *params, ObjectFile *objFile, 16511851Sbrandon.potter@amd.com SyscallDesc *_syscallDescs, int _numSyscallDescs) 16611851Sbrandon.potter@amd.com : X86Process(params, objFile, _syscallDescs, _numSyscallDescs) 1674166Sgblack@eecs.umich.edu{ 1689026Sgblack@eecs.umich.edu _gdtStart = ULL(0xffffd000); 16910318Sandreas.hansson@arm.com _gdtSize = PageBytes; 1705973Sgblack@eecs.umich.edu 1715973Sgblack@eecs.umich.edu vsyscallPage.base = 0xffffe000ULL; 17210318Sandreas.hansson@arm.com vsyscallPage.size = PageBytes; 1735973Sgblack@eecs.umich.edu vsyscallPage.vsyscallOffset = 0x400; 1745973Sgblack@eecs.umich.edu vsyscallPage.vsysexitOffset = 0x410; 1755973Sgblack@eecs.umich.edu 17611905SBrandon.Potter@amd.com Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 17711905SBrandon.Potter@amd.com objFile->bssSize(), PageBytes); 17811905SBrandon.Potter@amd.com Addr stack_base = _gdtStart; 17911905SBrandon.Potter@amd.com Addr max_stack_size = 8 * 1024 * 1024; 18011905SBrandon.Potter@amd.com Addr next_thread_stack_base = stack_base - max_stack_size; 18111905SBrandon.Potter@amd.com Addr mmap_end = 0xB7FFF000ULL; 1825956Sgblack@eecs.umich.edu 18311905SBrandon.Potter@amd.com memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 18411905SBrandon.Potter@amd.com next_thread_stack_base, mmap_end); 1855956Sgblack@eecs.umich.edu} 1865956Sgblack@eecs.umich.edu 1875956Sgblack@eecs.umich.eduSyscallDesc* 18811851Sbrandon.potter@amd.comX86Process::getDesc(int callnum) 1895956Sgblack@eecs.umich.edu{ 1905956Sgblack@eecs.umich.edu if (callnum < 0 || callnum >= numSyscallDescs) 1915956Sgblack@eecs.umich.edu return NULL; 1925956Sgblack@eecs.umich.edu return &syscallDescs[callnum]; 1934166Sgblack@eecs.umich.edu} 1944166Sgblack@eecs.umich.edu 1954166Sgblack@eecs.umich.eduvoid 19611851Sbrandon.potter@amd.comX86_64Process::initState() 1974166Sgblack@eecs.umich.edu{ 19811851Sbrandon.potter@amd.com X86Process::initState(); 1995183Ssaidi@eecs.umich.edu 20011884Sbrandon.potter@amd.com argsInit(PageBytes); 2015140Sgblack@eecs.umich.edu 20211906SBrandon.Potter@amd.com // Set up the vsyscall page for this process. 2038601Ssteve.reinhardt@amd.com allocateMem(vsyscallPage.base, vsyscallPage.size); 2046709Svince@csl.cornell.edu uint8_t vtimeBlob[] = { 2056709Svince@csl.cornell.edu 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax 2066709Svince@csl.cornell.edu 0x0f,0x05, // syscall 2076709Svince@csl.cornell.edu 0xc3 // retq 2086709Svince@csl.cornell.edu }; 2098852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset, 2106709Svince@csl.cornell.edu vtimeBlob, sizeof(vtimeBlob)); 2116709Svince@csl.cornell.edu 2126709Svince@csl.cornell.edu uint8_t vgettimeofdayBlob[] = { 2136709Svince@csl.cornell.edu 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax 2146709Svince@csl.cornell.edu 0x0f,0x05, // syscall 2156709Svince@csl.cornell.edu 0xc3 // retq 2166709Svince@csl.cornell.edu }; 2178852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset, 2186709Svince@csl.cornell.edu vgettimeofdayBlob, sizeof(vgettimeofdayBlob)); 2196709Svince@csl.cornell.edu 22010554Salexandru.dutu@amd.com if (kvmInSE) { 22110554Salexandru.dutu@amd.com PortProxy physProxy = system->physProxy; 2225140Sgblack@eecs.umich.edu 22312458Sgabeblack@google.com Addr syscallCodePhysAddr = system->allocPhysPages(1); 22412458Sgabeblack@google.com Addr gdtPhysAddr = system->allocPhysPages(1); 22512458Sgabeblack@google.com Addr idtPhysAddr = system->allocPhysPages(1); 22612458Sgabeblack@google.com Addr istPhysAddr = system->allocPhysPages(1); 22712458Sgabeblack@google.com Addr tssPhysAddr = system->allocPhysPages(1); 22812458Sgabeblack@google.com Addr pfHandlerPhysAddr = system->allocPhysPages(1); 22912458Sgabeblack@google.com 23010554Salexandru.dutu@amd.com /* 23110554Salexandru.dutu@amd.com * Set up the gdt. 23210554Salexandru.dutu@amd.com */ 23310554Salexandru.dutu@amd.com uint8_t numGDTEntries = 0; 23410554Salexandru.dutu@amd.com uint64_t nullDescriptor = 0; 23512458Sgabeblack@google.com physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 23610554Salexandru.dutu@amd.com (uint8_t *)(&nullDescriptor), 8); 23710554Salexandru.dutu@amd.com numGDTEntries++; 2385140Sgblack@eecs.umich.edu 23910554Salexandru.dutu@amd.com SegDescriptor initDesc = 0; 24010554Salexandru.dutu@amd.com initDesc.type.codeOrData = 0; // code or data type 24110554Salexandru.dutu@amd.com initDesc.type.c = 0; // conforming 24210554Salexandru.dutu@amd.com initDesc.type.r = 1; // readable 24310554Salexandru.dutu@amd.com initDesc.dpl = 0; // privilege 24410554Salexandru.dutu@amd.com initDesc.p = 1; // present 24510554Salexandru.dutu@amd.com initDesc.l = 1; // longmode - 64 bit 24610554Salexandru.dutu@amd.com initDesc.d = 0; // operand size 24710554Salexandru.dutu@amd.com initDesc.s = 1; // system segment 24812588Sgabeblack@google.com initDesc.limit = 0xFFFFFFFF; 24912588Sgabeblack@google.com initDesc.base = 0; 25010554Salexandru.dutu@amd.com 25110554Salexandru.dutu@amd.com //64 bit code segment 25210554Salexandru.dutu@amd.com SegDescriptor csLowPLDesc = initDesc; 25310554Salexandru.dutu@amd.com csLowPLDesc.type.codeOrData = 1; 25410554Salexandru.dutu@amd.com csLowPLDesc.dpl = 0; 25510554Salexandru.dutu@amd.com uint64_t csLowPLDescVal = csLowPLDesc; 25612458Sgabeblack@google.com physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 25710554Salexandru.dutu@amd.com (uint8_t *)(&csLowPLDescVal), 8); 25810554Salexandru.dutu@amd.com 25910554Salexandru.dutu@amd.com numGDTEntries++; 26010554Salexandru.dutu@amd.com 26110554Salexandru.dutu@amd.com SegSelector csLowPL = 0; 26210554Salexandru.dutu@amd.com csLowPL.si = numGDTEntries - 1; 26310554Salexandru.dutu@amd.com csLowPL.rpl = 0; 26410554Salexandru.dutu@amd.com 26510554Salexandru.dutu@amd.com //64 bit data segment 26610554Salexandru.dutu@amd.com SegDescriptor dsLowPLDesc = initDesc; 26710554Salexandru.dutu@amd.com dsLowPLDesc.type.codeOrData = 0; 26810554Salexandru.dutu@amd.com dsLowPLDesc.dpl = 0; 26910554Salexandru.dutu@amd.com uint64_t dsLowPLDescVal = dsLowPLDesc; 27012458Sgabeblack@google.com physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 27110554Salexandru.dutu@amd.com (uint8_t *)(&dsLowPLDescVal), 8); 27210554Salexandru.dutu@amd.com 27310554Salexandru.dutu@amd.com numGDTEntries++; 27410554Salexandru.dutu@amd.com 27510554Salexandru.dutu@amd.com SegSelector dsLowPL = 0; 27610554Salexandru.dutu@amd.com dsLowPL.si = numGDTEntries - 1; 27710554Salexandru.dutu@amd.com dsLowPL.rpl = 0; 27810554Salexandru.dutu@amd.com 27910554Salexandru.dutu@amd.com //64 bit data segment 28010554Salexandru.dutu@amd.com SegDescriptor dsDesc = initDesc; 28110554Salexandru.dutu@amd.com dsDesc.type.codeOrData = 0; 28210554Salexandru.dutu@amd.com dsDesc.dpl = 3; 28310554Salexandru.dutu@amd.com uint64_t dsDescVal = dsDesc; 28412458Sgabeblack@google.com physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 28510554Salexandru.dutu@amd.com (uint8_t *)(&dsDescVal), 8); 28610554Salexandru.dutu@amd.com 28710554Salexandru.dutu@amd.com numGDTEntries++; 28810554Salexandru.dutu@amd.com 28910554Salexandru.dutu@amd.com SegSelector ds = 0; 29010554Salexandru.dutu@amd.com ds.si = numGDTEntries - 1; 29110554Salexandru.dutu@amd.com ds.rpl = 3; 29210554Salexandru.dutu@amd.com 29310554Salexandru.dutu@amd.com //64 bit code segment 29410554Salexandru.dutu@amd.com SegDescriptor csDesc = initDesc; 29510554Salexandru.dutu@amd.com csDesc.type.codeOrData = 1; 29610554Salexandru.dutu@amd.com csDesc.dpl = 3; 29710554Salexandru.dutu@amd.com uint64_t csDescVal = csDesc; 29812458Sgabeblack@google.com physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 29910554Salexandru.dutu@amd.com (uint8_t *)(&csDescVal), 8); 30010554Salexandru.dutu@amd.com 30110554Salexandru.dutu@amd.com numGDTEntries++; 30210554Salexandru.dutu@amd.com 30310554Salexandru.dutu@amd.com SegSelector cs = 0; 30410554Salexandru.dutu@amd.com cs.si = numGDTEntries - 1; 30510554Salexandru.dutu@amd.com cs.rpl = 3; 30610554Salexandru.dutu@amd.com 30710554Salexandru.dutu@amd.com SegSelector scall = 0; 30810554Salexandru.dutu@amd.com scall.si = csLowPL.si; 30910554Salexandru.dutu@amd.com scall.rpl = 0; 31010554Salexandru.dutu@amd.com 31110554Salexandru.dutu@amd.com SegSelector sret = 0; 31210554Salexandru.dutu@amd.com sret.si = dsLowPL.si; 31310554Salexandru.dutu@amd.com sret.rpl = 3; 31410554Salexandru.dutu@amd.com 31510554Salexandru.dutu@amd.com /* In long mode the TSS has been extended to 16 Bytes */ 31610554Salexandru.dutu@amd.com TSSlow TSSDescLow = 0; 31710554Salexandru.dutu@amd.com TSSDescLow.type = 0xB; 31810554Salexandru.dutu@amd.com TSSDescLow.dpl = 0; // Privelege level 0 31910554Salexandru.dutu@amd.com TSSDescLow.p = 1; // Present 32012588Sgabeblack@google.com TSSDescLow.limit = 0xFFFFFFFF; 32112588Sgabeblack@google.com TSSDescLow.base = bits(TSSVirtAddr, 31, 0); 32210554Salexandru.dutu@amd.com 32310554Salexandru.dutu@amd.com TSShigh TSSDescHigh = 0; 32410590Sgabeblack@google.com TSSDescHigh.base = bits(TSSVirtAddr, 63, 32); 32510554Salexandru.dutu@amd.com 32610554Salexandru.dutu@amd.com struct TSSDesc { 32710554Salexandru.dutu@amd.com uint64_t low; 32810554Salexandru.dutu@amd.com uint64_t high; 32910554Salexandru.dutu@amd.com } tssDescVal = {TSSDescLow, TSSDescHigh}; 33010554Salexandru.dutu@amd.com 33112458Sgabeblack@google.com physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8, 33210554Salexandru.dutu@amd.com (uint8_t *)(&tssDescVal), sizeof(tssDescVal)); 33310554Salexandru.dutu@amd.com 33410554Salexandru.dutu@amd.com numGDTEntries++; 33510554Salexandru.dutu@amd.com 33610554Salexandru.dutu@amd.com SegSelector tssSel = 0; 33710554Salexandru.dutu@amd.com tssSel.si = numGDTEntries - 1; 33810554Salexandru.dutu@amd.com 33912588Sgabeblack@google.com uint64_t tss_base_addr = (TSSDescHigh.base << 32) | TSSDescLow.base; 34012588Sgabeblack@google.com uint64_t tss_limit = TSSDescLow.limit; 34110554Salexandru.dutu@amd.com 34210554Salexandru.dutu@amd.com SegAttr tss_attr = 0; 34310554Salexandru.dutu@amd.com 34410554Salexandru.dutu@amd.com tss_attr.type = TSSDescLow.type; 34510554Salexandru.dutu@amd.com tss_attr.dpl = TSSDescLow.dpl; 34610554Salexandru.dutu@amd.com tss_attr.present = TSSDescLow.p; 34710554Salexandru.dutu@amd.com tss_attr.granularity = TSSDescLow.g; 34810554Salexandru.dutu@amd.com tss_attr.unusable = 0; 34910554Salexandru.dutu@amd.com 35010554Salexandru.dutu@amd.com for (int i = 0; i < contextIds.size(); i++) { 35110554Salexandru.dutu@amd.com ThreadContext * tc = system->getThreadContext(contextIds[i]); 35210554Salexandru.dutu@amd.com 35310590Sgabeblack@google.com tc->setMiscReg(MISCREG_CS, cs); 35410590Sgabeblack@google.com tc->setMiscReg(MISCREG_DS, ds); 35510590Sgabeblack@google.com tc->setMiscReg(MISCREG_ES, ds); 35610590Sgabeblack@google.com tc->setMiscReg(MISCREG_FS, ds); 35710590Sgabeblack@google.com tc->setMiscReg(MISCREG_GS, ds); 35810590Sgabeblack@google.com tc->setMiscReg(MISCREG_SS, ds); 35910554Salexandru.dutu@amd.com 36010554Salexandru.dutu@amd.com // LDT 36110554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSL, 0); 36210554Salexandru.dutu@amd.com SegAttr tslAttr = 0; 36310554Salexandru.dutu@amd.com tslAttr.present = 1; 36410554Salexandru.dutu@amd.com tslAttr.type = 2; 36510554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr); 36610554Salexandru.dutu@amd.com 36710554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 36810554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 36910554Salexandru.dutu@amd.com 37010590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR, tssSel); 37110590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr); 37210590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR_EFF_BASE, 0); 37310590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit); 37410590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR_ATTR, tss_attr); 37510554Salexandru.dutu@amd.com 37610554Salexandru.dutu@amd.com //Start using longmode segments. 37710554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 37810554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 37910554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 38010554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 38110554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 38210554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 38310554Salexandru.dutu@amd.com 38410554Salexandru.dutu@amd.com Efer efer = 0; 38510554Salexandru.dutu@amd.com efer.sce = 1; // Enable system call extensions. 38610554Salexandru.dutu@amd.com efer.lme = 1; // Enable long mode. 38710554Salexandru.dutu@amd.com efer.lma = 1; // Activate long mode. 38810554Salexandru.dutu@amd.com efer.nxe = 0; // Enable nx support. 38910554Salexandru.dutu@amd.com efer.svme = 1; // Enable svm support for now. 39010554Salexandru.dutu@amd.com efer.ffxsr = 0; // Turn on fast fxsave and fxrstor. 39110554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_EFER, efer); 39210554Salexandru.dutu@amd.com 39310554Salexandru.dutu@amd.com //Set up the registers that describe the operating mode. 39410554Salexandru.dutu@amd.com CR0 cr0 = 0; 39510554Salexandru.dutu@amd.com cr0.pg = 1; // Turn on paging. 39610554Salexandru.dutu@amd.com cr0.cd = 0; // Don't disable caching. 39710554Salexandru.dutu@amd.com cr0.nw = 0; // This is bit is defined to be ignored. 39810554Salexandru.dutu@amd.com cr0.am = 1; // No alignment checking 39910554Salexandru.dutu@amd.com cr0.wp = 1; // Supervisor mode can write read only pages 40010554Salexandru.dutu@amd.com cr0.ne = 1; 40110554Salexandru.dutu@amd.com cr0.et = 1; // This should always be 1 40210554Salexandru.dutu@amd.com cr0.ts = 0; // We don't do task switching, so causing fp exceptions 40310554Salexandru.dutu@amd.com // would be pointless. 40410554Salexandru.dutu@amd.com cr0.em = 0; // Allow x87 instructions to execute natively. 40510554Salexandru.dutu@amd.com cr0.mp = 1; // This doesn't really matter, but the manual suggests 40610554Salexandru.dutu@amd.com // setting it to one. 40710554Salexandru.dutu@amd.com cr0.pe = 1; // We're definitely in protected mode. 40810554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR0, cr0); 40910554Salexandru.dutu@amd.com 41010554Salexandru.dutu@amd.com CR0 cr2 = 0; 41110554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR2, cr2); 41210554Salexandru.dutu@amd.com 41312458Sgabeblack@google.com CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr(); 41410554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR3, cr3); 41510554Salexandru.dutu@amd.com 41610554Salexandru.dutu@amd.com CR4 cr4 = 0; 41710554Salexandru.dutu@amd.com //Turn on pae. 41810554Salexandru.dutu@amd.com cr4.osxsave = 1; // Enable XSAVE and Proc Extended States 41910554Salexandru.dutu@amd.com cr4.osxmmexcpt = 1; // Operating System Unmasked Exception 42010554Salexandru.dutu@amd.com cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support 42110554Salexandru.dutu@amd.com cr4.pce = 0; // Performance-Monitoring Counter Enable 42210554Salexandru.dutu@amd.com cr4.pge = 0; // Page-Global Enable 42310554Salexandru.dutu@amd.com cr4.mce = 0; // Machine Check Enable 42410554Salexandru.dutu@amd.com cr4.pae = 1; // Physical-Address Extension 42510554Salexandru.dutu@amd.com cr4.pse = 0; // Page Size Extensions 42610554Salexandru.dutu@amd.com cr4.de = 0; // Debugging Extensions 42710554Salexandru.dutu@amd.com cr4.tsd = 0; // Time Stamp Disable 42810554Salexandru.dutu@amd.com cr4.pvi = 0; // Protected-Mode Virtual Interrupts 42910554Salexandru.dutu@amd.com cr4.vme = 0; // Virtual-8086 Mode Extensions 43010554Salexandru.dutu@amd.com 43110554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR4, cr4); 43210554Salexandru.dutu@amd.com 43310554Salexandru.dutu@amd.com CR4 cr8 = 0; 43410554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR8, cr8); 43510554Salexandru.dutu@amd.com 43610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 43710554Salexandru.dutu@amd.com 43810554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900); 43910554Salexandru.dutu@amd.com 44010590Sgabeblack@google.com tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 44110590Sgabeblack@google.com tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff); 44210554Salexandru.dutu@amd.com 44310590Sgabeblack@google.com tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr); 44410590Sgabeblack@google.com tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 44510554Salexandru.dutu@amd.com 44610554Salexandru.dutu@amd.com /* enabling syscall and sysret */ 44713613Sgabeblack@google.com RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32); 44810554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_STAR, star); 44913613Sgabeblack@google.com RegVal lstar = (RegVal)syscallCodeVirtAddr; 45010554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_LSTAR, lstar); 45113613Sgabeblack@google.com RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF 45210554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SF_MASK, sfmask); 4535140Sgblack@eecs.umich.edu } 4545140Sgblack@eecs.umich.edu 45510590Sgabeblack@google.com /* Set up the content of the TSS and write it to physical memory. */ 4565140Sgblack@eecs.umich.edu 45710554Salexandru.dutu@amd.com struct { 45810554Salexandru.dutu@amd.com uint32_t reserved0; // +00h 45910554Salexandru.dutu@amd.com uint32_t RSP0_low; // +04h 46010554Salexandru.dutu@amd.com uint32_t RSP0_high; // +08h 46110554Salexandru.dutu@amd.com uint32_t RSP1_low; // +0Ch 46210554Salexandru.dutu@amd.com uint32_t RSP1_high; // +10h 46310554Salexandru.dutu@amd.com uint32_t RSP2_low; // +14h 46410554Salexandru.dutu@amd.com uint32_t RSP2_high; // +18h 46510554Salexandru.dutu@amd.com uint32_t reserved1; // +1Ch 46610554Salexandru.dutu@amd.com uint32_t reserved2; // +20h 46710554Salexandru.dutu@amd.com uint32_t IST1_low; // +24h 46810554Salexandru.dutu@amd.com uint32_t IST1_high; // +28h 46910554Salexandru.dutu@amd.com uint32_t IST2_low; // +2Ch 47010554Salexandru.dutu@amd.com uint32_t IST2_high; // +30h 47110554Salexandru.dutu@amd.com uint32_t IST3_low; // +34h 47210554Salexandru.dutu@amd.com uint32_t IST3_high; // +38h 47310554Salexandru.dutu@amd.com uint32_t IST4_low; // +3Ch 47410554Salexandru.dutu@amd.com uint32_t IST4_high; // +40h 47510554Salexandru.dutu@amd.com uint32_t IST5_low; // +44h 47610554Salexandru.dutu@amd.com uint32_t IST5_high; // +48h 47710554Salexandru.dutu@amd.com uint32_t IST6_low; // +4Ch 47810554Salexandru.dutu@amd.com uint32_t IST6_high; // +50h 47910554Salexandru.dutu@amd.com uint32_t IST7_low; // +54h 48010554Salexandru.dutu@amd.com uint32_t IST7_high; // +58h 48110554Salexandru.dutu@amd.com uint32_t reserved3; // +5Ch 48210554Salexandru.dutu@amd.com uint32_t reserved4; // +60h 48310554Salexandru.dutu@amd.com uint16_t reserved5; // +64h 48410554Salexandru.dutu@amd.com uint16_t IO_MapBase; // +66h 48510554Salexandru.dutu@amd.com } tss; 4865140Sgblack@eecs.umich.edu 48710554Salexandru.dutu@amd.com /** setting Interrupt Stack Table */ 48810554Salexandru.dutu@amd.com uint64_t IST_start = ISTVirtAddr + PageBytes; 48910590Sgabeblack@google.com tss.IST1_low = IST_start; 49010590Sgabeblack@google.com tss.IST1_high = IST_start >> 32; 49110554Salexandru.dutu@amd.com tss.RSP0_low = tss.IST1_low; 49210554Salexandru.dutu@amd.com tss.RSP0_high = tss.IST1_high; 49310554Salexandru.dutu@amd.com tss.RSP1_low = tss.IST1_low; 49410554Salexandru.dutu@amd.com tss.RSP1_high = tss.IST1_high; 49510554Salexandru.dutu@amd.com tss.RSP2_low = tss.IST1_low; 49610554Salexandru.dutu@amd.com tss.RSP2_high = tss.IST1_high; 49712458Sgabeblack@google.com physProxy.writeBlob(tssPhysAddr, (uint8_t *)(&tss), sizeof(tss)); 4986140Sgblack@eecs.umich.edu 49910554Salexandru.dutu@amd.com /* Setting IDT gates */ 50010554Salexandru.dutu@amd.com GateDescriptorLow PFGateLow = 0; 50110590Sgabeblack@google.com PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16); 50210590Sgabeblack@google.com PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0); 50310590Sgabeblack@google.com PFGateLow.selector = csLowPL; 50410554Salexandru.dutu@amd.com PFGateLow.p = 1; 50510554Salexandru.dutu@amd.com PFGateLow.dpl = 0; 50610554Salexandru.dutu@amd.com PFGateLow.type = 0xe; // gate interrupt type 50710554Salexandru.dutu@amd.com PFGateLow.IST = 0; // setting IST to 0 and using RSP0 5086609Sgblack@eecs.umich.edu 50910554Salexandru.dutu@amd.com GateDescriptorHigh PFGateHigh = 0; 51010590Sgabeblack@google.com PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32); 51110554Salexandru.dutu@amd.com 51210554Salexandru.dutu@amd.com struct { 51310554Salexandru.dutu@amd.com uint64_t low; 51410554Salexandru.dutu@amd.com uint64_t high; 51510554Salexandru.dutu@amd.com } PFGate = {PFGateLow, PFGateHigh}; 51610554Salexandru.dutu@amd.com 51712458Sgabeblack@google.com physProxy.writeBlob(idtPhysAddr + 0xE0, 51810554Salexandru.dutu@amd.com (uint8_t *)(&PFGate), sizeof(PFGate)); 51910554Salexandru.dutu@amd.com 52010590Sgabeblack@google.com /* System call handler */ 52110554Salexandru.dutu@amd.com uint8_t syscallBlob[] = { 52210590Sgabeblack@google.com // mov %rax, (0xffffc90000005600) 52310590Sgabeblack@google.com 0x48, 0xa3, 0x00, 0x60, 0x00, 52410590Sgabeblack@google.com 0x00, 0x00, 0xc9, 0xff, 0xff, 52510590Sgabeblack@google.com // sysret 52610590Sgabeblack@google.com 0x48, 0x0f, 0x07 52710554Salexandru.dutu@amd.com }; 52810554Salexandru.dutu@amd.com 52910554Salexandru.dutu@amd.com physProxy.writeBlob(syscallCodePhysAddr, 53010554Salexandru.dutu@amd.com syscallBlob, sizeof(syscallBlob)); 53110554Salexandru.dutu@amd.com 53210554Salexandru.dutu@amd.com /** Page fault handler */ 53310554Salexandru.dutu@amd.com uint8_t faultBlob[] = { 53410590Sgabeblack@google.com // mov %rax, (0xffffc90000005700) 53510590Sgabeblack@google.com 0x48, 0xa3, 0x00, 0x61, 0x00, 53610590Sgabeblack@google.com 0x00, 0x00, 0xc9, 0xff, 0xff, 53710590Sgabeblack@google.com // add $0x8, %rsp # skip error 53810590Sgabeblack@google.com 0x48, 0x83, 0xc4, 0x08, 53910590Sgabeblack@google.com // iretq 54010590Sgabeblack@google.com 0x48, 0xcf 54110554Salexandru.dutu@amd.com }; 54210554Salexandru.dutu@amd.com 54312458Sgabeblack@google.com physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob)); 54410554Salexandru.dutu@amd.com 54510554Salexandru.dutu@amd.com /* Syscall handler */ 54612460Sgabeblack@google.com pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr, 54712460Sgabeblack@google.com PageBytes, false); 54810554Salexandru.dutu@amd.com /* GDT */ 54912460Sgabeblack@google.com pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false); 55010554Salexandru.dutu@amd.com /* IDT */ 55112460Sgabeblack@google.com pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false); 55210554Salexandru.dutu@amd.com /* TSS */ 55312460Sgabeblack@google.com pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false); 55410554Salexandru.dutu@amd.com /* IST */ 55512460Sgabeblack@google.com pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false); 55610554Salexandru.dutu@amd.com /* PF handler */ 55712460Sgabeblack@google.com pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false); 55810554Salexandru.dutu@amd.com /* MMIO region for m5ops */ 55912460Sgabeblack@google.com pTable->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 56012460Sgabeblack@google.com 16 * PageBytes, false); 56110554Salexandru.dutu@amd.com } else { 56210554Salexandru.dutu@amd.com for (int i = 0; i < contextIds.size(); i++) { 56310554Salexandru.dutu@amd.com ThreadContext * tc = system->getThreadContext(contextIds[i]); 56410554Salexandru.dutu@amd.com 56510554Salexandru.dutu@amd.com SegAttr dataAttr = 0; 56610554Salexandru.dutu@amd.com dataAttr.dpl = 3; 56710554Salexandru.dutu@amd.com dataAttr.unusable = 0; 56810554Salexandru.dutu@amd.com dataAttr.defaultSize = 1; 56910554Salexandru.dutu@amd.com dataAttr.longMode = 1; 57010554Salexandru.dutu@amd.com dataAttr.avl = 0; 57110554Salexandru.dutu@amd.com dataAttr.granularity = 1; 57210554Salexandru.dutu@amd.com dataAttr.present = 1; 57310554Salexandru.dutu@amd.com dataAttr.type = 3; 57410554Salexandru.dutu@amd.com dataAttr.writable = 1; 57510554Salexandru.dutu@amd.com dataAttr.readable = 1; 57610554Salexandru.dutu@amd.com dataAttr.expandDown = 0; 57710554Salexandru.dutu@amd.com dataAttr.system = 1; 57810554Salexandru.dutu@amd.com 57911906SBrandon.Potter@amd.com // Initialize the segment registers. 58011321Ssteve.reinhardt@amd.com for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 58110554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 58210554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 58310554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 58410554Salexandru.dutu@amd.com } 58510554Salexandru.dutu@amd.com 58610554Salexandru.dutu@amd.com SegAttr csAttr = 0; 58710554Salexandru.dutu@amd.com csAttr.dpl = 3; 58810554Salexandru.dutu@amd.com csAttr.unusable = 0; 58910554Salexandru.dutu@amd.com csAttr.defaultSize = 0; 59010554Salexandru.dutu@amd.com csAttr.longMode = 1; 59110554Salexandru.dutu@amd.com csAttr.avl = 0; 59210554Salexandru.dutu@amd.com csAttr.granularity = 1; 59310554Salexandru.dutu@amd.com csAttr.present = 1; 59410554Salexandru.dutu@amd.com csAttr.type = 10; 59510554Salexandru.dutu@amd.com csAttr.writable = 0; 59610554Salexandru.dutu@amd.com csAttr.readable = 1; 59710554Salexandru.dutu@amd.com csAttr.expandDown = 0; 59810554Salexandru.dutu@amd.com csAttr.system = 1; 59910554Salexandru.dutu@amd.com 60010554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 60110554Salexandru.dutu@amd.com 60210554Salexandru.dutu@amd.com Efer efer = 0; 60310554Salexandru.dutu@amd.com efer.sce = 1; // Enable system call extensions. 60410554Salexandru.dutu@amd.com efer.lme = 1; // Enable long mode. 60510554Salexandru.dutu@amd.com efer.lma = 1; // Activate long mode. 60610554Salexandru.dutu@amd.com efer.nxe = 1; // Enable nx support. 60710554Salexandru.dutu@amd.com efer.svme = 0; // Disable svm support for now. It isn't implemented. 60810554Salexandru.dutu@amd.com efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 60910554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_EFER, efer); 61010554Salexandru.dutu@amd.com 61111906SBrandon.Potter@amd.com // Set up the registers that describe the operating mode. 61210554Salexandru.dutu@amd.com CR0 cr0 = 0; 61310554Salexandru.dutu@amd.com cr0.pg = 1; // Turn on paging. 61410554Salexandru.dutu@amd.com cr0.cd = 0; // Don't disable caching. 61510554Salexandru.dutu@amd.com cr0.nw = 0; // This is bit is defined to be ignored. 61610554Salexandru.dutu@amd.com cr0.am = 0; // No alignment checking 61710554Salexandru.dutu@amd.com cr0.wp = 0; // Supervisor mode can write read only pages 61810554Salexandru.dutu@amd.com cr0.ne = 1; 61910554Salexandru.dutu@amd.com cr0.et = 1; // This should always be 1 62010554Salexandru.dutu@amd.com cr0.ts = 0; // We don't do task switching, so causing fp exceptions 62110554Salexandru.dutu@amd.com // would be pointless. 62210554Salexandru.dutu@amd.com cr0.em = 0; // Allow x87 instructions to execute natively. 62310554Salexandru.dutu@amd.com cr0.mp = 1; // This doesn't really matter, but the manual suggests 62410554Salexandru.dutu@amd.com // setting it to one. 62510554Salexandru.dutu@amd.com cr0.pe = 1; // We're definitely in protected mode. 62610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR0, cr0); 62710554Salexandru.dutu@amd.com 62810554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 62910554Salexandru.dutu@amd.com } 6305140Sgblack@eecs.umich.edu } 6314166Sgblack@eecs.umich.edu} 6324166Sgblack@eecs.umich.edu 6334166Sgblack@eecs.umich.eduvoid 63411851Sbrandon.potter@amd.comI386Process::initState() 6354166Sgblack@eecs.umich.edu{ 63611851Sbrandon.potter@amd.com X86Process::initState(); 6375956Sgblack@eecs.umich.edu 63811884Sbrandon.potter@amd.com argsInit(PageBytes); 6395956Sgblack@eecs.umich.edu 64011320Ssteve.reinhardt@amd.com /* 6415962Sgblack@eecs.umich.edu * Set up a GDT for this process. The whole GDT wouldn't really be for 6425962Sgblack@eecs.umich.edu * this process, but the only parts we care about are. 6435962Sgblack@eecs.umich.edu */ 6448601Ssteve.reinhardt@amd.com allocateMem(_gdtStart, _gdtSize); 6455962Sgblack@eecs.umich.edu uint64_t zero = 0; 6465962Sgblack@eecs.umich.edu assert(_gdtSize % sizeof(zero) == 0); 6475962Sgblack@eecs.umich.edu for (Addr gdtCurrent = _gdtStart; 6485962Sgblack@eecs.umich.edu gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) { 6498852Sandreas.hansson@arm.com initVirtMem.write(gdtCurrent, zero); 6505962Sgblack@eecs.umich.edu } 6515962Sgblack@eecs.umich.edu 6525973Sgblack@eecs.umich.edu // Set up the vsyscall page for this process. 6538601Ssteve.reinhardt@amd.com allocateMem(vsyscallPage.base, vsyscallPage.size); 6545973Sgblack@eecs.umich.edu uint8_t vsyscallBlob[] = { 6555973Sgblack@eecs.umich.edu 0x51, // push %ecx 6565973Sgblack@eecs.umich.edu 0x52, // push %edp 6575973Sgblack@eecs.umich.edu 0x55, // push %ebp 6585973Sgblack@eecs.umich.edu 0x89, 0xe5, // mov %esp, %ebp 6595973Sgblack@eecs.umich.edu 0x0f, 0x34 // sysenter 6605973Sgblack@eecs.umich.edu }; 6618852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset, 6625973Sgblack@eecs.umich.edu vsyscallBlob, sizeof(vsyscallBlob)); 6635973Sgblack@eecs.umich.edu 6645973Sgblack@eecs.umich.edu uint8_t vsysexitBlob[] = { 6655973Sgblack@eecs.umich.edu 0x5d, // pop %ebp 6665973Sgblack@eecs.umich.edu 0x5a, // pop %edx 6675973Sgblack@eecs.umich.edu 0x59, // pop %ecx 6685973Sgblack@eecs.umich.edu 0xc3 // ret 6695973Sgblack@eecs.umich.edu }; 6708852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset, 6715973Sgblack@eecs.umich.edu vsysexitBlob, sizeof(vsysexitBlob)); 6725973Sgblack@eecs.umich.edu 6735956Sgblack@eecs.umich.edu for (int i = 0; i < contextIds.size(); i++) { 6745956Sgblack@eecs.umich.edu ThreadContext * tc = system->getThreadContext(contextIds[i]); 6755956Sgblack@eecs.umich.edu 6765956Sgblack@eecs.umich.edu SegAttr dataAttr = 0; 6776222Sgblack@eecs.umich.edu dataAttr.dpl = 3; 6786222Sgblack@eecs.umich.edu dataAttr.unusable = 0; 6796222Sgblack@eecs.umich.edu dataAttr.defaultSize = 1; 6806222Sgblack@eecs.umich.edu dataAttr.longMode = 0; 6816222Sgblack@eecs.umich.edu dataAttr.avl = 0; 6826222Sgblack@eecs.umich.edu dataAttr.granularity = 1; 6836222Sgblack@eecs.umich.edu dataAttr.present = 1; 6846222Sgblack@eecs.umich.edu dataAttr.type = 3; 6855956Sgblack@eecs.umich.edu dataAttr.writable = 1; 6865956Sgblack@eecs.umich.edu dataAttr.readable = 1; 6875956Sgblack@eecs.umich.edu dataAttr.expandDown = 0; 6886222Sgblack@eecs.umich.edu dataAttr.system = 1; 6895956Sgblack@eecs.umich.edu 69011906SBrandon.Potter@amd.com // Initialize the segment registers. 69111321Ssteve.reinhardt@amd.com for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 6925956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 6935956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 6945956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 6955956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB); 6965959Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1)); 6975956Sgblack@eecs.umich.edu } 6985956Sgblack@eecs.umich.edu 6995956Sgblack@eecs.umich.edu SegAttr csAttr = 0; 7006222Sgblack@eecs.umich.edu csAttr.dpl = 3; 7016222Sgblack@eecs.umich.edu csAttr.unusable = 0; 7026222Sgblack@eecs.umich.edu csAttr.defaultSize = 1; 7036222Sgblack@eecs.umich.edu csAttr.longMode = 0; 7046222Sgblack@eecs.umich.edu csAttr.avl = 0; 7056222Sgblack@eecs.umich.edu csAttr.granularity = 1; 7066222Sgblack@eecs.umich.edu csAttr.present = 1; 7076222Sgblack@eecs.umich.edu csAttr.type = 0xa; 7085956Sgblack@eecs.umich.edu csAttr.writable = 0; 7095956Sgblack@eecs.umich.edu csAttr.readable = 1; 7105956Sgblack@eecs.umich.edu csAttr.expandDown = 0; 7116222Sgblack@eecs.umich.edu csAttr.system = 1; 7125956Sgblack@eecs.umich.edu 7135956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 7145956Sgblack@eecs.umich.edu 7155962Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart); 7165962Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart); 7175962Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1); 7185962Sgblack@eecs.umich.edu 7195963Sgblack@eecs.umich.edu // Set the LDT selector to 0 to deactivate it. 7205963Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSL, 0); 7215963Sgblack@eecs.umich.edu 7226140Sgblack@eecs.umich.edu Efer efer = 0; 7236140Sgblack@eecs.umich.edu efer.sce = 1; // Enable system call extensions. 7246140Sgblack@eecs.umich.edu efer.lme = 1; // Enable long mode. 7256140Sgblack@eecs.umich.edu efer.lma = 0; // Deactivate long mode. 7266140Sgblack@eecs.umich.edu efer.nxe = 1; // Enable nx support. 7276140Sgblack@eecs.umich.edu efer.svme = 0; // Disable svm support for now. It isn't implemented. 7286140Sgblack@eecs.umich.edu efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 7296140Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_EFER, efer); 7306140Sgblack@eecs.umich.edu 73111906SBrandon.Potter@amd.com // Set up the registers that describe the operating mode. 7325956Sgblack@eecs.umich.edu CR0 cr0 = 0; 7335956Sgblack@eecs.umich.edu cr0.pg = 1; // Turn on paging. 7345956Sgblack@eecs.umich.edu cr0.cd = 0; // Don't disable caching. 7355956Sgblack@eecs.umich.edu cr0.nw = 0; // This is bit is defined to be ignored. 7365956Sgblack@eecs.umich.edu cr0.am = 0; // No alignment checking 7375956Sgblack@eecs.umich.edu cr0.wp = 0; // Supervisor mode can write read only pages 7385956Sgblack@eecs.umich.edu cr0.ne = 1; 7395956Sgblack@eecs.umich.edu cr0.et = 1; // This should always be 1 7405956Sgblack@eecs.umich.edu cr0.ts = 0; // We don't do task switching, so causing fp exceptions 7415956Sgblack@eecs.umich.edu // would be pointless. 7425956Sgblack@eecs.umich.edu cr0.em = 0; // Allow x87 instructions to execute natively. 7435956Sgblack@eecs.umich.edu cr0.mp = 1; // This doesn't really matter, but the manual suggests 7445956Sgblack@eecs.umich.edu // setting it to one. 7455956Sgblack@eecs.umich.edu cr0.pe = 1; // We're definitely in protected mode. 7465956Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, cr0); 7476609Sgblack@eecs.umich.edu 7486609Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 7495956Sgblack@eecs.umich.edu } 7505956Sgblack@eecs.umich.edu} 7515956Sgblack@eecs.umich.edu 7525956Sgblack@eecs.umich.edutemplate<class IntType> 7535956Sgblack@eecs.umich.eduvoid 75411851Sbrandon.potter@amd.comX86Process::argsInit(int pageSize, 75511884Sbrandon.potter@amd.com std::vector<AuxVector<IntType> > extraAuxvs) 7565956Sgblack@eecs.umich.edu{ 7575956Sgblack@eecs.umich.edu int intSize = sizeof(IntType); 7585956Sgblack@eecs.umich.edu 7595956Sgblack@eecs.umich.edu typedef AuxVector<IntType> auxv_t; 7605973Sgblack@eecs.umich.edu std::vector<auxv_t> auxv = extraAuxvs; 7615758Shsul@eecs.umich.edu 7624166Sgblack@eecs.umich.edu string filename; 76311321Ssteve.reinhardt@amd.com if (argv.size() < 1) 7644166Sgblack@eecs.umich.edu filename = ""; 7654166Sgblack@eecs.umich.edu else 7664166Sgblack@eecs.umich.edu filename = argv[0]; 7674166Sgblack@eecs.umich.edu 76811906SBrandon.Potter@amd.com // We want 16 byte alignment 7694849Sgblack@eecs.umich.edu uint64_t align = 16; 7704166Sgblack@eecs.umich.edu 77111389Sbrandon.potter@amd.com // Patch the ld_bias for dynamic executables. 77211389Sbrandon.potter@amd.com updateBias(); 77311389Sbrandon.potter@amd.com 7744166Sgblack@eecs.umich.edu // load object file into target memory 7754166Sgblack@eecs.umich.edu objFile->loadSections(initVirtMem); 7764166Sgblack@eecs.umich.edu 7774793Sgblack@eecs.umich.edu enum X86CpuFeature { 7784793Sgblack@eecs.umich.edu X86_OnboardFPU = 1 << 0, 7794793Sgblack@eecs.umich.edu X86_VirtualModeExtensions = 1 << 1, 7804793Sgblack@eecs.umich.edu X86_DebuggingExtensions = 1 << 2, 7814793Sgblack@eecs.umich.edu X86_PageSizeExtensions = 1 << 3, 7824777Sgblack@eecs.umich.edu 7834793Sgblack@eecs.umich.edu X86_TimeStampCounter = 1 << 4, 7844793Sgblack@eecs.umich.edu X86_ModelSpecificRegisters = 1 << 5, 7854793Sgblack@eecs.umich.edu X86_PhysicalAddressExtensions = 1 << 6, 7864793Sgblack@eecs.umich.edu X86_MachineCheckExtensions = 1 << 7, 7874777Sgblack@eecs.umich.edu 7884793Sgblack@eecs.umich.edu X86_CMPXCHG8Instruction = 1 << 8, 7894793Sgblack@eecs.umich.edu X86_OnboardAPIC = 1 << 9, 7904793Sgblack@eecs.umich.edu X86_SYSENTER_SYSEXIT = 1 << 11, 7914793Sgblack@eecs.umich.edu 7924793Sgblack@eecs.umich.edu X86_MemoryTypeRangeRegisters = 1 << 12, 7934793Sgblack@eecs.umich.edu X86_PageGlobalEnable = 1 << 13, 7944793Sgblack@eecs.umich.edu X86_MachineCheckArchitecture = 1 << 14, 7954793Sgblack@eecs.umich.edu X86_CMOVInstruction = 1 << 15, 7964793Sgblack@eecs.umich.edu 7974793Sgblack@eecs.umich.edu X86_PageAttributeTable = 1 << 16, 7984793Sgblack@eecs.umich.edu X86_36BitPSEs = 1 << 17, 7994793Sgblack@eecs.umich.edu X86_ProcessorSerialNumber = 1 << 18, 8004793Sgblack@eecs.umich.edu X86_CLFLUSHInstruction = 1 << 19, 8014793Sgblack@eecs.umich.edu 8024793Sgblack@eecs.umich.edu X86_DebugTraceStore = 1 << 21, 8034793Sgblack@eecs.umich.edu X86_ACPIViaMSR = 1 << 22, 8044793Sgblack@eecs.umich.edu X86_MultimediaExtensions = 1 << 23, 8054793Sgblack@eecs.umich.edu 8064793Sgblack@eecs.umich.edu X86_FXSAVE_FXRSTOR = 1 << 24, 8074793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions = 1 << 25, 8084793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions2 = 1 << 26, 8094793Sgblack@eecs.umich.edu X86_CPUSelfSnoop = 1 << 27, 8104793Sgblack@eecs.umich.edu 8114793Sgblack@eecs.umich.edu X86_HyperThreading = 1 << 28, 8124793Sgblack@eecs.umich.edu X86_AutomaticClockControl = 1 << 29, 8134793Sgblack@eecs.umich.edu X86_IA64Processor = 1 << 30 8144166Sgblack@eecs.umich.edu }; 8154166Sgblack@eecs.umich.edu 81611389Sbrandon.potter@amd.com // Setup the auxiliary vectors. These will already have endian 81711389Sbrandon.potter@amd.com // conversion. Auxiliary vectors are loaded only for elf formatted 81811389Sbrandon.potter@amd.com // executables; the auxv is responsible for passing information from 81911389Sbrandon.potter@amd.com // the OS to the interpreter. 8204166Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 82110590Sgabeblack@google.com if (elfObject) { 8224793Sgblack@eecs.umich.edu uint64_t features = 8234793Sgblack@eecs.umich.edu X86_OnboardFPU | 8244793Sgblack@eecs.umich.edu X86_VirtualModeExtensions | 8254793Sgblack@eecs.umich.edu X86_DebuggingExtensions | 8264793Sgblack@eecs.umich.edu X86_PageSizeExtensions | 8274793Sgblack@eecs.umich.edu X86_TimeStampCounter | 8284793Sgblack@eecs.umich.edu X86_ModelSpecificRegisters | 8294793Sgblack@eecs.umich.edu X86_PhysicalAddressExtensions | 8304793Sgblack@eecs.umich.edu X86_MachineCheckExtensions | 8314793Sgblack@eecs.umich.edu X86_CMPXCHG8Instruction | 8324793Sgblack@eecs.umich.edu X86_OnboardAPIC | 8334793Sgblack@eecs.umich.edu X86_SYSENTER_SYSEXIT | 8344793Sgblack@eecs.umich.edu X86_MemoryTypeRangeRegisters | 8354793Sgblack@eecs.umich.edu X86_PageGlobalEnable | 8364793Sgblack@eecs.umich.edu X86_MachineCheckArchitecture | 8374793Sgblack@eecs.umich.edu X86_CMOVInstruction | 8384793Sgblack@eecs.umich.edu X86_PageAttributeTable | 8394793Sgblack@eecs.umich.edu X86_36BitPSEs | 8404793Sgblack@eecs.umich.edu// X86_ProcessorSerialNumber | 8414793Sgblack@eecs.umich.edu X86_CLFLUSHInstruction | 8424793Sgblack@eecs.umich.edu// X86_DebugTraceStore | 8434793Sgblack@eecs.umich.edu// X86_ACPIViaMSR | 8444793Sgblack@eecs.umich.edu X86_MultimediaExtensions | 8454793Sgblack@eecs.umich.edu X86_FXSAVE_FXRSTOR | 8464793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions | 8474793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions2 | 8484793Sgblack@eecs.umich.edu// X86_CPUSelfSnoop | 8494793Sgblack@eecs.umich.edu// X86_HyperThreading | 8504793Sgblack@eecs.umich.edu// X86_AutomaticClockControl | 8514793Sgblack@eecs.umich.edu// X86_IA64Processor | 8524793Sgblack@eecs.umich.edu 0; 8534793Sgblack@eecs.umich.edu 85411906SBrandon.Potter@amd.com // Bits which describe the system hardware capabilities 85511906SBrandon.Potter@amd.com // XXX Figure out what these should be 8564793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 85711906SBrandon.Potter@amd.com // The system page size 85810318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes)); 85911906SBrandon.Potter@amd.com // Frequency at which times() increments 86011906SBrandon.Potter@amd.com // Defined to be 100 in the kernel source. 8614793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 86211389Sbrandon.potter@amd.com // This is the virtual address of the program header tables if they 86311389Sbrandon.potter@amd.com // appear in the executable image. 8644793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 8654166Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 8664793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 8674166Sgblack@eecs.umich.edu // This is the number of program headers from the original elf file. 8684793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 86911389Sbrandon.potter@amd.com // This is the base address of the ELF interpreter; it should be 87011389Sbrandon.potter@amd.com // zero for static executables or contain the base address for 87111389Sbrandon.potter@amd.com // dynamic executables. 87211389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 87311906SBrandon.Potter@amd.com // XXX Figure out what this should be. 8744793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 87511906SBrandon.Potter@amd.com // The entry point to the program 8764793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 87711906SBrandon.Potter@amd.com // Different user and group IDs 8784793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 8794793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 8804793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 8814793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 88211906SBrandon.Potter@amd.com // Whether to enable "secure mode" in the executable 8834793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 88411906SBrandon.Potter@amd.com // The address of 16 "random" bytes. 8857073Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 88611906SBrandon.Potter@amd.com // The name of the program 8877073Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 88811906SBrandon.Potter@amd.com // The platform string 8894793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 8904166Sgblack@eecs.umich.edu } 8914166Sgblack@eecs.umich.edu 89211906SBrandon.Potter@amd.com // Figure out how big the initial stack needs to be 8934166Sgblack@eecs.umich.edu 8944849Sgblack@eecs.umich.edu // A sentry NULL void pointer at the top of the stack. 8954849Sgblack@eecs.umich.edu int sentry_size = intSize; 8964166Sgblack@eecs.umich.edu 89711906SBrandon.Potter@amd.com // This is the name of the file which is present on the initial stack 89811906SBrandon.Potter@amd.com // It's purpose is to let the user space linker examine the original file. 8994847Sgblack@eecs.umich.edu int file_name_size = filename.size() + 1; 9004793Sgblack@eecs.umich.edu 9017073Sgblack@eecs.umich.edu const int numRandomBytes = 16; 9027073Sgblack@eecs.umich.edu int aux_data_size = numRandomBytes; 9037073Sgblack@eecs.umich.edu 9044793Sgblack@eecs.umich.edu string platform = "x86_64"; 9057073Sgblack@eecs.umich.edu aux_data_size += platform.size() + 1; 9064166Sgblack@eecs.umich.edu 9074166Sgblack@eecs.umich.edu int env_data_size = 0; 90810590Sgabeblack@google.com for (int i = 0; i < envp.size(); ++i) 9094847Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 9104166Sgblack@eecs.umich.edu int arg_data_size = 0; 91110590Sgabeblack@google.com for (int i = 0; i < argv.size(); ++i) 9124847Sgblack@eecs.umich.edu arg_data_size += argv[i].size() + 1; 9134166Sgblack@eecs.umich.edu 91411906SBrandon.Potter@amd.com // The info_block needs to be padded so its size is a multiple of the 91511906SBrandon.Potter@amd.com // alignment mask. Also, it appears that there needs to be at least some 91611906SBrandon.Potter@amd.com // padding, so if the size is already a multiple, we need to increase it 91711906SBrandon.Potter@amd.com // anyway. 9184849Sgblack@eecs.umich.edu int base_info_block_size = 9194849Sgblack@eecs.umich.edu sentry_size + file_name_size + env_data_size + arg_data_size; 9204166Sgblack@eecs.umich.edu 9214849Sgblack@eecs.umich.edu int info_block_size = roundUp(base_info_block_size, align); 9224849Sgblack@eecs.umich.edu 9234849Sgblack@eecs.umich.edu int info_block_padding = info_block_size - base_info_block_size; 9244166Sgblack@eecs.umich.edu 92511906SBrandon.Potter@amd.com // Each auxiliary vector is two 8 byte words 9264166Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 9274166Sgblack@eecs.umich.edu 9284166Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 9294166Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 9304166Sgblack@eecs.umich.edu 9314166Sgblack@eecs.umich.edu int argc_size = intSize; 9324166Sgblack@eecs.umich.edu 93311906SBrandon.Potter@amd.com // Figure out the size of the contents of the actual initial frame 9344849Sgblack@eecs.umich.edu int frame_size = 9354166Sgblack@eecs.umich.edu aux_array_size + 9364166Sgblack@eecs.umich.edu envp_array_size + 9374166Sgblack@eecs.umich.edu argv_array_size + 9384607Sgblack@eecs.umich.edu argc_size; 9394166Sgblack@eecs.umich.edu 94011906SBrandon.Potter@amd.com // There needs to be padding after the auxiliary vector data so that the 94111906SBrandon.Potter@amd.com // very bottom of the stack is aligned properly. 9424849Sgblack@eecs.umich.edu int partial_size = frame_size + aux_data_size; 9434849Sgblack@eecs.umich.edu int aligned_partial_size = roundUp(partial_size, align); 9444849Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - partial_size; 9454849Sgblack@eecs.umich.edu 9464849Sgblack@eecs.umich.edu int space_needed = 9474849Sgblack@eecs.umich.edu info_block_size + 9484849Sgblack@eecs.umich.edu aux_data_size + 9494849Sgblack@eecs.umich.edu aux_padding + 9504849Sgblack@eecs.umich.edu frame_size; 9514849Sgblack@eecs.umich.edu 95211905SBrandon.Potter@amd.com Addr stack_base = memState->getStackBase(); 95311905SBrandon.Potter@amd.com 95411905SBrandon.Potter@amd.com Addr stack_min = stack_base - space_needed; 95511905SBrandon.Potter@amd.com stack_min = roundDown(stack_min, align); 95611905SBrandon.Potter@amd.com 95711905SBrandon.Potter@amd.com unsigned stack_size = stack_base - stack_min; 95811905SBrandon.Potter@amd.com stack_size = roundUp(stack_size, pageSize); 95911905SBrandon.Potter@amd.com memState->setStackSize(stack_size); 9604166Sgblack@eecs.umich.edu 9614166Sgblack@eecs.umich.edu // map memory 96211905SBrandon.Potter@amd.com Addr stack_end = roundDown(stack_base - stack_size, pageSize); 96310554Salexandru.dutu@amd.com 96411905SBrandon.Potter@amd.com DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size); 96511905SBrandon.Potter@amd.com allocateMem(stack_end, stack_size); 9664166Sgblack@eecs.umich.edu 9674166Sgblack@eecs.umich.edu // map out initial stack contents 96811905SBrandon.Potter@amd.com IntType sentry_base = stack_base - sentry_size; 9695956Sgblack@eecs.umich.edu IntType file_name_base = sentry_base - file_name_size; 9705956Sgblack@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 9715956Sgblack@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 9725956Sgblack@eecs.umich.edu IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size; 9735956Sgblack@eecs.umich.edu IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding; 9745956Sgblack@eecs.umich.edu IntType envp_array_base = auxv_array_base - envp_array_size; 9755956Sgblack@eecs.umich.edu IntType argv_array_base = envp_array_base - argv_array_size; 9765956Sgblack@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 9774166Sgblack@eecs.umich.edu 9785941Sgblack@eecs.umich.edu DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 9795941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - file name\n", file_name_base); 9805941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - env data\n", env_data_base); 9815941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 9825941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 9835941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 9845941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 9855941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 9865941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - argc \n", argc_base); 98711905SBrandon.Potter@amd.com DPRINTF(Stack, "0x%x - stack min\n", stack_min); 9884166Sgblack@eecs.umich.edu 9894166Sgblack@eecs.umich.edu // write contents to stack 9904166Sgblack@eecs.umich.edu 9914166Sgblack@eecs.umich.edu // figure out argc 9925956Sgblack@eecs.umich.edu IntType argc = argv.size(); 9935956Sgblack@eecs.umich.edu IntType guestArgc = X86ISA::htog(argc); 9944166Sgblack@eecs.umich.edu 99511906SBrandon.Potter@amd.com // Write out the sentry void * 9965956Sgblack@eecs.umich.edu IntType sentry_NULL = 0; 99711906SBrandon.Potter@amd.com initVirtMem.writeBlob(sentry_base, (uint8_t*)&sentry_NULL, sentry_size); 9984166Sgblack@eecs.umich.edu 99911906SBrandon.Potter@amd.com // Write the file name 10008852Sandreas.hansson@arm.com initVirtMem.writeString(file_name_base, filename.c_str()); 10014166Sgblack@eecs.umich.edu 100211906SBrandon.Potter@amd.com // Fix up the aux vectors which point to data 100313028Sbrandon.potter@amd.com assert(auxv[auxv.size() - 3].getHostAuxType() == M5_AT_RANDOM); 100413028Sbrandon.potter@amd.com auxv[auxv.size() - 3].setAuxVal(aux_data_base); 100513028Sbrandon.potter@amd.com assert(auxv[auxv.size() - 2].getHostAuxType() == M5_AT_EXECFN); 100613028Sbrandon.potter@amd.com auxv[auxv.size() - 2].setAuxVal(argv_array_base); 100713028Sbrandon.potter@amd.com assert(auxv[auxv.size() - 1].getHostAuxType() == M5_AT_PLATFORM); 100813028Sbrandon.potter@amd.com auxv[auxv.size() - 1].setAuxVal(aux_data_base + numRandomBytes); 10094793Sgblack@eecs.umich.edu 101011906SBrandon.Potter@amd.com 101111906SBrandon.Potter@amd.com // Copy the aux stuff 101210590Sgabeblack@google.com for (int x = 0; x < auxv.size(); x++) { 10138852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 101413028Sbrandon.potter@amd.com (uint8_t*)&(auxv[x].getAuxType()), 101513028Sbrandon.potter@amd.com intSize); 10168852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 101713028Sbrandon.potter@amd.com (uint8_t*)&(auxv[x].getAuxVal()), 101813028Sbrandon.potter@amd.com intSize); 10194166Sgblack@eecs.umich.edu } 102011906SBrandon.Potter@amd.com // Write out the terminating zeroed auxiliary vector 10214166Sgblack@eecs.umich.edu const uint64_t zero = 0; 102211326Ssteve.reinhardt@amd.com initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize, 102311326Ssteve.reinhardt@amd.com (uint8_t*)&zero, intSize); 102411326Ssteve.reinhardt@amd.com initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize, 102511326Ssteve.reinhardt@amd.com (uint8_t*)&zero, intSize); 10264166Sgblack@eecs.umich.edu 10278852Sandreas.hansson@arm.com initVirtMem.writeString(aux_data_base, platform.c_str()); 10284793Sgblack@eecs.umich.edu 10294166Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 10304166Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 10314166Sgblack@eecs.umich.edu 10328852Sandreas.hansson@arm.com initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 10334166Sgblack@eecs.umich.edu 10345713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 103511906SBrandon.Potter@amd.com // Set the stack pointer register 103611905SBrandon.Potter@amd.com tc->setIntReg(StackPointerReg, stack_min); 10374166Sgblack@eecs.umich.edu 10385246Sgblack@eecs.umich.edu // There doesn't need to be any segment base added in since we're dealing 10395246Sgblack@eecs.umich.edu // with the flat segmentation model. 104011389Sbrandon.potter@amd.com tc->pcState(getStartPC()); 10414166Sgblack@eecs.umich.edu 104211906SBrandon.Potter@amd.com // Align the "stack_min" to a page boundary. 104311905SBrandon.Potter@amd.com memState->setStackMin(roundDown(stack_min, pageSize)); 10444166Sgblack@eecs.umich.edu} 10455956Sgblack@eecs.umich.edu 10465956Sgblack@eecs.umich.eduvoid 104711884Sbrandon.potter@amd.comX86_64Process::argsInit(int pageSize) 10485956Sgblack@eecs.umich.edu{ 10495973Sgblack@eecs.umich.edu std::vector<AuxVector<uint64_t> > extraAuxvs; 10507073Sgblack@eecs.umich.edu extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR, 10517073Sgblack@eecs.umich.edu vsyscallPage.base)); 105211851Sbrandon.potter@amd.com X86Process::argsInit<uint64_t>(pageSize, extraAuxvs); 10535956Sgblack@eecs.umich.edu} 10545956Sgblack@eecs.umich.edu 10555956Sgblack@eecs.umich.eduvoid 105611884Sbrandon.potter@amd.comI386Process::argsInit(int pageSize) 10575956Sgblack@eecs.umich.edu{ 10585973Sgblack@eecs.umich.edu std::vector<AuxVector<uint32_t> > extraAuxvs; 10595973Sgblack@eecs.umich.edu //Tell the binary where the vsyscall part of the vsyscall page is. 10607073Sgblack@eecs.umich.edu extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO, 10615973Sgblack@eecs.umich.edu vsyscallPage.base + vsyscallPage.vsyscallOffset)); 10627073Sgblack@eecs.umich.edu extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR, 10637073Sgblack@eecs.umich.edu vsyscallPage.base)); 106411851Sbrandon.potter@amd.com X86Process::argsInit<uint32_t>(pageSize, extraAuxvs); 10655956Sgblack@eecs.umich.edu} 10665958Sgblack@eecs.umich.edu 10675958Sgblack@eecs.umich.eduvoid 106811851Sbrandon.potter@amd.comX86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval) 10695958Sgblack@eecs.umich.edu{ 107010223Ssteve.reinhardt@amd.com tc->setIntReg(INTREG_RAX, retval.encodedValue()); 10715958Sgblack@eecs.umich.edu} 10725958Sgblack@eecs.umich.edu 107313613Sgabeblack@google.comRegVal 107411851Sbrandon.potter@amd.comX86_64Process::getSyscallArg(ThreadContext *tc, int &i) 10755958Sgblack@eecs.umich.edu{ 10765958Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10776701Sgblack@eecs.umich.edu return tc->readIntReg(ArgumentReg[i++]); 10785958Sgblack@eecs.umich.edu} 10795958Sgblack@eecs.umich.edu 10805958Sgblack@eecs.umich.eduvoid 108113613Sgabeblack@google.comX86_64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val) 10825958Sgblack@eecs.umich.edu{ 10835958Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10845958Sgblack@eecs.umich.edu return tc->setIntReg(ArgumentReg[i], val); 10855958Sgblack@eecs.umich.edu} 10865958Sgblack@eecs.umich.edu 108711886Sbrandon.potter@amd.comvoid 108811886Sbrandon.potter@amd.comX86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, 108913613Sgabeblack@google.com Process *p, RegVal flags) 109011886Sbrandon.potter@amd.com{ 109111886Sbrandon.potter@amd.com X86Process::clone(old_tc, new_tc, p, flags); 109211886Sbrandon.potter@amd.com ((X86_64Process*)p)->vsyscallPage = vsyscallPage; 109311886Sbrandon.potter@amd.com} 109411886Sbrandon.potter@amd.com 109513613Sgabeblack@google.comRegVal 109611851Sbrandon.potter@amd.comI386Process::getSyscallArg(ThreadContext *tc, int &i) 10975958Sgblack@eecs.umich.edu{ 10985959Sgblack@eecs.umich.edu assert(i < NumArgumentRegs32); 10996701Sgblack@eecs.umich.edu return tc->readIntReg(ArgumentReg32[i++]); 11006701Sgblack@eecs.umich.edu} 11016701Sgblack@eecs.umich.edu 110213613Sgabeblack@google.comRegVal 110311851Sbrandon.potter@amd.comI386Process::getSyscallArg(ThreadContext *tc, int &i, int width) 11046701Sgblack@eecs.umich.edu{ 11056701Sgblack@eecs.umich.edu assert(width == 32 || width == 64); 11066701Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 11076701Sgblack@eecs.umich.edu uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32); 11086701Sgblack@eecs.umich.edu if (width == 64) 11096701Sgblack@eecs.umich.edu retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32); 11106701Sgblack@eecs.umich.edu return retVal; 11115958Sgblack@eecs.umich.edu} 11125958Sgblack@eecs.umich.edu 11135958Sgblack@eecs.umich.eduvoid 111413613Sgabeblack@google.comI386Process::setSyscallArg(ThreadContext *tc, int i, RegVal val) 11155958Sgblack@eecs.umich.edu{ 11165959Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 11175959Sgblack@eecs.umich.edu return tc->setIntReg(ArgumentReg[i], val); 11185958Sgblack@eecs.umich.edu} 111911886Sbrandon.potter@amd.com 112011886Sbrandon.potter@amd.comvoid 112111886Sbrandon.potter@amd.comI386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, 112213613Sgabeblack@google.com Process *p, RegVal flags) 112311886Sbrandon.potter@amd.com{ 112411886Sbrandon.potter@amd.com X86Process::clone(old_tc, new_tc, p, flags); 112511886Sbrandon.potter@amd.com ((I386Process*)p)->vsyscallPage = vsyscallPage; 112611886Sbrandon.potter@amd.com} 1127