process.cc revision 10554
14166Sgblack@eecs.umich.edu/* 210554Salexandru.dutu@amd.com * Copyright (c) 2014 Advanced Micro Devices, Inc. 37087Snate@binkert.org * Copyright (c) 2007 The Hewlett-Packard Development Company 47087Snate@binkert.org * All rights reserved. 57087Snate@binkert.org * 67087Snate@binkert.org * The license below extends only to copyright in the software and shall 77087Snate@binkert.org * not be construed as granting a license to any other intellectual 87087Snate@binkert.org * property including but not limited to intellectual property relating 97087Snate@binkert.org * to a hardware implementation of the functionality of the software 107087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 117087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 127087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 137087Snate@binkert.org * modified or unmodified, in source code or in binary form. 147087Snate@binkert.org * 154166Sgblack@eecs.umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 164166Sgblack@eecs.umich.edu * All rights reserved. 174166Sgblack@eecs.umich.edu * 184166Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 194166Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 204166Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 214166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 224166Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 234166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 244166Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 254166Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 264166Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 274166Sgblack@eecs.umich.edu * this software without specific prior written permission. 284166Sgblack@eecs.umich.edu * 294166Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304166Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314166Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324166Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334166Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344166Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354166Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364166Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374166Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384166Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394166Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404166Sgblack@eecs.umich.edu * 414166Sgblack@eecs.umich.edu * Authors: Gabe Black 424166Sgblack@eecs.umich.edu * Ali Saidi 434166Sgblack@eecs.umich.edu */ 444166Sgblack@eecs.umich.edu 458229Snate@binkert.org#include "arch/x86/regs/misc.hh" 468229Snate@binkert.org#include "arch/x86/regs/segment.hh" 474166Sgblack@eecs.umich.edu#include "arch/x86/isa_traits.hh" 484166Sgblack@eecs.umich.edu#include "arch/x86/process.hh" 4910554Salexandru.dutu@amd.com#include "arch/x86/system.hh" 504166Sgblack@eecs.umich.edu#include "arch/x86/types.hh" 518229Snate@binkert.org#include "base/loader/elf_object.hh" 524166Sgblack@eecs.umich.edu#include "base/loader/object_file.hh" 534166Sgblack@eecs.umich.edu#include "base/misc.hh" 545004Sgblack@eecs.umich.edu#include "base/trace.hh" 554166Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 568232Snate@binkert.org#include "debug/Stack.hh" 5710554Salexandru.dutu@amd.com#include "mem/multi_level_page_table.hh" 584166Sgblack@eecs.umich.edu#include "mem/page_table.hh" 594434Ssaidi@eecs.umich.edu#include "sim/process_impl.hh" 605956Sgblack@eecs.umich.edu#include "sim/syscall_emul.hh" 614166Sgblack@eecs.umich.edu#include "sim/system.hh" 624166Sgblack@eecs.umich.edu 634166Sgblack@eecs.umich.eduusing namespace std; 644166Sgblack@eecs.umich.eduusing namespace X86ISA; 654166Sgblack@eecs.umich.edu 665958Sgblack@eecs.umich.edustatic const int ArgumentReg[] = { 675958Sgblack@eecs.umich.edu INTREG_RDI, 685958Sgblack@eecs.umich.edu INTREG_RSI, 695958Sgblack@eecs.umich.edu INTREG_RDX, 705958Sgblack@eecs.umich.edu //This argument register is r10 for syscalls and rcx for C. 715958Sgblack@eecs.umich.edu INTREG_R10W, 725958Sgblack@eecs.umich.edu //INTREG_RCX, 735958Sgblack@eecs.umich.edu INTREG_R8W, 745958Sgblack@eecs.umich.edu INTREG_R9W 755958Sgblack@eecs.umich.edu}; 765958Sgblack@eecs.umich.edustatic const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 775959Sgblack@eecs.umich.edustatic const int ArgumentReg32[] = { 785959Sgblack@eecs.umich.edu INTREG_EBX, 795959Sgblack@eecs.umich.edu INTREG_ECX, 805959Sgblack@eecs.umich.edu INTREG_EDX, 815959Sgblack@eecs.umich.edu INTREG_ESI, 825959Sgblack@eecs.umich.edu INTREG_EDI, 835959Sgblack@eecs.umich.edu}; 845959Sgblack@eecs.umich.edustatic const int NumArgumentRegs32 = sizeof(ArgumentReg) / sizeof(const int); 854166Sgblack@eecs.umich.edu 865956Sgblack@eecs.umich.eduX86LiveProcess::X86LiveProcess(LiveProcessParams * params, ObjectFile *objFile, 875956Sgblack@eecs.umich.edu SyscallDesc *_syscallDescs, int _numSyscallDescs) : 885956Sgblack@eecs.umich.edu LiveProcess(params, objFile), syscallDescs(_syscallDescs), 895956Sgblack@eecs.umich.edu numSyscallDescs(_numSyscallDescs) 904166Sgblack@eecs.umich.edu{ 914166Sgblack@eecs.umich.edu brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 9210318Sandreas.hansson@arm.com brk_point = roundUp(brk_point, PageBytes); 935956Sgblack@eecs.umich.edu} 944166Sgblack@eecs.umich.edu 955956Sgblack@eecs.umich.eduX86_64LiveProcess::X86_64LiveProcess(LiveProcessParams *params, 965956Sgblack@eecs.umich.edu ObjectFile *objFile, SyscallDesc *_syscallDescs, 975956Sgblack@eecs.umich.edu int _numSyscallDescs) : 985956Sgblack@eecs.umich.edu X86LiveProcess(params, objFile, _syscallDescs, _numSyscallDescs) 995956Sgblack@eecs.umich.edu{ 1006709Svince@csl.cornell.edu 1016709Svince@csl.cornell.edu vsyscallPage.base = 0xffffffffff600000ULL; 10210318Sandreas.hansson@arm.com vsyscallPage.size = PageBytes; 1036709Svince@csl.cornell.edu vsyscallPage.vtimeOffset = 0x400; 1049679Smjleven@sandia.gov vsyscallPage.vgettimeofdayOffset = 0x0; 1056709Svince@csl.cornell.edu 1064786Sgblack@eecs.umich.edu // Set up stack. On X86_64 Linux, stack goes from the top of memory 1074786Sgblack@eecs.umich.edu // downward, less the hole for the kernel address space plus one page 1084786Sgblack@eecs.umich.edu // for undertermined purposes. 1094793Sgblack@eecs.umich.edu stack_base = (Addr)0x7FFFFFFFF000ULL; 1104166Sgblack@eecs.umich.edu 1115956Sgblack@eecs.umich.edu // Set pointer for next thread stack. Reserve 8M for main stack. 1125956Sgblack@eecs.umich.edu next_thread_stack_base = stack_base - (8 * 1024 * 1024); 1135956Sgblack@eecs.umich.edu 1144820Sgblack@eecs.umich.edu // Set up region for mmaps. This was determined empirically and may not 1154820Sgblack@eecs.umich.edu // always be correct. 1165188Sgblack@eecs.umich.edu mmap_start = mmap_end = (Addr)0x2aaaaaaab000ULL; 1174166Sgblack@eecs.umich.edu} 1184166Sgblack@eecs.umich.edu 1195973Sgblack@eecs.umich.eduvoid 1205973Sgblack@eecs.umich.eduI386LiveProcess::syscall(int64_t callnum, ThreadContext *tc) 1215973Sgblack@eecs.umich.edu{ 1227720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 1237720Sgblack@eecs.umich.edu Addr eip = pc.pc(); 1245973Sgblack@eecs.umich.edu if (eip >= vsyscallPage.base && 1255973Sgblack@eecs.umich.edu eip < vsyscallPage.base + vsyscallPage.size) { 1267720Sgblack@eecs.umich.edu pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset); 1277720Sgblack@eecs.umich.edu tc->pcState(pc); 1285973Sgblack@eecs.umich.edu } 1295973Sgblack@eecs.umich.edu X86LiveProcess::syscall(callnum, tc); 1305973Sgblack@eecs.umich.edu} 1315973Sgblack@eecs.umich.edu 1325973Sgblack@eecs.umich.edu 1335956Sgblack@eecs.umich.eduI386LiveProcess::I386LiveProcess(LiveProcessParams *params, 1345956Sgblack@eecs.umich.edu ObjectFile *objFile, SyscallDesc *_syscallDescs, 1355956Sgblack@eecs.umich.edu int _numSyscallDescs) : 1365956Sgblack@eecs.umich.edu X86LiveProcess(params, objFile, _syscallDescs, _numSyscallDescs) 1374166Sgblack@eecs.umich.edu{ 1389026Sgblack@eecs.umich.edu _gdtStart = ULL(0xffffd000); 13910318Sandreas.hansson@arm.com _gdtSize = PageBytes; 1405973Sgblack@eecs.umich.edu 1415973Sgblack@eecs.umich.edu vsyscallPage.base = 0xffffe000ULL; 14210318Sandreas.hansson@arm.com vsyscallPage.size = PageBytes; 1435973Sgblack@eecs.umich.edu vsyscallPage.vsyscallOffset = 0x400; 1445973Sgblack@eecs.umich.edu vsyscallPage.vsysexitOffset = 0x410; 1455973Sgblack@eecs.umich.edu 1469026Sgblack@eecs.umich.edu stack_base = _gdtStart; 1475956Sgblack@eecs.umich.edu 1485956Sgblack@eecs.umich.edu // Set pointer for next thread stack. Reserve 8M for main stack. 1495956Sgblack@eecs.umich.edu next_thread_stack_base = stack_base - (8 * 1024 * 1024); 1505956Sgblack@eecs.umich.edu 1515956Sgblack@eecs.umich.edu // Set up region for mmaps. This was determined empirically and may not 1525956Sgblack@eecs.umich.edu // always be correct. 1536673Sgblack@eecs.umich.edu mmap_start = mmap_end = (Addr)0xf7ffe000ULL; 1545956Sgblack@eecs.umich.edu} 1555956Sgblack@eecs.umich.edu 1565956Sgblack@eecs.umich.eduSyscallDesc* 1575956Sgblack@eecs.umich.eduX86LiveProcess::getDesc(int callnum) 1585956Sgblack@eecs.umich.edu{ 1595956Sgblack@eecs.umich.edu if (callnum < 0 || callnum >= numSyscallDescs) 1605956Sgblack@eecs.umich.edu return NULL; 1615956Sgblack@eecs.umich.edu return &syscallDescs[callnum]; 1624166Sgblack@eecs.umich.edu} 1634166Sgblack@eecs.umich.edu 1644166Sgblack@eecs.umich.eduvoid 1657532Ssteve.reinhardt@amd.comX86_64LiveProcess::initState() 1664166Sgblack@eecs.umich.edu{ 1677532Ssteve.reinhardt@amd.com X86LiveProcess::initState(); 1685183Ssaidi@eecs.umich.edu 16910318Sandreas.hansson@arm.com argsInit(sizeof(uint64_t), PageBytes); 1705140Sgblack@eecs.umich.edu 1716709Svince@csl.cornell.edu // Set up the vsyscall page for this process. 1728601Ssteve.reinhardt@amd.com allocateMem(vsyscallPage.base, vsyscallPage.size); 1736709Svince@csl.cornell.edu uint8_t vtimeBlob[] = { 1746709Svince@csl.cornell.edu 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax 1756709Svince@csl.cornell.edu 0x0f,0x05, // syscall 1766709Svince@csl.cornell.edu 0xc3 // retq 1776709Svince@csl.cornell.edu }; 1788852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset, 1796709Svince@csl.cornell.edu vtimeBlob, sizeof(vtimeBlob)); 1806709Svince@csl.cornell.edu 1816709Svince@csl.cornell.edu uint8_t vgettimeofdayBlob[] = { 1826709Svince@csl.cornell.edu 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax 1836709Svince@csl.cornell.edu 0x0f,0x05, // syscall 1846709Svince@csl.cornell.edu 0xc3 // retq 1856709Svince@csl.cornell.edu }; 1868852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset, 1876709Svince@csl.cornell.edu vgettimeofdayBlob, sizeof(vgettimeofdayBlob)); 1886709Svince@csl.cornell.edu 18910554Salexandru.dutu@amd.com if (kvmInSE) { 19010554Salexandru.dutu@amd.com PortProxy physProxy = system->physProxy; 1915140Sgblack@eecs.umich.edu 19210554Salexandru.dutu@amd.com /* 19310554Salexandru.dutu@amd.com * Set up the gdt. 19410554Salexandru.dutu@amd.com */ 19510554Salexandru.dutu@amd.com uint8_t numGDTEntries = 0; 19610554Salexandru.dutu@amd.com uint64_t nullDescriptor = 0; 19710554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 19810554Salexandru.dutu@amd.com (uint8_t *)(&nullDescriptor), 8); 19910554Salexandru.dutu@amd.com numGDTEntries++; 2005140Sgblack@eecs.umich.edu 20110554Salexandru.dutu@amd.com SegDescriptor initDesc = 0; 20210554Salexandru.dutu@amd.com initDesc.type.codeOrData = 0; // code or data type 20310554Salexandru.dutu@amd.com initDesc.type.c = 0; // conforming 20410554Salexandru.dutu@amd.com initDesc.type.r = 1; // readable 20510554Salexandru.dutu@amd.com initDesc.dpl = 0; // privilege 20610554Salexandru.dutu@amd.com initDesc.p = 1; // present 20710554Salexandru.dutu@amd.com initDesc.l = 1; // longmode - 64 bit 20810554Salexandru.dutu@amd.com initDesc.d = 0; // operand size 20910554Salexandru.dutu@amd.com initDesc.g = 1; // granularity 21010554Salexandru.dutu@amd.com initDesc.s = 1; // system segment 21110554Salexandru.dutu@amd.com initDesc.limitHigh = 0xFFFF; 21210554Salexandru.dutu@amd.com initDesc.limitLow = 0xF; 21310554Salexandru.dutu@amd.com initDesc.baseHigh = 0x0; 21410554Salexandru.dutu@amd.com initDesc.baseLow = 0x0; 21510554Salexandru.dutu@amd.com 21610554Salexandru.dutu@amd.com //64 bit code segment 21710554Salexandru.dutu@amd.com SegDescriptor csLowPLDesc = initDesc; 21810554Salexandru.dutu@amd.com csLowPLDesc.type.codeOrData = 1; 21910554Salexandru.dutu@amd.com csLowPLDesc.dpl = 0; 22010554Salexandru.dutu@amd.com uint64_t csLowPLDescVal = csLowPLDesc; 22110554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 22210554Salexandru.dutu@amd.com (uint8_t *)(&csLowPLDescVal), 8); 22310554Salexandru.dutu@amd.com 22410554Salexandru.dutu@amd.com numGDTEntries++; 22510554Salexandru.dutu@amd.com 22610554Salexandru.dutu@amd.com SegSelector csLowPL = 0; 22710554Salexandru.dutu@amd.com csLowPL.si = numGDTEntries - 1; 22810554Salexandru.dutu@amd.com csLowPL.rpl = 0; 22910554Salexandru.dutu@amd.com 23010554Salexandru.dutu@amd.com //64 bit data segment 23110554Salexandru.dutu@amd.com SegDescriptor dsLowPLDesc = initDesc; 23210554Salexandru.dutu@amd.com dsLowPLDesc.type.codeOrData = 0; 23310554Salexandru.dutu@amd.com dsLowPLDesc.dpl = 0; 23410554Salexandru.dutu@amd.com uint64_t dsLowPLDescVal = dsLowPLDesc; 23510554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 23610554Salexandru.dutu@amd.com (uint8_t *)(&dsLowPLDescVal), 8); 23710554Salexandru.dutu@amd.com 23810554Salexandru.dutu@amd.com numGDTEntries++; 23910554Salexandru.dutu@amd.com 24010554Salexandru.dutu@amd.com SegSelector dsLowPL = 0; 24110554Salexandru.dutu@amd.com dsLowPL.si = numGDTEntries - 1; 24210554Salexandru.dutu@amd.com dsLowPL.rpl = 0; 24310554Salexandru.dutu@amd.com 24410554Salexandru.dutu@amd.com //64 bit data segment 24510554Salexandru.dutu@amd.com SegDescriptor dsDesc = initDesc; 24610554Salexandru.dutu@amd.com dsDesc.type.codeOrData = 0; 24710554Salexandru.dutu@amd.com dsDesc.dpl = 3; 24810554Salexandru.dutu@amd.com uint64_t dsDescVal = dsDesc; 24910554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 25010554Salexandru.dutu@amd.com (uint8_t *)(&dsDescVal), 8); 25110554Salexandru.dutu@amd.com 25210554Salexandru.dutu@amd.com numGDTEntries++; 25310554Salexandru.dutu@amd.com 25410554Salexandru.dutu@amd.com SegSelector ds = 0; 25510554Salexandru.dutu@amd.com ds.si = numGDTEntries - 1; 25610554Salexandru.dutu@amd.com ds.rpl = 3; 25710554Salexandru.dutu@amd.com 25810554Salexandru.dutu@amd.com //64 bit code segment 25910554Salexandru.dutu@amd.com SegDescriptor csDesc = initDesc; 26010554Salexandru.dutu@amd.com csDesc.type.codeOrData = 1; 26110554Salexandru.dutu@amd.com csDesc.dpl = 3; 26210554Salexandru.dutu@amd.com uint64_t csDescVal = csDesc; 26310554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 26410554Salexandru.dutu@amd.com (uint8_t *)(&csDescVal), 8); 26510554Salexandru.dutu@amd.com 26610554Salexandru.dutu@amd.com numGDTEntries++; 26710554Salexandru.dutu@amd.com 26810554Salexandru.dutu@amd.com SegSelector cs = 0; 26910554Salexandru.dutu@amd.com cs.si = numGDTEntries - 1; 27010554Salexandru.dutu@amd.com cs.rpl = 3; 27110554Salexandru.dutu@amd.com 27210554Salexandru.dutu@amd.com SegSelector scall = 0; 27310554Salexandru.dutu@amd.com scall.si = csLowPL.si; 27410554Salexandru.dutu@amd.com scall.rpl = 0; 27510554Salexandru.dutu@amd.com 27610554Salexandru.dutu@amd.com SegSelector sret = 0; 27710554Salexandru.dutu@amd.com sret.si = dsLowPL.si; 27810554Salexandru.dutu@amd.com sret.rpl = 3; 27910554Salexandru.dutu@amd.com 28010554Salexandru.dutu@amd.com /* In long mode the TSS has been extended to 16 Bytes */ 28110554Salexandru.dutu@amd.com TSSlow TSSDescLow = 0; 28210554Salexandru.dutu@amd.com TSSDescLow.type = 0xB; 28310554Salexandru.dutu@amd.com TSSDescLow.dpl = 0; // Privelege level 0 28410554Salexandru.dutu@amd.com TSSDescLow.p = 1; // Present 28510554Salexandru.dutu@amd.com TSSDescLow.g = 1; // Page granularity 28610554Salexandru.dutu@amd.com TSSDescLow.limitHigh = 0xF; 28710554Salexandru.dutu@amd.com TSSDescLow.limitLow = 0xFFFF; 28810554Salexandru.dutu@amd.com TSSDescLow.baseLow = (((uint32_t)TSSVirtAddr) << 8) >> 8; 28910554Salexandru.dutu@amd.com TSSDescLow.baseHigh = (uint8_t)(((uint32_t)TSSVirtAddr) >> 24); 29010554Salexandru.dutu@amd.com 29110554Salexandru.dutu@amd.com TSShigh TSSDescHigh = 0; 29210554Salexandru.dutu@amd.com TSSDescHigh.base = (uint32_t)(TSSVirtAddr >> 32); 29310554Salexandru.dutu@amd.com 29410554Salexandru.dutu@amd.com struct TSSDesc { 29510554Salexandru.dutu@amd.com uint64_t low; 29610554Salexandru.dutu@amd.com uint64_t high; 29710554Salexandru.dutu@amd.com } tssDescVal = {TSSDescLow, TSSDescHigh}; 29810554Salexandru.dutu@amd.com 29910554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 30010554Salexandru.dutu@amd.com (uint8_t *)(&tssDescVal), sizeof(tssDescVal)); 30110554Salexandru.dutu@amd.com 30210554Salexandru.dutu@amd.com numGDTEntries++; 30310554Salexandru.dutu@amd.com 30410554Salexandru.dutu@amd.com SegSelector tssSel = 0; 30510554Salexandru.dutu@amd.com tssSel.si = numGDTEntries - 1; 30610554Salexandru.dutu@amd.com 30710554Salexandru.dutu@amd.com uint64_t tss_base_addr = (TSSDescHigh.base << 32) | ((TSSDescLow.baseHigh << 24) | TSSDescLow.baseLow); 30810554Salexandru.dutu@amd.com uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16); 30910554Salexandru.dutu@amd.com 31010554Salexandru.dutu@amd.com SegAttr tss_attr = 0; 31110554Salexandru.dutu@amd.com 31210554Salexandru.dutu@amd.com tss_attr.type = TSSDescLow.type; 31310554Salexandru.dutu@amd.com tss_attr.dpl = TSSDescLow.dpl; 31410554Salexandru.dutu@amd.com tss_attr.present = TSSDescLow.p; 31510554Salexandru.dutu@amd.com tss_attr.granularity = TSSDescLow.g; 31610554Salexandru.dutu@amd.com tss_attr.unusable = 0; 31710554Salexandru.dutu@amd.com 31810554Salexandru.dutu@amd.com for (int i = 0; i < contextIds.size(); i++) { 31910554Salexandru.dutu@amd.com ThreadContext * tc = system->getThreadContext(contextIds[i]); 32010554Salexandru.dutu@amd.com 32110554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CS, (MiscReg)cs); 32210554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_DS, (MiscReg)ds); 32310554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_ES, (MiscReg)ds); 32410554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_FS, (MiscReg)ds); 32510554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_GS, (MiscReg)ds); 32610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SS, (MiscReg)ds); 32710554Salexandru.dutu@amd.com 32810554Salexandru.dutu@amd.com // LDT 32910554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSL, 0); 33010554Salexandru.dutu@amd.com SegAttr tslAttr = 0; 33110554Salexandru.dutu@amd.com tslAttr.present = 1; 33210554Salexandru.dutu@amd.com tslAttr.type = 2; 33310554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr); 33410554Salexandru.dutu@amd.com 33510554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 33610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 33710554Salexandru.dutu@amd.com 33810554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TR, (MiscReg)tssSel); 33910554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SEG_BASE(SYS_SEGMENT_REG_TR), tss_base_addr); 34010554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SEG_EFF_BASE(SYS_SEGMENT_REG_TR), 0); 34110554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SEG_LIMIT(SYS_SEGMENT_REG_TR), tss_limit); 34210554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SEG_ATTR(SYS_SEGMENT_REG_TR), (MiscReg)tss_attr); 34310554Salexandru.dutu@amd.com 34410554Salexandru.dutu@amd.com //Start using longmode segments. 34510554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 34610554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 34710554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 34810554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 34910554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 35010554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 35110554Salexandru.dutu@amd.com 35210554Salexandru.dutu@amd.com Efer efer = 0; 35310554Salexandru.dutu@amd.com efer.sce = 1; // Enable system call extensions. 35410554Salexandru.dutu@amd.com efer.lme = 1; // Enable long mode. 35510554Salexandru.dutu@amd.com efer.lma = 1; // Activate long mode. 35610554Salexandru.dutu@amd.com efer.nxe = 0; // Enable nx support. 35710554Salexandru.dutu@amd.com efer.svme = 1; // Enable svm support for now. 35810554Salexandru.dutu@amd.com efer.ffxsr = 0; // Turn on fast fxsave and fxrstor. 35910554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_EFER, efer); 36010554Salexandru.dutu@amd.com 36110554Salexandru.dutu@amd.com //Set up the registers that describe the operating mode. 36210554Salexandru.dutu@amd.com CR0 cr0 = 0; 36310554Salexandru.dutu@amd.com cr0.pg = 1; // Turn on paging. 36410554Salexandru.dutu@amd.com cr0.cd = 0; // Don't disable caching. 36510554Salexandru.dutu@amd.com cr0.nw = 0; // This is bit is defined to be ignored. 36610554Salexandru.dutu@amd.com cr0.am = 1; // No alignment checking 36710554Salexandru.dutu@amd.com cr0.wp = 1; // Supervisor mode can write read only pages 36810554Salexandru.dutu@amd.com cr0.ne = 1; 36910554Salexandru.dutu@amd.com cr0.et = 1; // This should always be 1 37010554Salexandru.dutu@amd.com cr0.ts = 0; // We don't do task switching, so causing fp exceptions 37110554Salexandru.dutu@amd.com // would be pointless. 37210554Salexandru.dutu@amd.com cr0.em = 0; // Allow x87 instructions to execute natively. 37310554Salexandru.dutu@amd.com cr0.mp = 1; // This doesn't really matter, but the manual suggests 37410554Salexandru.dutu@amd.com // setting it to one. 37510554Salexandru.dutu@amd.com cr0.pe = 1; // We're definitely in protected mode. 37610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR0, cr0); 37710554Salexandru.dutu@amd.com 37810554Salexandru.dutu@amd.com CR0 cr2 = 0; 37910554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR2, cr2); 38010554Salexandru.dutu@amd.com 38110554Salexandru.dutu@amd.com CR3 cr3 = pageTablePhysAddr; 38210554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR3, cr3); 38310554Salexandru.dutu@amd.com 38410554Salexandru.dutu@amd.com CR4 cr4 = 0; 38510554Salexandru.dutu@amd.com //Turn on pae. 38610554Salexandru.dutu@amd.com cr4.osxsave = 1; // Enable XSAVE and Proc Extended States 38710554Salexandru.dutu@amd.com cr4.osxmmexcpt = 1; // Operating System Unmasked Exception 38810554Salexandru.dutu@amd.com cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support 38910554Salexandru.dutu@amd.com cr4.pce = 0; // Performance-Monitoring Counter Enable 39010554Salexandru.dutu@amd.com cr4.pge = 0; // Page-Global Enable 39110554Salexandru.dutu@amd.com cr4.mce = 0; // Machine Check Enable 39210554Salexandru.dutu@amd.com cr4.pae = 1; // Physical-Address Extension 39310554Salexandru.dutu@amd.com cr4.pse = 0; // Page Size Extensions 39410554Salexandru.dutu@amd.com cr4.de = 0; // Debugging Extensions 39510554Salexandru.dutu@amd.com cr4.tsd = 0; // Time Stamp Disable 39610554Salexandru.dutu@amd.com cr4.pvi = 0; // Protected-Mode Virtual Interrupts 39710554Salexandru.dutu@amd.com cr4.vme = 0; // Virtual-8086 Mode Extensions 39810554Salexandru.dutu@amd.com 39910554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR4, cr4); 40010554Salexandru.dutu@amd.com 40110554Salexandru.dutu@amd.com CR4 cr8 = 0; 40210554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR8, cr8); 40310554Salexandru.dutu@amd.com 40410554Salexandru.dutu@amd.com const Addr PageMapLevel4 = pageTablePhysAddr; 40510554Salexandru.dutu@amd.com //Point to the page tables. 40610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 40710554Salexandru.dutu@amd.com 40810554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 40910554Salexandru.dutu@amd.com 41010554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900); 41110554Salexandru.dutu@amd.com 41210554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SEG_BASE(MISCREG_TSG - MISCREG_SEG_SEL_BASE), GDTVirtAddr); 41310554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SEG_LIMIT(MISCREG_TSG - MISCREG_SEG_SEL_BASE), 0xffff); 41410554Salexandru.dutu@amd.com 41510554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SEG_BASE(MISCREG_IDTR - MISCREG_SEG_SEL_BASE), IDTVirtAddr); 41610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SEG_LIMIT(MISCREG_IDTR - MISCREG_SEG_SEL_BASE), 0xffff); 41710554Salexandru.dutu@amd.com 41810554Salexandru.dutu@amd.com /* enabling syscall and sysret */ 41910554Salexandru.dutu@amd.com MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32); 42010554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_STAR, star); 42110554Salexandru.dutu@amd.com MiscReg lstar = (MiscReg) syscallCodeVirtAddr; 42210554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_LSTAR, lstar); 42310554Salexandru.dutu@amd.com MiscReg sfmask = (1<<8) | (1<<10); // TF | DF 42410554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SF_MASK, sfmask); 4255140Sgblack@eecs.umich.edu } 4265140Sgblack@eecs.umich.edu 42710554Salexandru.dutu@amd.com /* 42810554Salexandru.dutu@amd.com * Setting up the content of the TSS 42910554Salexandru.dutu@amd.com * and writting it to physical memory 43010554Salexandru.dutu@amd.com */ 4315140Sgblack@eecs.umich.edu 43210554Salexandru.dutu@amd.com struct { 43310554Salexandru.dutu@amd.com uint32_t reserved0; // +00h 43410554Salexandru.dutu@amd.com uint32_t RSP0_low; // +04h 43510554Salexandru.dutu@amd.com uint32_t RSP0_high; // +08h 43610554Salexandru.dutu@amd.com uint32_t RSP1_low; // +0Ch 43710554Salexandru.dutu@amd.com uint32_t RSP1_high; // +10h 43810554Salexandru.dutu@amd.com uint32_t RSP2_low; // +14h 43910554Salexandru.dutu@amd.com uint32_t RSP2_high; // +18h 44010554Salexandru.dutu@amd.com uint32_t reserved1; // +1Ch 44110554Salexandru.dutu@amd.com uint32_t reserved2; // +20h 44210554Salexandru.dutu@amd.com uint32_t IST1_low; // +24h 44310554Salexandru.dutu@amd.com uint32_t IST1_high; // +28h 44410554Salexandru.dutu@amd.com uint32_t IST2_low; // +2Ch 44510554Salexandru.dutu@amd.com uint32_t IST2_high; // +30h 44610554Salexandru.dutu@amd.com uint32_t IST3_low; // +34h 44710554Salexandru.dutu@amd.com uint32_t IST3_high; // +38h 44810554Salexandru.dutu@amd.com uint32_t IST4_low; // +3Ch 44910554Salexandru.dutu@amd.com uint32_t IST4_high; // +40h 45010554Salexandru.dutu@amd.com uint32_t IST5_low; // +44h 45110554Salexandru.dutu@amd.com uint32_t IST5_high; // +48h 45210554Salexandru.dutu@amd.com uint32_t IST6_low; // +4Ch 45310554Salexandru.dutu@amd.com uint32_t IST6_high; // +50h 45410554Salexandru.dutu@amd.com uint32_t IST7_low; // +54h 45510554Salexandru.dutu@amd.com uint32_t IST7_high; // +58h 45610554Salexandru.dutu@amd.com uint32_t reserved3; // +5Ch 45710554Salexandru.dutu@amd.com uint32_t reserved4; // +60h 45810554Salexandru.dutu@amd.com uint16_t reserved5; // +64h 45910554Salexandru.dutu@amd.com uint16_t IO_MapBase; // +66h 46010554Salexandru.dutu@amd.com } tss; 4615140Sgblack@eecs.umich.edu 46210554Salexandru.dutu@amd.com /** setting Interrupt Stack Table */ 46310554Salexandru.dutu@amd.com uint64_t IST_start = ISTVirtAddr + PageBytes; 46410554Salexandru.dutu@amd.com tss.IST1_low = (uint32_t)IST_start; 46510554Salexandru.dutu@amd.com tss.IST1_high = (uint32_t)(IST_start >> 32); 46610554Salexandru.dutu@amd.com tss.RSP0_low = tss.IST1_low; 46710554Salexandru.dutu@amd.com tss.RSP0_high = tss.IST1_high; 46810554Salexandru.dutu@amd.com tss.RSP1_low = tss.IST1_low; 46910554Salexandru.dutu@amd.com tss.RSP1_high = tss.IST1_high; 47010554Salexandru.dutu@amd.com tss.RSP2_low = tss.IST1_low; 47110554Salexandru.dutu@amd.com tss.RSP2_high = tss.IST1_high; 47210554Salexandru.dutu@amd.com physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss)); 4736140Sgblack@eecs.umich.edu 47410554Salexandru.dutu@amd.com /* Setting IDT gates */ 47510554Salexandru.dutu@amd.com GateDescriptorLow PFGateLow = 0; 47610554Salexandru.dutu@amd.com PFGateLow.offsetHigh = (uint16_t)((uint32_t)PFHandlerVirtAddr >> 16); 47710554Salexandru.dutu@amd.com PFGateLow.offsetLow = (uint16_t)PFHandlerVirtAddr; 47810554Salexandru.dutu@amd.com PFGateLow.selector = (MiscReg)csLowPL; 47910554Salexandru.dutu@amd.com PFGateLow.p = 1; 48010554Salexandru.dutu@amd.com PFGateLow.dpl = 0; 48110554Salexandru.dutu@amd.com PFGateLow.type = 0xe; // gate interrupt type 48210554Salexandru.dutu@amd.com PFGateLow.IST = 0; // setting IST to 0 and using RSP0 4836609Sgblack@eecs.umich.edu 48410554Salexandru.dutu@amd.com GateDescriptorHigh PFGateHigh = 0; 48510554Salexandru.dutu@amd.com PFGateHigh.offset = (uint32_t)(PFHandlerVirtAddr >> 32); 48610554Salexandru.dutu@amd.com 48710554Salexandru.dutu@amd.com struct { 48810554Salexandru.dutu@amd.com uint64_t low; 48910554Salexandru.dutu@amd.com uint64_t high; 49010554Salexandru.dutu@amd.com } PFGate = {PFGateLow, PFGateHigh}; 49110554Salexandru.dutu@amd.com 49210554Salexandru.dutu@amd.com physProxy.writeBlob(IDTPhysAddr + 0xE0, 49310554Salexandru.dutu@amd.com (uint8_t *)(&PFGate), sizeof(PFGate)); 49410554Salexandru.dutu@amd.com 49510554Salexandru.dutu@amd.com /** System call handler */ 49610554Salexandru.dutu@amd.com uint8_t syscallBlob[] = { 49710554Salexandru.dutu@amd.com 0x48,0xa3,0x00,0x60,0x00, 49810554Salexandru.dutu@amd.com 0x00,0x00,0xc9,0xff,0xff, // mov %rax, (0xffffc90000005600) 49910554Salexandru.dutu@amd.com 0x48,0x0f,0x07, // sysret 50010554Salexandru.dutu@amd.com }; 50110554Salexandru.dutu@amd.com 50210554Salexandru.dutu@amd.com physProxy.writeBlob(syscallCodePhysAddr, 50310554Salexandru.dutu@amd.com syscallBlob, sizeof(syscallBlob)); 50410554Salexandru.dutu@amd.com 50510554Salexandru.dutu@amd.com /** Page fault handler */ 50610554Salexandru.dutu@amd.com uint8_t faultBlob[] = { 50710554Salexandru.dutu@amd.com 0x48,0xa3,0x00,0x61,0x00, 50810554Salexandru.dutu@amd.com 0x00,0x00,0xc9,0xff,0xff, // mov %rax, (0xffffc90000005700) 50910554Salexandru.dutu@amd.com 0x48,0x83,0xc4,0x08, // add $0x8,%rsp # skip error 51010554Salexandru.dutu@amd.com 0x48,0xcf, // iretq 51110554Salexandru.dutu@amd.com }; 51210554Salexandru.dutu@amd.com 51310554Salexandru.dutu@amd.com physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob)); 51410554Salexandru.dutu@amd.com 51510554Salexandru.dutu@amd.com MultiLevelPageTable<PageTableOps> *pt = 51610554Salexandru.dutu@amd.com dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable); 51710554Salexandru.dutu@amd.com 51810554Salexandru.dutu@amd.com /* Syscall handler */ 51910554Salexandru.dutu@amd.com pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false); 52010554Salexandru.dutu@amd.com /* GDT */ 52110554Salexandru.dutu@amd.com pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false); 52210554Salexandru.dutu@amd.com /* IDT */ 52310554Salexandru.dutu@amd.com pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false); 52410554Salexandru.dutu@amd.com /* TSS */ 52510554Salexandru.dutu@amd.com pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false); 52610554Salexandru.dutu@amd.com /* IST */ 52710554Salexandru.dutu@amd.com pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false); 52810554Salexandru.dutu@amd.com /* PF handler */ 52910554Salexandru.dutu@amd.com pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false); 53010554Salexandru.dutu@amd.com /* MMIO region for m5ops */ 53110554Salexandru.dutu@amd.com pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false); 53210554Salexandru.dutu@amd.com } else { 53310554Salexandru.dutu@amd.com for (int i = 0; i < contextIds.size(); i++) { 53410554Salexandru.dutu@amd.com ThreadContext * tc = system->getThreadContext(contextIds[i]); 53510554Salexandru.dutu@amd.com 53610554Salexandru.dutu@amd.com SegAttr dataAttr = 0; 53710554Salexandru.dutu@amd.com dataAttr.dpl = 3; 53810554Salexandru.dutu@amd.com dataAttr.unusable = 0; 53910554Salexandru.dutu@amd.com dataAttr.defaultSize = 1; 54010554Salexandru.dutu@amd.com dataAttr.longMode = 1; 54110554Salexandru.dutu@amd.com dataAttr.avl = 0; 54210554Salexandru.dutu@amd.com dataAttr.granularity = 1; 54310554Salexandru.dutu@amd.com dataAttr.present = 1; 54410554Salexandru.dutu@amd.com dataAttr.type = 3; 54510554Salexandru.dutu@amd.com dataAttr.writable = 1; 54610554Salexandru.dutu@amd.com dataAttr.readable = 1; 54710554Salexandru.dutu@amd.com dataAttr.expandDown = 0; 54810554Salexandru.dutu@amd.com dataAttr.system = 1; 54910554Salexandru.dutu@amd.com 55010554Salexandru.dutu@amd.com //Initialize the segment registers. 55110554Salexandru.dutu@amd.com for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 55210554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 55310554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 55410554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 55510554Salexandru.dutu@amd.com } 55610554Salexandru.dutu@amd.com 55710554Salexandru.dutu@amd.com SegAttr csAttr = 0; 55810554Salexandru.dutu@amd.com csAttr.dpl = 3; 55910554Salexandru.dutu@amd.com csAttr.unusable = 0; 56010554Salexandru.dutu@amd.com csAttr.defaultSize = 0; 56110554Salexandru.dutu@amd.com csAttr.longMode = 1; 56210554Salexandru.dutu@amd.com csAttr.avl = 0; 56310554Salexandru.dutu@amd.com csAttr.granularity = 1; 56410554Salexandru.dutu@amd.com csAttr.present = 1; 56510554Salexandru.dutu@amd.com csAttr.type = 10; 56610554Salexandru.dutu@amd.com csAttr.writable = 0; 56710554Salexandru.dutu@amd.com csAttr.readable = 1; 56810554Salexandru.dutu@amd.com csAttr.expandDown = 0; 56910554Salexandru.dutu@amd.com csAttr.system = 1; 57010554Salexandru.dutu@amd.com 57110554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 57210554Salexandru.dutu@amd.com 57310554Salexandru.dutu@amd.com Efer efer = 0; 57410554Salexandru.dutu@amd.com efer.sce = 1; // Enable system call extensions. 57510554Salexandru.dutu@amd.com efer.lme = 1; // Enable long mode. 57610554Salexandru.dutu@amd.com efer.lma = 1; // Activate long mode. 57710554Salexandru.dutu@amd.com efer.nxe = 1; // Enable nx support. 57810554Salexandru.dutu@amd.com efer.svme = 0; // Disable svm support for now. It isn't implemented. 57910554Salexandru.dutu@amd.com efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 58010554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_EFER, efer); 58110554Salexandru.dutu@amd.com 58210554Salexandru.dutu@amd.com //Set up the registers that describe the operating mode. 58310554Salexandru.dutu@amd.com CR0 cr0 = 0; 58410554Salexandru.dutu@amd.com cr0.pg = 1; // Turn on paging. 58510554Salexandru.dutu@amd.com cr0.cd = 0; // Don't disable caching. 58610554Salexandru.dutu@amd.com cr0.nw = 0; // This is bit is defined to be ignored. 58710554Salexandru.dutu@amd.com cr0.am = 0; // No alignment checking 58810554Salexandru.dutu@amd.com cr0.wp = 0; // Supervisor mode can write read only pages 58910554Salexandru.dutu@amd.com cr0.ne = 1; 59010554Salexandru.dutu@amd.com cr0.et = 1; // This should always be 1 59110554Salexandru.dutu@amd.com cr0.ts = 0; // We don't do task switching, so causing fp exceptions 59210554Salexandru.dutu@amd.com // would be pointless. 59310554Salexandru.dutu@amd.com cr0.em = 0; // Allow x87 instructions to execute natively. 59410554Salexandru.dutu@amd.com cr0.mp = 1; // This doesn't really matter, but the manual suggests 59510554Salexandru.dutu@amd.com // setting it to one. 59610554Salexandru.dutu@amd.com cr0.pe = 1; // We're definitely in protected mode. 59710554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR0, cr0); 59810554Salexandru.dutu@amd.com 59910554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 60010554Salexandru.dutu@amd.com } 6015140Sgblack@eecs.umich.edu } 6024166Sgblack@eecs.umich.edu} 6034166Sgblack@eecs.umich.edu 6044166Sgblack@eecs.umich.eduvoid 6057532Ssteve.reinhardt@amd.comI386LiveProcess::initState() 6064166Sgblack@eecs.umich.edu{ 6077532Ssteve.reinhardt@amd.com X86LiveProcess::initState(); 6085956Sgblack@eecs.umich.edu 60910318Sandreas.hansson@arm.com argsInit(sizeof(uint32_t), PageBytes); 6105956Sgblack@eecs.umich.edu 6115962Sgblack@eecs.umich.edu /* 6125962Sgblack@eecs.umich.edu * Set up a GDT for this process. The whole GDT wouldn't really be for 6135962Sgblack@eecs.umich.edu * this process, but the only parts we care about are. 6145962Sgblack@eecs.umich.edu */ 6158601Ssteve.reinhardt@amd.com allocateMem(_gdtStart, _gdtSize); 6165962Sgblack@eecs.umich.edu uint64_t zero = 0; 6175962Sgblack@eecs.umich.edu assert(_gdtSize % sizeof(zero) == 0); 6185962Sgblack@eecs.umich.edu for (Addr gdtCurrent = _gdtStart; 6195962Sgblack@eecs.umich.edu gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) { 6208852Sandreas.hansson@arm.com initVirtMem.write(gdtCurrent, zero); 6215962Sgblack@eecs.umich.edu } 6225962Sgblack@eecs.umich.edu 6235973Sgblack@eecs.umich.edu // Set up the vsyscall page for this process. 6248601Ssteve.reinhardt@amd.com allocateMem(vsyscallPage.base, vsyscallPage.size); 6255973Sgblack@eecs.umich.edu uint8_t vsyscallBlob[] = { 6265973Sgblack@eecs.umich.edu 0x51, // push %ecx 6275973Sgblack@eecs.umich.edu 0x52, // push %edp 6285973Sgblack@eecs.umich.edu 0x55, // push %ebp 6295973Sgblack@eecs.umich.edu 0x89, 0xe5, // mov %esp, %ebp 6305973Sgblack@eecs.umich.edu 0x0f, 0x34 // sysenter 6315973Sgblack@eecs.umich.edu }; 6328852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset, 6335973Sgblack@eecs.umich.edu vsyscallBlob, sizeof(vsyscallBlob)); 6345973Sgblack@eecs.umich.edu 6355973Sgblack@eecs.umich.edu uint8_t vsysexitBlob[] = { 6365973Sgblack@eecs.umich.edu 0x5d, // pop %ebp 6375973Sgblack@eecs.umich.edu 0x5a, // pop %edx 6385973Sgblack@eecs.umich.edu 0x59, // pop %ecx 6395973Sgblack@eecs.umich.edu 0xc3 // ret 6405973Sgblack@eecs.umich.edu }; 6418852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset, 6425973Sgblack@eecs.umich.edu vsysexitBlob, sizeof(vsysexitBlob)); 6435973Sgblack@eecs.umich.edu 6445956Sgblack@eecs.umich.edu for (int i = 0; i < contextIds.size(); i++) { 6455956Sgblack@eecs.umich.edu ThreadContext * tc = system->getThreadContext(contextIds[i]); 6465956Sgblack@eecs.umich.edu 6475956Sgblack@eecs.umich.edu SegAttr dataAttr = 0; 6486222Sgblack@eecs.umich.edu dataAttr.dpl = 3; 6496222Sgblack@eecs.umich.edu dataAttr.unusable = 0; 6506222Sgblack@eecs.umich.edu dataAttr.defaultSize = 1; 6516222Sgblack@eecs.umich.edu dataAttr.longMode = 0; 6526222Sgblack@eecs.umich.edu dataAttr.avl = 0; 6536222Sgblack@eecs.umich.edu dataAttr.granularity = 1; 6546222Sgblack@eecs.umich.edu dataAttr.present = 1; 6556222Sgblack@eecs.umich.edu dataAttr.type = 3; 6565956Sgblack@eecs.umich.edu dataAttr.writable = 1; 6575956Sgblack@eecs.umich.edu dataAttr.readable = 1; 6585956Sgblack@eecs.umich.edu dataAttr.expandDown = 0; 6596222Sgblack@eecs.umich.edu dataAttr.system = 1; 6605956Sgblack@eecs.umich.edu 6615956Sgblack@eecs.umich.edu //Initialize the segment registers. 6625956Sgblack@eecs.umich.edu for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 6635956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 6645956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 6655956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 6665956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB); 6675959Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1)); 6685956Sgblack@eecs.umich.edu } 6695956Sgblack@eecs.umich.edu 6705956Sgblack@eecs.umich.edu SegAttr csAttr = 0; 6716222Sgblack@eecs.umich.edu csAttr.dpl = 3; 6726222Sgblack@eecs.umich.edu csAttr.unusable = 0; 6736222Sgblack@eecs.umich.edu csAttr.defaultSize = 1; 6746222Sgblack@eecs.umich.edu csAttr.longMode = 0; 6756222Sgblack@eecs.umich.edu csAttr.avl = 0; 6766222Sgblack@eecs.umich.edu csAttr.granularity = 1; 6776222Sgblack@eecs.umich.edu csAttr.present = 1; 6786222Sgblack@eecs.umich.edu csAttr.type = 0xa; 6795956Sgblack@eecs.umich.edu csAttr.writable = 0; 6805956Sgblack@eecs.umich.edu csAttr.readable = 1; 6815956Sgblack@eecs.umich.edu csAttr.expandDown = 0; 6826222Sgblack@eecs.umich.edu csAttr.system = 1; 6835956Sgblack@eecs.umich.edu 6845956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 6855956Sgblack@eecs.umich.edu 6865962Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart); 6875962Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart); 6885962Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1); 6895962Sgblack@eecs.umich.edu 6905963Sgblack@eecs.umich.edu // Set the LDT selector to 0 to deactivate it. 6915963Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSL, 0); 6925963Sgblack@eecs.umich.edu 6936140Sgblack@eecs.umich.edu Efer efer = 0; 6946140Sgblack@eecs.umich.edu efer.sce = 1; // Enable system call extensions. 6956140Sgblack@eecs.umich.edu efer.lme = 1; // Enable long mode. 6966140Sgblack@eecs.umich.edu efer.lma = 0; // Deactivate long mode. 6976140Sgblack@eecs.umich.edu efer.nxe = 1; // Enable nx support. 6986140Sgblack@eecs.umich.edu efer.svme = 0; // Disable svm support for now. It isn't implemented. 6996140Sgblack@eecs.umich.edu efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 7006140Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_EFER, efer); 7016140Sgblack@eecs.umich.edu 7025956Sgblack@eecs.umich.edu //Set up the registers that describe the operating mode. 7035956Sgblack@eecs.umich.edu CR0 cr0 = 0; 7045956Sgblack@eecs.umich.edu cr0.pg = 1; // Turn on paging. 7055956Sgblack@eecs.umich.edu cr0.cd = 0; // Don't disable caching. 7065956Sgblack@eecs.umich.edu cr0.nw = 0; // This is bit is defined to be ignored. 7075956Sgblack@eecs.umich.edu cr0.am = 0; // No alignment checking 7085956Sgblack@eecs.umich.edu cr0.wp = 0; // Supervisor mode can write read only pages 7095956Sgblack@eecs.umich.edu cr0.ne = 1; 7105956Sgblack@eecs.umich.edu cr0.et = 1; // This should always be 1 7115956Sgblack@eecs.umich.edu cr0.ts = 0; // We don't do task switching, so causing fp exceptions 7125956Sgblack@eecs.umich.edu // would be pointless. 7135956Sgblack@eecs.umich.edu cr0.em = 0; // Allow x87 instructions to execute natively. 7145956Sgblack@eecs.umich.edu cr0.mp = 1; // This doesn't really matter, but the manual suggests 7155956Sgblack@eecs.umich.edu // setting it to one. 7165956Sgblack@eecs.umich.edu cr0.pe = 1; // We're definitely in protected mode. 7175956Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, cr0); 7186609Sgblack@eecs.umich.edu 7196609Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 7205956Sgblack@eecs.umich.edu } 7215956Sgblack@eecs.umich.edu} 7225956Sgblack@eecs.umich.edu 7235956Sgblack@eecs.umich.edutemplate<class IntType> 7245956Sgblack@eecs.umich.eduvoid 7255973Sgblack@eecs.umich.eduX86LiveProcess::argsInit(int pageSize, 7265973Sgblack@eecs.umich.edu std::vector<AuxVector<IntType> > extraAuxvs) 7275956Sgblack@eecs.umich.edu{ 7285956Sgblack@eecs.umich.edu int intSize = sizeof(IntType); 7295956Sgblack@eecs.umich.edu 7305956Sgblack@eecs.umich.edu typedef AuxVector<IntType> auxv_t; 7315973Sgblack@eecs.umich.edu std::vector<auxv_t> auxv = extraAuxvs; 7325758Shsul@eecs.umich.edu 7334166Sgblack@eecs.umich.edu string filename; 7344166Sgblack@eecs.umich.edu if(argv.size() < 1) 7354166Sgblack@eecs.umich.edu filename = ""; 7364166Sgblack@eecs.umich.edu else 7374166Sgblack@eecs.umich.edu filename = argv[0]; 7384166Sgblack@eecs.umich.edu 7394793Sgblack@eecs.umich.edu //We want 16 byte alignment 7404849Sgblack@eecs.umich.edu uint64_t align = 16; 7414166Sgblack@eecs.umich.edu 7424166Sgblack@eecs.umich.edu // load object file into target memory 7434166Sgblack@eecs.umich.edu objFile->loadSections(initVirtMem); 7444166Sgblack@eecs.umich.edu 7454793Sgblack@eecs.umich.edu enum X86CpuFeature { 7464793Sgblack@eecs.umich.edu X86_OnboardFPU = 1 << 0, 7474793Sgblack@eecs.umich.edu X86_VirtualModeExtensions = 1 << 1, 7484793Sgblack@eecs.umich.edu X86_DebuggingExtensions = 1 << 2, 7494793Sgblack@eecs.umich.edu X86_PageSizeExtensions = 1 << 3, 7504777Sgblack@eecs.umich.edu 7514793Sgblack@eecs.umich.edu X86_TimeStampCounter = 1 << 4, 7524793Sgblack@eecs.umich.edu X86_ModelSpecificRegisters = 1 << 5, 7534793Sgblack@eecs.umich.edu X86_PhysicalAddressExtensions = 1 << 6, 7544793Sgblack@eecs.umich.edu X86_MachineCheckExtensions = 1 << 7, 7554777Sgblack@eecs.umich.edu 7564793Sgblack@eecs.umich.edu X86_CMPXCHG8Instruction = 1 << 8, 7574793Sgblack@eecs.umich.edu X86_OnboardAPIC = 1 << 9, 7584793Sgblack@eecs.umich.edu X86_SYSENTER_SYSEXIT = 1 << 11, 7594793Sgblack@eecs.umich.edu 7604793Sgblack@eecs.umich.edu X86_MemoryTypeRangeRegisters = 1 << 12, 7614793Sgblack@eecs.umich.edu X86_PageGlobalEnable = 1 << 13, 7624793Sgblack@eecs.umich.edu X86_MachineCheckArchitecture = 1 << 14, 7634793Sgblack@eecs.umich.edu X86_CMOVInstruction = 1 << 15, 7644793Sgblack@eecs.umich.edu 7654793Sgblack@eecs.umich.edu X86_PageAttributeTable = 1 << 16, 7664793Sgblack@eecs.umich.edu X86_36BitPSEs = 1 << 17, 7674793Sgblack@eecs.umich.edu X86_ProcessorSerialNumber = 1 << 18, 7684793Sgblack@eecs.umich.edu X86_CLFLUSHInstruction = 1 << 19, 7694793Sgblack@eecs.umich.edu 7704793Sgblack@eecs.umich.edu X86_DebugTraceStore = 1 << 21, 7714793Sgblack@eecs.umich.edu X86_ACPIViaMSR = 1 << 22, 7724793Sgblack@eecs.umich.edu X86_MultimediaExtensions = 1 << 23, 7734793Sgblack@eecs.umich.edu 7744793Sgblack@eecs.umich.edu X86_FXSAVE_FXRSTOR = 1 << 24, 7754793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions = 1 << 25, 7764793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions2 = 1 << 26, 7774793Sgblack@eecs.umich.edu X86_CPUSelfSnoop = 1 << 27, 7784793Sgblack@eecs.umich.edu 7794793Sgblack@eecs.umich.edu X86_HyperThreading = 1 << 28, 7804793Sgblack@eecs.umich.edu X86_AutomaticClockControl = 1 << 29, 7814793Sgblack@eecs.umich.edu X86_IA64Processor = 1 << 30 7824166Sgblack@eecs.umich.edu }; 7834166Sgblack@eecs.umich.edu 7844166Sgblack@eecs.umich.edu //Setup the auxilliary vectors. These will already have endian conversion. 7854166Sgblack@eecs.umich.edu //Auxilliary vectors are loaded only for elf formatted executables. 7864166Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 7874166Sgblack@eecs.umich.edu if(elfObject) 7884166Sgblack@eecs.umich.edu { 7894793Sgblack@eecs.umich.edu uint64_t features = 7904793Sgblack@eecs.umich.edu X86_OnboardFPU | 7914793Sgblack@eecs.umich.edu X86_VirtualModeExtensions | 7924793Sgblack@eecs.umich.edu X86_DebuggingExtensions | 7934793Sgblack@eecs.umich.edu X86_PageSizeExtensions | 7944793Sgblack@eecs.umich.edu X86_TimeStampCounter | 7954793Sgblack@eecs.umich.edu X86_ModelSpecificRegisters | 7964793Sgblack@eecs.umich.edu X86_PhysicalAddressExtensions | 7974793Sgblack@eecs.umich.edu X86_MachineCheckExtensions | 7984793Sgblack@eecs.umich.edu X86_CMPXCHG8Instruction | 7994793Sgblack@eecs.umich.edu X86_OnboardAPIC | 8004793Sgblack@eecs.umich.edu X86_SYSENTER_SYSEXIT | 8014793Sgblack@eecs.umich.edu X86_MemoryTypeRangeRegisters | 8024793Sgblack@eecs.umich.edu X86_PageGlobalEnable | 8034793Sgblack@eecs.umich.edu X86_MachineCheckArchitecture | 8044793Sgblack@eecs.umich.edu X86_CMOVInstruction | 8054793Sgblack@eecs.umich.edu X86_PageAttributeTable | 8064793Sgblack@eecs.umich.edu X86_36BitPSEs | 8074793Sgblack@eecs.umich.edu// X86_ProcessorSerialNumber | 8084793Sgblack@eecs.umich.edu X86_CLFLUSHInstruction | 8094793Sgblack@eecs.umich.edu// X86_DebugTraceStore | 8104793Sgblack@eecs.umich.edu// X86_ACPIViaMSR | 8114793Sgblack@eecs.umich.edu X86_MultimediaExtensions | 8124793Sgblack@eecs.umich.edu X86_FXSAVE_FXRSTOR | 8134793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions | 8144793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions2 | 8154793Sgblack@eecs.umich.edu// X86_CPUSelfSnoop | 8164793Sgblack@eecs.umich.edu// X86_HyperThreading | 8174793Sgblack@eecs.umich.edu// X86_AutomaticClockControl | 8184793Sgblack@eecs.umich.edu// X86_IA64Processor | 8194793Sgblack@eecs.umich.edu 0; 8204793Sgblack@eecs.umich.edu 8214166Sgblack@eecs.umich.edu //Bits which describe the system hardware capabilities 8224777Sgblack@eecs.umich.edu //XXX Figure out what these should be 8234793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 8244166Sgblack@eecs.umich.edu //The system page size 82510318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes)); 8264166Sgblack@eecs.umich.edu //Frequency at which times() increments 8276363Sgblack@eecs.umich.edu //Defined to be 100 in the kernel source. 8284793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 8294166Sgblack@eecs.umich.edu // For statically linked executables, this is the virtual address of the 8304166Sgblack@eecs.umich.edu // program header tables if they appear in the executable image 8314793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 8324166Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 8334793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 8344166Sgblack@eecs.umich.edu // This is the number of program headers from the original elf file. 8354793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 8364166Sgblack@eecs.umich.edu //This is the address of the elf "interpreter", It should be set 8374166Sgblack@eecs.umich.edu //to 0 for regular executables. It should be something else 8384166Sgblack@eecs.umich.edu //(not sure what) for dynamic libraries. 8394793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_BASE, 0)); 8404777Sgblack@eecs.umich.edu 8414777Sgblack@eecs.umich.edu //XXX Figure out what this should be. 8424793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 8434166Sgblack@eecs.umich.edu //The entry point to the program 8444793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 8454166Sgblack@eecs.umich.edu //Different user and group IDs 8464793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 8474793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 8484793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 8494793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 8504166Sgblack@eecs.umich.edu //Whether to enable "secure mode" in the executable 8514793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 8527073Sgblack@eecs.umich.edu //The address of 16 "random" bytes. 8537073Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 8547073Sgblack@eecs.umich.edu //The name of the program 8557073Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 8567073Sgblack@eecs.umich.edu //The platform string 8574793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 8584166Sgblack@eecs.umich.edu } 8594166Sgblack@eecs.umich.edu 8604166Sgblack@eecs.umich.edu //Figure out how big the initial stack needs to be 8614166Sgblack@eecs.umich.edu 8624849Sgblack@eecs.umich.edu // A sentry NULL void pointer at the top of the stack. 8634849Sgblack@eecs.umich.edu int sentry_size = intSize; 8644166Sgblack@eecs.umich.edu 8654166Sgblack@eecs.umich.edu //This is the name of the file which is present on the initial stack 8664166Sgblack@eecs.umich.edu //It's purpose is to let the user space linker examine the original file. 8674847Sgblack@eecs.umich.edu int file_name_size = filename.size() + 1; 8684793Sgblack@eecs.umich.edu 8697073Sgblack@eecs.umich.edu const int numRandomBytes = 16; 8707073Sgblack@eecs.umich.edu int aux_data_size = numRandomBytes; 8717073Sgblack@eecs.umich.edu 8724793Sgblack@eecs.umich.edu string platform = "x86_64"; 8737073Sgblack@eecs.umich.edu aux_data_size += platform.size() + 1; 8744166Sgblack@eecs.umich.edu 8754166Sgblack@eecs.umich.edu int env_data_size = 0; 8764166Sgblack@eecs.umich.edu for (int i = 0; i < envp.size(); ++i) { 8774847Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 8784166Sgblack@eecs.umich.edu } 8794166Sgblack@eecs.umich.edu int arg_data_size = 0; 8804166Sgblack@eecs.umich.edu for (int i = 0; i < argv.size(); ++i) { 8814847Sgblack@eecs.umich.edu arg_data_size += argv[i].size() + 1; 8824166Sgblack@eecs.umich.edu } 8834166Sgblack@eecs.umich.edu 8844166Sgblack@eecs.umich.edu //The info_block needs to be padded so it's size is a multiple of the 8854166Sgblack@eecs.umich.edu //alignment mask. Also, it appears that there needs to be at least some 8864166Sgblack@eecs.umich.edu //padding, so if the size is already a multiple, we need to increase it 8874166Sgblack@eecs.umich.edu //anyway. 8884849Sgblack@eecs.umich.edu int base_info_block_size = 8894849Sgblack@eecs.umich.edu sentry_size + file_name_size + env_data_size + arg_data_size; 8904166Sgblack@eecs.umich.edu 8914849Sgblack@eecs.umich.edu int info_block_size = roundUp(base_info_block_size, align); 8924849Sgblack@eecs.umich.edu 8934849Sgblack@eecs.umich.edu int info_block_padding = info_block_size - base_info_block_size; 8944166Sgblack@eecs.umich.edu 8954166Sgblack@eecs.umich.edu //Each auxilliary vector is two 8 byte words 8964166Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 8974166Sgblack@eecs.umich.edu 8984166Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 8994166Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 9004166Sgblack@eecs.umich.edu 9014166Sgblack@eecs.umich.edu int argc_size = intSize; 9024166Sgblack@eecs.umich.edu 9034849Sgblack@eecs.umich.edu //Figure out the size of the contents of the actual initial frame 9044849Sgblack@eecs.umich.edu int frame_size = 9054166Sgblack@eecs.umich.edu aux_array_size + 9064166Sgblack@eecs.umich.edu envp_array_size + 9074166Sgblack@eecs.umich.edu argv_array_size + 9084607Sgblack@eecs.umich.edu argc_size; 9094166Sgblack@eecs.umich.edu 9104849Sgblack@eecs.umich.edu //There needs to be padding after the auxiliary vector data so that the 9114849Sgblack@eecs.umich.edu //very bottom of the stack is aligned properly. 9124849Sgblack@eecs.umich.edu int partial_size = frame_size + aux_data_size; 9134849Sgblack@eecs.umich.edu int aligned_partial_size = roundUp(partial_size, align); 9144849Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - partial_size; 9154849Sgblack@eecs.umich.edu 9164849Sgblack@eecs.umich.edu int space_needed = 9174849Sgblack@eecs.umich.edu info_block_size + 9184849Sgblack@eecs.umich.edu aux_data_size + 9194849Sgblack@eecs.umich.edu aux_padding + 9204849Sgblack@eecs.umich.edu frame_size; 9214849Sgblack@eecs.umich.edu 9224166Sgblack@eecs.umich.edu stack_min = stack_base - space_needed; 9234849Sgblack@eecs.umich.edu stack_min = roundDown(stack_min, align); 92410554Salexandru.dutu@amd.com stack_size = roundUp(stack_base - stack_min, pageSize); 9254166Sgblack@eecs.umich.edu 9264166Sgblack@eecs.umich.edu // map memory 92710554Salexandru.dutu@amd.com Addr stack_end = roundDown(stack_base - stack_size, pageSize); 92810554Salexandru.dutu@amd.com 92910554Salexandru.dutu@amd.com DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size); 93010554Salexandru.dutu@amd.com allocateMem(stack_end, stack_size); 9314166Sgblack@eecs.umich.edu 9324166Sgblack@eecs.umich.edu // map out initial stack contents 9335956Sgblack@eecs.umich.edu IntType sentry_base = stack_base - sentry_size; 9345956Sgblack@eecs.umich.edu IntType file_name_base = sentry_base - file_name_size; 9355956Sgblack@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 9365956Sgblack@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 9375956Sgblack@eecs.umich.edu IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size; 9385956Sgblack@eecs.umich.edu IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding; 9395956Sgblack@eecs.umich.edu IntType envp_array_base = auxv_array_base - envp_array_size; 9405956Sgblack@eecs.umich.edu IntType argv_array_base = envp_array_base - argv_array_size; 9415956Sgblack@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 9424166Sgblack@eecs.umich.edu 9435941Sgblack@eecs.umich.edu DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 9445941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - file name\n", file_name_base); 9455941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - env data\n", env_data_base); 9465941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 9475941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 9485941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 9495941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 9505941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 9515941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - argc \n", argc_base); 9525941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - stack min\n", stack_min); 9534166Sgblack@eecs.umich.edu 9544166Sgblack@eecs.umich.edu // write contents to stack 9554166Sgblack@eecs.umich.edu 9564166Sgblack@eecs.umich.edu // figure out argc 9575956Sgblack@eecs.umich.edu IntType argc = argv.size(); 9585956Sgblack@eecs.umich.edu IntType guestArgc = X86ISA::htog(argc); 9594166Sgblack@eecs.umich.edu 9604849Sgblack@eecs.umich.edu //Write out the sentry void * 9615956Sgblack@eecs.umich.edu IntType sentry_NULL = 0; 9628852Sandreas.hansson@arm.com initVirtMem.writeBlob(sentry_base, 9634849Sgblack@eecs.umich.edu (uint8_t*)&sentry_NULL, sentry_size); 9644166Sgblack@eecs.umich.edu 9654166Sgblack@eecs.umich.edu //Write the file name 9668852Sandreas.hansson@arm.com initVirtMem.writeString(file_name_base, filename.c_str()); 9674166Sgblack@eecs.umich.edu 9687073Sgblack@eecs.umich.edu //Fix up the aux vectors which point to data 9697073Sgblack@eecs.umich.edu assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM); 9707073Sgblack@eecs.umich.edu auxv[auxv.size() - 3].a_val = aux_data_base; 9717073Sgblack@eecs.umich.edu assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN); 9727073Sgblack@eecs.umich.edu auxv[auxv.size() - 2].a_val = argv_array_base; 9737073Sgblack@eecs.umich.edu assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM); 9747073Sgblack@eecs.umich.edu auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes; 9754793Sgblack@eecs.umich.edu 9764166Sgblack@eecs.umich.edu //Copy the aux stuff 9774166Sgblack@eecs.umich.edu for(int x = 0; x < auxv.size(); x++) 9784166Sgblack@eecs.umich.edu { 9798852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 9804166Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 9818852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 9824166Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 9834166Sgblack@eecs.umich.edu } 9844166Sgblack@eecs.umich.edu //Write out the terminating zeroed auxilliary vector 9854166Sgblack@eecs.umich.edu const uint64_t zero = 0; 9868852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(), 9874166Sgblack@eecs.umich.edu (uint8_t*)&zero, 2 * intSize); 9884166Sgblack@eecs.umich.edu 9898852Sandreas.hansson@arm.com initVirtMem.writeString(aux_data_base, platform.c_str()); 9904793Sgblack@eecs.umich.edu 9914166Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 9924166Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 9934166Sgblack@eecs.umich.edu 9948852Sandreas.hansson@arm.com initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 9954166Sgblack@eecs.umich.edu 9965713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 9974793Sgblack@eecs.umich.edu //Set the stack pointer register 9985713Shsul@eecs.umich.edu tc->setIntReg(StackPointerReg, stack_min); 9994166Sgblack@eecs.umich.edu 10005246Sgblack@eecs.umich.edu // There doesn't need to be any segment base added in since we're dealing 10015246Sgblack@eecs.umich.edu // with the flat segmentation model. 10027720Sgblack@eecs.umich.edu tc->pcState(objFile->entryPoint()); 10034166Sgblack@eecs.umich.edu 10044166Sgblack@eecs.umich.edu //Align the "stack_min" to a page boundary. 10054166Sgblack@eecs.umich.edu stack_min = roundDown(stack_min, pageSize); 10064166Sgblack@eecs.umich.edu 10074166Sgblack@eecs.umich.edu// num_processes++; 10084166Sgblack@eecs.umich.edu} 10095956Sgblack@eecs.umich.edu 10105956Sgblack@eecs.umich.eduvoid 10115956Sgblack@eecs.umich.eduX86_64LiveProcess::argsInit(int intSize, int pageSize) 10125956Sgblack@eecs.umich.edu{ 10135973Sgblack@eecs.umich.edu std::vector<AuxVector<uint64_t> > extraAuxvs; 10147073Sgblack@eecs.umich.edu extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR, 10157073Sgblack@eecs.umich.edu vsyscallPage.base)); 10165973Sgblack@eecs.umich.edu X86LiveProcess::argsInit<uint64_t>(pageSize, extraAuxvs); 10175956Sgblack@eecs.umich.edu} 10185956Sgblack@eecs.umich.edu 10195956Sgblack@eecs.umich.eduvoid 10205956Sgblack@eecs.umich.eduI386LiveProcess::argsInit(int intSize, int pageSize) 10215956Sgblack@eecs.umich.edu{ 10225973Sgblack@eecs.umich.edu std::vector<AuxVector<uint32_t> > extraAuxvs; 10235973Sgblack@eecs.umich.edu //Tell the binary where the vsyscall part of the vsyscall page is. 10247073Sgblack@eecs.umich.edu extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO, 10255973Sgblack@eecs.umich.edu vsyscallPage.base + vsyscallPage.vsyscallOffset)); 10267073Sgblack@eecs.umich.edu extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR, 10277073Sgblack@eecs.umich.edu vsyscallPage.base)); 10285973Sgblack@eecs.umich.edu X86LiveProcess::argsInit<uint32_t>(pageSize, extraAuxvs); 10295956Sgblack@eecs.umich.edu} 10305958Sgblack@eecs.umich.edu 10315958Sgblack@eecs.umich.eduvoid 103210223Ssteve.reinhardt@amd.comX86LiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn retval) 10335958Sgblack@eecs.umich.edu{ 103410223Ssteve.reinhardt@amd.com tc->setIntReg(INTREG_RAX, retval.encodedValue()); 10355958Sgblack@eecs.umich.edu} 10365958Sgblack@eecs.umich.edu 10375958Sgblack@eecs.umich.eduX86ISA::IntReg 10386701Sgblack@eecs.umich.eduX86_64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 10395958Sgblack@eecs.umich.edu{ 10405958Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10416701Sgblack@eecs.umich.edu return tc->readIntReg(ArgumentReg[i++]); 10425958Sgblack@eecs.umich.edu} 10435958Sgblack@eecs.umich.edu 10445958Sgblack@eecs.umich.eduvoid 10455958Sgblack@eecs.umich.eduX86_64LiveProcess::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 10465958Sgblack@eecs.umich.edu{ 10475958Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10485958Sgblack@eecs.umich.edu return tc->setIntReg(ArgumentReg[i], val); 10495958Sgblack@eecs.umich.edu} 10505958Sgblack@eecs.umich.edu 10515958Sgblack@eecs.umich.eduX86ISA::IntReg 10526701Sgblack@eecs.umich.eduI386LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 10535958Sgblack@eecs.umich.edu{ 10545959Sgblack@eecs.umich.edu assert(i < NumArgumentRegs32); 10556701Sgblack@eecs.umich.edu return tc->readIntReg(ArgumentReg32[i++]); 10566701Sgblack@eecs.umich.edu} 10576701Sgblack@eecs.umich.edu 10586701Sgblack@eecs.umich.eduX86ISA::IntReg 10596701Sgblack@eecs.umich.eduI386LiveProcess::getSyscallArg(ThreadContext *tc, int &i, int width) 10606701Sgblack@eecs.umich.edu{ 10616701Sgblack@eecs.umich.edu assert(width == 32 || width == 64); 10626701Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10636701Sgblack@eecs.umich.edu uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32); 10646701Sgblack@eecs.umich.edu if (width == 64) 10656701Sgblack@eecs.umich.edu retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32); 10666701Sgblack@eecs.umich.edu return retVal; 10675958Sgblack@eecs.umich.edu} 10685958Sgblack@eecs.umich.edu 10695958Sgblack@eecs.umich.eduvoid 10705958Sgblack@eecs.umich.eduI386LiveProcess::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 10715958Sgblack@eecs.umich.edu{ 10725959Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10735959Sgblack@eecs.umich.edu return tc->setIntReg(ArgumentReg[i], val); 10745958Sgblack@eecs.umich.edu} 1075