pagetable.hh revision 9115:6a0ab7d94d4e 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_PAGETABLE_HH__
41#define __ARCH_X86_PAGETABLE_HH__
42
43#include <iostream>
44#include <string>
45
46#include "base/bitunion.hh"
47#include "base/misc.hh"
48#include "base/types.hh"
49#include "base/trie.hh"
50
51class Checkpoint;
52
53namespace X86ISA
54{
55    struct TlbEntry;
56}
57
58typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
59
60namespace X86ISA
61{
62    BitUnion64(VAddr)
63        Bitfield<20, 12> longl1;
64        Bitfield<29, 21> longl2;
65        Bitfield<38, 30> longl3;
66        Bitfield<47, 39> longl4;
67
68        Bitfield<20, 12> pael1;
69        Bitfield<29, 21> pael2;
70        Bitfield<31, 30> pael3;
71
72        Bitfield<21, 12> norml1;
73        Bitfield<31, 22> norml2;
74    EndBitUnion(VAddr)
75
76    struct TlbEntry
77    {
78        // The base of the physical page.
79        Addr paddr;
80
81        // The beginning of the virtual page this entry maps.
82        Addr vaddr;
83        // The size of the page this represents, in address bits.
84        unsigned logBytes;
85
86        // Read permission is always available, assuming it isn't blocked by
87        // other mechanisms.
88        bool writable;
89        // Whether this page is accesible without being in supervisor mode.
90        bool user;
91        // Whether to use write through or write back. M5 ignores this and
92        // lets the caches handle the writeback policy.
93        //bool pwt;
94        // Whether the page is cacheable or not.
95        bool uncacheable;
96        // Whether or not to kick this page out on a write to CR3.
97        bool global;
98        // A bit used to form an index into the PAT table.
99        bool patBit;
100        // Whether or not memory on this page can be executed.
101        bool noExec;
102        // A sequence number to keep track of LRU.
103        uint64_t lruSeq;
104
105        TlbEntryTrie::Handle trieHandle;
106
107        TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
108        TlbEntry() {}
109
110        void
111        updateVaddr(Addr new_vaddr)
112        {
113            vaddr = new_vaddr;
114        }
115
116        Addr pageStart()
117        {
118            return paddr;
119        }
120
121        // Return the page size in bytes
122        int size()
123        {
124            return (1 << logBytes);
125        }
126
127        void serialize(std::ostream &os);
128        void unserialize(Checkpoint *cp, const std::string &section);
129    };
130}
131
132#endif
133