pagetable.hh revision 12457:b9b7bdb5a8ac 
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
41#ifndef __ARCH_X86_PAGETABLE_HH__
42#define __ARCH_X86_PAGETABLE_HH__
43
44#include <iostream>
45#include <string>
46#include <vector>
47
48#include "base/bitunion.hh"
49#include "base/types.hh"
50#include "base/trie.hh"
51#include "arch/x86/system.hh"
52#include "debug/MMU.hh"
53
54class Checkpoint;
55class ThreadContext;
56
57namespace X86ISA
58{
59    struct TlbEntry;
60}
61
62typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
63
64namespace X86ISA
65{
66    BitUnion64(VAddr)
67        Bitfield<20, 12> longl1;
68        Bitfield<29, 21> longl2;
69        Bitfield<38, 30> longl3;
70        Bitfield<47, 39> longl4;
71
72        Bitfield<20, 12> pael1;
73        Bitfield<29, 21> pael2;
74        Bitfield<31, 30> pael3;
75
76        Bitfield<21, 12> norml1;
77        Bitfield<31, 22> norml2;
78    EndBitUnion(VAddr)
79
80    // Unfortunately, the placement of the base field in a page table entry is
81    // very erratic and would make a mess here. It might be moved here at some
82    // point in the future.
83    BitUnion64(PageTableEntry)
84        Bitfield<63> nx;
85        Bitfield<51, 12> base;
86        Bitfield<11, 9> avl;
87        Bitfield<8> g;
88        Bitfield<7> ps;
89        Bitfield<6> d;
90        Bitfield<5> a;
91        Bitfield<4> pcd;
92        Bitfield<3> pwt;
93        Bitfield<2> u;
94        Bitfield<1> w;
95        Bitfield<0> p;
96    EndBitUnion(PageTableEntry)
97
98
99    struct TlbEntry : public Serializable
100    {
101        // The base of the physical page.
102        Addr paddr;
103
104        // The beginning of the virtual page this entry maps.
105        Addr vaddr;
106        // The size of the page this represents, in address bits.
107        unsigned logBytes;
108
109        // Read permission is always available, assuming it isn't blocked by
110        // other mechanisms.
111        bool writable;
112        // Whether this page is accesible without being in supervisor mode.
113        bool user;
114        // Whether to use write through or write back. M5 ignores this and
115        // lets the caches handle the writeback policy.
116        //bool pwt;
117        // Whether the page is cacheable or not.
118        bool uncacheable;
119        // Whether or not to kick this page out on a write to CR3.
120        bool global;
121        // A bit used to form an index into the PAT table.
122        bool patBit;
123        // Whether or not memory on this page can be executed.
124        bool noExec;
125        // A sequence number to keep track of LRU.
126        uint64_t lruSeq;
127
128        TlbEntryTrie::Handle trieHandle;
129
130        TlbEntry(Addr asn, Addr _vaddr, Addr _paddr,
131                 bool uncacheable, bool read_only);
132        TlbEntry();
133
134        void
135        updateVaddr(Addr new_vaddr)
136        {
137            vaddr = new_vaddr;
138        }
139
140        Addr pageStart()
141        {
142            return paddr;
143        }
144
145        // Return the page size in bytes
146        int size()
147        {
148            return (1 << logBytes);
149        }
150
151        void serialize(CheckpointOut &cp) const override;
152        void unserialize(CheckpointIn &cp) override;
153    };
154
155    /** The size of each level of the page table expressed in base 2
156     * logarithmic values
157     */
158    const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9};
159
160    /* x86 specific PTE flags */
161    enum PTEField{
162        PTE_NotPresent  = 1,
163        PTE_Supervisor  = 2,
164        PTE_ReadOnly    = 4,
165        PTE_Uncacheable = 8,
166    };
167
168    /** Page table operations specific to x86 ISA.
169     * Indended to be used as parameter of MultiLevelPageTable.
170     */
171    class PageTableOps
172    {
173      public:
174        void setPTEFields(PageTableEntry& PTE, uint64_t flags = 0)
175        {
176            PTE.p   = flags & PTE_NotPresent  ? 0 : 1;
177            PTE.pcd = flags & PTE_Uncacheable ? 1 : 0;
178            PTE.w   = flags & PTE_ReadOnly    ? 0 : 1;
179            PTE.u   = flags & PTE_Supervisor  ? 0 : 1;
180        }
181
182        /** returns the page number out of a page table entry */
183        Addr getPnum(PageTableEntry PTE)
184        {
185            return PTE.base;
186        }
187
188        bool isUncacheable(const PageTableEntry PTE)
189        {
190            return PTE.pcd;
191        }
192
193        bool isReadOnly(PageTableEntry PTE)
194        {
195            return !PTE.w;
196        }
197
198        /** sets the page number in a page table entry */
199        void setPnum(PageTableEntry& PTE, Addr paddr)
200        {
201            PTE.base = paddr;
202        }
203
204        /** returns the offsets to index in every level of a page
205         * table, contained in a virtual address
206         */
207        std::vector<uint64_t> getOffsets(Addr vaddr)
208        {
209            X86ISA::VAddr addr(vaddr);
210            return {addr.longl1, addr.longl2, addr.longl3, addr.longl4};
211        }
212    };
213
214}
215
216#endif
217