pagetable.hh revision 11168
14159Sgblack@eecs.umich.edu/* 210299Salexandru.dutu@amd.com * Copyright (c) 2014 Advanced Micro Devices, Inc. 34159Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 44159Sgblack@eecs.umich.edu * All rights reserved. 54159Sgblack@eecs.umich.edu * 67087Snate@binkert.org * The license below extends only to copyright in the software and shall 77087Snate@binkert.org * not be construed as granting a license to any other intellectual 87087Snate@binkert.org * property including but not limited to intellectual property relating 97087Snate@binkert.org * to a hardware implementation of the functionality of the software 107087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 117087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 127087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 137087Snate@binkert.org * modified or unmodified, in source code or in binary form. 144159Sgblack@eecs.umich.edu * 157087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 167087Snate@binkert.org * modification, are permitted provided that the following conditions are 177087Snate@binkert.org * met: redistributions of source code must retain the above copyright 187087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 197087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 207087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 217087Snate@binkert.org * documentation and/or other materials provided with the distribution; 227087Snate@binkert.org * neither the name of the copyright holders nor the names of its 234159Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 247087Snate@binkert.org * this software without specific prior written permission. 254159Sgblack@eecs.umich.edu * 264159Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 274159Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 284159Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 294159Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 304159Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 314159Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 324159Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 334159Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 344159Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 354159Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 364159Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 374159Sgblack@eecs.umich.edu * 384159Sgblack@eecs.umich.edu * Authors: Gabe Black 394159Sgblack@eecs.umich.edu */ 404159Sgblack@eecs.umich.edu 414159Sgblack@eecs.umich.edu#ifndef __ARCH_X86_PAGETABLE_HH__ 424159Sgblack@eecs.umich.edu#define __ARCH_X86_PAGETABLE_HH__ 434159Sgblack@eecs.umich.edu 445124Sgblack@eecs.umich.edu#include <iostream> 455124Sgblack@eecs.umich.edu#include <string> 4610299Salexandru.dutu@amd.com#include <vector> 475124Sgblack@eecs.umich.edu 485237Sgblack@eecs.umich.edu#include "base/bitunion.hh" 494159Sgblack@eecs.umich.edu#include "base/misc.hh" 506216Snate@binkert.org#include "base/types.hh" 518953Sgblack@eecs.umich.edu#include "base/trie.hh" 5210299Salexandru.dutu@amd.com#include "cpu/thread_context.hh" 5310299Salexandru.dutu@amd.com#include "arch/x86/system.hh" 5410299Salexandru.dutu@amd.com#include "debug/MMU.hh" 554159Sgblack@eecs.umich.edu 565124Sgblack@eecs.umich.educlass Checkpoint; 575124Sgblack@eecs.umich.edu 584159Sgblack@eecs.umich.edunamespace X86ISA 594159Sgblack@eecs.umich.edu{ 608953Sgblack@eecs.umich.edu struct TlbEntry; 618953Sgblack@eecs.umich.edu} 628953Sgblack@eecs.umich.edu 638953Sgblack@eecs.umich.edutypedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie; 648953Sgblack@eecs.umich.edu 658953Sgblack@eecs.umich.edunamespace X86ISA 668953Sgblack@eecs.umich.edu{ 675237Sgblack@eecs.umich.edu BitUnion64(VAddr) 685237Sgblack@eecs.umich.edu Bitfield<20, 12> longl1; 695237Sgblack@eecs.umich.edu Bitfield<29, 21> longl2; 705237Sgblack@eecs.umich.edu Bitfield<38, 30> longl3; 715237Sgblack@eecs.umich.edu Bitfield<47, 39> longl4; 725237Sgblack@eecs.umich.edu 735237Sgblack@eecs.umich.edu Bitfield<20, 12> pael1; 745237Sgblack@eecs.umich.edu Bitfield<29, 21> pael2; 755237Sgblack@eecs.umich.edu Bitfield<31, 30> pael3; 765237Sgblack@eecs.umich.edu 775237Sgblack@eecs.umich.edu Bitfield<21, 12> norml1; 785237Sgblack@eecs.umich.edu Bitfield<31, 22> norml2; 795237Sgblack@eecs.umich.edu EndBitUnion(VAddr) 804159Sgblack@eecs.umich.edu 8110299Salexandru.dutu@amd.com // Unfortunately, the placement of the base field in a page table entry is 8210299Salexandru.dutu@amd.com // very erratic and would make a mess here. It might be moved here at some 8310299Salexandru.dutu@amd.com // point in the future. 8410299Salexandru.dutu@amd.com BitUnion64(PageTableEntry) 8510299Salexandru.dutu@amd.com Bitfield<63> nx; 8610299Salexandru.dutu@amd.com Bitfield<51, 12> base; 8710299Salexandru.dutu@amd.com Bitfield<11, 9> avl; 8810299Salexandru.dutu@amd.com Bitfield<8> g; 8910299Salexandru.dutu@amd.com Bitfield<7> ps; 9010299Salexandru.dutu@amd.com Bitfield<6> d; 9110299Salexandru.dutu@amd.com Bitfield<5> a; 9210299Salexandru.dutu@amd.com Bitfield<4> pcd; 9310299Salexandru.dutu@amd.com Bitfield<3> pwt; 9410299Salexandru.dutu@amd.com Bitfield<2> u; 9510299Salexandru.dutu@amd.com Bitfield<1> w; 9610299Salexandru.dutu@amd.com Bitfield<0> p; 9710299Salexandru.dutu@amd.com EndBitUnion(PageTableEntry) 9810299Salexandru.dutu@amd.com 9910299Salexandru.dutu@amd.com 10010905Sandreas.sandberg@arm.com struct TlbEntry : public Serializable 1014159Sgblack@eecs.umich.edu { 1025124Sgblack@eecs.umich.edu // The base of the physical page. 1035184Sgblack@eecs.umich.edu Addr paddr; 1045184Sgblack@eecs.umich.edu 1055184Sgblack@eecs.umich.edu // The beginning of the virtual page this entry maps. 1065184Sgblack@eecs.umich.edu Addr vaddr; 1078953Sgblack@eecs.umich.edu // The size of the page this represents, in address bits. 1088953Sgblack@eecs.umich.edu unsigned logBytes; 1095184Sgblack@eecs.umich.edu 1105124Sgblack@eecs.umich.edu // Read permission is always available, assuming it isn't blocked by 1115124Sgblack@eecs.umich.edu // other mechanisms. 1125184Sgblack@eecs.umich.edu bool writable; 1135124Sgblack@eecs.umich.edu // Whether this page is accesible without being in supervisor mode. 1145124Sgblack@eecs.umich.edu bool user; 1155124Sgblack@eecs.umich.edu // Whether to use write through or write back. M5 ignores this and 1165124Sgblack@eecs.umich.edu // lets the caches handle the writeback policy. 1175124Sgblack@eecs.umich.edu //bool pwt; 1185124Sgblack@eecs.umich.edu // Whether the page is cacheable or not. 1195124Sgblack@eecs.umich.edu bool uncacheable; 1205124Sgblack@eecs.umich.edu // Whether or not to kick this page out on a write to CR3. 1215124Sgblack@eecs.umich.edu bool global; 1225124Sgblack@eecs.umich.edu // A bit used to form an index into the PAT table. 1235124Sgblack@eecs.umich.edu bool patBit; 1245124Sgblack@eecs.umich.edu // Whether or not memory on this page can be executed. 1255124Sgblack@eecs.umich.edu bool noExec; 1268953Sgblack@eecs.umich.edu // A sequence number to keep track of LRU. 1278953Sgblack@eecs.umich.edu uint64_t lruSeq; 1288953Sgblack@eecs.umich.edu 1298953Sgblack@eecs.umich.edu TlbEntryTrie::Handle trieHandle; 1305124Sgblack@eecs.umich.edu 13110558Salexandru.dutu@amd.com TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, 13210558Salexandru.dutu@amd.com bool uncacheable, bool read_only); 13310905Sandreas.sandberg@arm.com TlbEntry(); 1345124Sgblack@eecs.umich.edu 1355877Shsul@eecs.umich.edu void 1365877Shsul@eecs.umich.edu updateVaddr(Addr new_vaddr) 1375877Shsul@eecs.umich.edu { 1385877Shsul@eecs.umich.edu vaddr = new_vaddr; 1395877Shsul@eecs.umich.edu } 1405877Shsul@eecs.umich.edu 1415184Sgblack@eecs.umich.edu Addr pageStart() 1425184Sgblack@eecs.umich.edu { 1435184Sgblack@eecs.umich.edu return paddr; 1445184Sgblack@eecs.umich.edu } 1455124Sgblack@eecs.umich.edu 1469115SBrad.Beckmann@amd.com // Return the page size in bytes 1479115SBrad.Beckmann@amd.com int size() 1489115SBrad.Beckmann@amd.com { 1499115SBrad.Beckmann@amd.com return (1 << logBytes); 1509115SBrad.Beckmann@amd.com } 1519115SBrad.Beckmann@amd.com 15211168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 15311168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1544159Sgblack@eecs.umich.edu }; 15510299Salexandru.dutu@amd.com 15610299Salexandru.dutu@amd.com /** The size of each level of the page table expressed in base 2 15710299Salexandru.dutu@amd.com * logarithmic values 15810299Salexandru.dutu@amd.com */ 15910299Salexandru.dutu@amd.com const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9}; 16010299Salexandru.dutu@amd.com 16110558Salexandru.dutu@amd.com /* x86 specific PTE flags */ 16210299Salexandru.dutu@amd.com enum PTEField{ 16310558Salexandru.dutu@amd.com PTE_NotPresent = 1, 16410558Salexandru.dutu@amd.com PTE_Supervisor = 2, 16510558Salexandru.dutu@amd.com PTE_ReadOnly = 4, 16610558Salexandru.dutu@amd.com PTE_Uncacheable = 8, 16710299Salexandru.dutu@amd.com }; 16810299Salexandru.dutu@amd.com 16910299Salexandru.dutu@amd.com /** Page table operations specific to x86 ISA. 17010299Salexandru.dutu@amd.com * Indended to be used as parameter of MultiLevelPageTable. 17110299Salexandru.dutu@amd.com */ 17210299Salexandru.dutu@amd.com class PageTableOps 17310299Salexandru.dutu@amd.com { 17410299Salexandru.dutu@amd.com public: 17510558Salexandru.dutu@amd.com void setPTEFields(PageTableEntry& PTE, uint64_t flags = 0) 17610299Salexandru.dutu@amd.com { 17710558Salexandru.dutu@amd.com PTE.p = flags & PTE_NotPresent ? 0 : 1; 17810558Salexandru.dutu@amd.com PTE.pcd = flags & PTE_Uncacheable ? 1 : 0; 17910558Salexandru.dutu@amd.com PTE.w = flags & PTE_ReadOnly ? 0 : 1; 18010558Salexandru.dutu@amd.com PTE.u = flags & PTE_Supervisor ? 0 : 1; 18110299Salexandru.dutu@amd.com } 18210299Salexandru.dutu@amd.com 18310299Salexandru.dutu@amd.com /** returns the physical memory address of the page table */ 18410299Salexandru.dutu@amd.com Addr getBasePtr(ThreadContext* tc) 18510299Salexandru.dutu@amd.com { 18610299Salexandru.dutu@amd.com CR3 cr3 = pageTablePhysAddr; 18710299Salexandru.dutu@amd.com DPRINTF(MMU, "CR3: %d\n", cr3); 18810299Salexandru.dutu@amd.com return cr3.longPdtb; 18910299Salexandru.dutu@amd.com } 19010299Salexandru.dutu@amd.com 19110299Salexandru.dutu@amd.com /** returns the page number out of a page table entry */ 19210299Salexandru.dutu@amd.com Addr getPnum(PageTableEntry PTE) 19310299Salexandru.dutu@amd.com { 19410299Salexandru.dutu@amd.com return PTE.base; 19510299Salexandru.dutu@amd.com } 19610299Salexandru.dutu@amd.com 19710558Salexandru.dutu@amd.com bool isUncacheable(const PageTableEntry PTE) 19810558Salexandru.dutu@amd.com { 19910558Salexandru.dutu@amd.com return PTE.pcd; 20010558Salexandru.dutu@amd.com } 20110558Salexandru.dutu@amd.com 20210558Salexandru.dutu@amd.com bool isReadOnly(PageTableEntry PTE) 20310558Salexandru.dutu@amd.com { 20410558Salexandru.dutu@amd.com return !PTE.w; 20510558Salexandru.dutu@amd.com } 20610558Salexandru.dutu@amd.com 20710299Salexandru.dutu@amd.com /** sets the page number in a page table entry */ 20810299Salexandru.dutu@amd.com void setPnum(PageTableEntry& PTE, Addr paddr) 20910299Salexandru.dutu@amd.com { 21010299Salexandru.dutu@amd.com PTE.base = paddr; 21110299Salexandru.dutu@amd.com } 21210299Salexandru.dutu@amd.com 21310299Salexandru.dutu@amd.com /** returns the offsets to index in every level of a page 21410299Salexandru.dutu@amd.com * table, contained in a virtual address 21510299Salexandru.dutu@amd.com */ 21610299Salexandru.dutu@amd.com std::vector<uint64_t> getOffsets(Addr vaddr) 21710299Salexandru.dutu@amd.com { 21810299Salexandru.dutu@amd.com X86ISA::VAddr addr(vaddr); 21910299Salexandru.dutu@amd.com return {addr.longl1, addr.longl2, addr.longl3, addr.longl4}; 22010299Salexandru.dutu@amd.com } 22110299Salexandru.dutu@amd.com }; 22210299Salexandru.dutu@amd.com 2234159Sgblack@eecs.umich.edu} 2244159Sgblack@eecs.umich.edu 2254159Sgblack@eecs.umich.edu#endif 226