nativetrace.cc revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2007-2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/isa_traits.hh"
32#include "arch/x86/nativetrace.hh"
33#include "arch/x86/regs/float.hh"
34#include "arch/x86/regs/int.hh"
35#include "cpu/thread_context.hh"
36#include "params/X86NativeTrace.hh"
37#include "sim/byteswap.hh"
38
39namespace Trace {
40
41void
42X86NativeTrace::ThreadState::update(NativeTrace *parent)
43{
44    parent->read(this, sizeof(*this));
45    rax = X86ISA::gtoh(rax);
46    rcx = X86ISA::gtoh(rcx);
47    rdx = X86ISA::gtoh(rdx);
48    rbx = X86ISA::gtoh(rbx);
49    rsp = X86ISA::gtoh(rsp);
50    rbp = X86ISA::gtoh(rbp);
51    rsi = X86ISA::gtoh(rsi);
52    rdi = X86ISA::gtoh(rdi);
53    r8 = X86ISA::gtoh(r8);
54    r9 = X86ISA::gtoh(r9);
55    r10 = X86ISA::gtoh(r10);
56    r11 = X86ISA::gtoh(r11);
57    r12 = X86ISA::gtoh(r12);
58    r13 = X86ISA::gtoh(r13);
59    r14 = X86ISA::gtoh(r14);
60    r15 = X86ISA::gtoh(r15);
61    rip = X86ISA::gtoh(rip);
62    //This should be expanded if x87 registers are considered
63    for (int i = 0; i < 8; i++)
64        mmx[i] = X86ISA::gtoh(mmx[i]);
65    for (int i = 0; i < 32; i++)
66        xmm[i] = X86ISA::gtoh(xmm[i]);
67}
68
69void
70X86NativeTrace::ThreadState::update(ThreadContext *tc)
71{
72    rax = tc->readIntReg(X86ISA::INTREG_RAX);
73    rcx = tc->readIntReg(X86ISA::INTREG_RCX);
74    rdx = tc->readIntReg(X86ISA::INTREG_RDX);
75    rbx = tc->readIntReg(X86ISA::INTREG_RBX);
76    rsp = tc->readIntReg(X86ISA::INTREG_RSP);
77    rbp = tc->readIntReg(X86ISA::INTREG_RBP);
78    rsi = tc->readIntReg(X86ISA::INTREG_RSI);
79    rdi = tc->readIntReg(X86ISA::INTREG_RDI);
80    r8 = tc->readIntReg(X86ISA::INTREG_R8);
81    r9 = tc->readIntReg(X86ISA::INTREG_R9);
82    r10 = tc->readIntReg(X86ISA::INTREG_R10);
83    r11 = tc->readIntReg(X86ISA::INTREG_R11);
84    r12 = tc->readIntReg(X86ISA::INTREG_R12);
85    r13 = tc->readIntReg(X86ISA::INTREG_R13);
86    r14 = tc->readIntReg(X86ISA::INTREG_R14);
87    r15 = tc->readIntReg(X86ISA::INTREG_R15);
88    rip = tc->pcState().pc();
89    //This should be expanded if x87 registers are considered
90    for (int i = 0; i < 8; i++)
91        mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
92    for (int i = 0; i < 32; i++)
93        xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
94}
95
96
97X86NativeTrace::X86NativeTrace(const Params *p)
98    : NativeTrace(p)
99{
100    checkRcx = true;
101    checkR11 = true;
102}
103
104bool
105X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
106{
107    if(!checkRcx)
108        checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
109    if(checkRcx)
110        return checkReg(name, mVal, nVal);
111    return true;
112}
113
114bool
115X86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
116{
117    if(!checkR11)
118        checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
119    if(checkR11)
120        return checkReg(name, mVal, nVal);
121    return true;
122}
123
124bool
125X86NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
126{
127    if (mXmmBuf[num * 2]     != nXmmBuf[num * 2] ||
128        mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
129        DPRINTF(ExecRegDelta,
130                "Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
131                num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
132                     mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
133        return false;
134    }
135    return true;
136}
137
138void
139X86NativeTrace::check(NativeTraceRecord *record)
140{
141    nState.update(this);
142    mState.update(record->getThread());
143
144    if(record->getStaticInst()->isSyscall())
145    {
146        checkRcx = false;
147        checkR11 = false;
148        oldRcxVal = mState.rcx;
149        oldRealRcxVal = nState.rcx;
150        oldR11Val = mState.r11;
151        oldRealR11Val = nState.r11;
152    }
153
154    checkReg("rax", mState.rax, nState.rax);
155    checkRcxReg("rcx", mState.rcx, nState.rcx);
156    checkReg("rdx", mState.rdx, nState.rdx);
157    checkReg("rbx", mState.rbx, nState.rbx);
158    checkReg("rsp", mState.rsp, nState.rsp);
159    checkReg("rbp", mState.rbp, nState.rbp);
160    checkReg("rsi", mState.rsi, nState.rsi);
161    checkReg("rdi", mState.rdi, nState.rdi);
162    checkReg("r8",  mState.r8,  nState.r8);
163    checkReg("r9",  mState.r9,  nState.r9);
164    checkReg("r10", mState.r10, nState.r10);
165    checkR11Reg("r11", mState.r11, nState.r11);
166    checkReg("r12", mState.r12, nState.r12);
167    checkReg("r13", mState.r13, nState.r13);
168    checkReg("r14", mState.r14, nState.r14);
169    checkReg("r15", mState.r15, nState.r15);
170    checkReg("rip", mState.rip, nState.rip);
171    checkXMM(0, mState.xmm, nState.xmm);
172    checkXMM(1, mState.xmm, nState.xmm);
173    checkXMM(2, mState.xmm, nState.xmm);
174    checkXMM(3, mState.xmm, nState.xmm);
175    checkXMM(4, mState.xmm, nState.xmm);
176    checkXMM(5, mState.xmm, nState.xmm);
177    checkXMM(6, mState.xmm, nState.xmm);
178    checkXMM(7, mState.xmm, nState.xmm);
179    checkXMM(8, mState.xmm, nState.xmm);
180    checkXMM(9, mState.xmm, nState.xmm);
181    checkXMM(10, mState.xmm, nState.xmm);
182    checkXMM(11, mState.xmm, nState.xmm);
183    checkXMM(12, mState.xmm, nState.xmm);
184    checkXMM(13, mState.xmm, nState.xmm);
185    checkXMM(14, mState.xmm, nState.xmm);
186    checkXMM(15, mState.xmm, nState.xmm);
187}
188
189} /* namespace Trace */
190
191////////////////////////////////////////////////////////////////////////
192//
193//  ExeTracer Simulation Object
194//
195Trace::X86NativeTrace *
196X86NativeTraceParams::create()
197{
198    return new Trace::X86NativeTrace(this);
199};
200