nativetrace.cc revision 13611:c8b7847b4171 
1/*
2 * Copyright (c) 2007-2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/nativetrace.hh"
32
33#include "arch/x86/isa_traits.hh"
34#include "arch/x86/regs/float.hh"
35#include "arch/x86/regs/int.hh"
36#include "cpu/thread_context.hh"
37#include "debug/ExecRegDelta.hh"
38#include "params/X86NativeTrace.hh"
39#include "sim/byteswap.hh"
40
41namespace Trace {
42
43void
44X86NativeTrace::ThreadState::update(NativeTrace *parent)
45{
46    parent->read(this, sizeof(*this));
47    rax = X86ISA::gtoh(rax);
48    rcx = X86ISA::gtoh(rcx);
49    rdx = X86ISA::gtoh(rdx);
50    rbx = X86ISA::gtoh(rbx);
51    rsp = X86ISA::gtoh(rsp);
52    rbp = X86ISA::gtoh(rbp);
53    rsi = X86ISA::gtoh(rsi);
54    rdi = X86ISA::gtoh(rdi);
55    r8 = X86ISA::gtoh(r8);
56    r9 = X86ISA::gtoh(r9);
57    r10 = X86ISA::gtoh(r10);
58    r11 = X86ISA::gtoh(r11);
59    r12 = X86ISA::gtoh(r12);
60    r13 = X86ISA::gtoh(r13);
61    r14 = X86ISA::gtoh(r14);
62    r15 = X86ISA::gtoh(r15);
63    rip = X86ISA::gtoh(rip);
64    //This should be expanded if x87 registers are considered
65    for (int i = 0; i < 8; i++)
66        mmx[i] = X86ISA::gtoh(mmx[i]);
67    for (int i = 0; i < 32; i++)
68        xmm[i] = X86ISA::gtoh(xmm[i]);
69}
70
71void
72X86NativeTrace::ThreadState::update(ThreadContext *tc)
73{
74    rax = tc->readIntReg(X86ISA::INTREG_RAX);
75    rcx = tc->readIntReg(X86ISA::INTREG_RCX);
76    rdx = tc->readIntReg(X86ISA::INTREG_RDX);
77    rbx = tc->readIntReg(X86ISA::INTREG_RBX);
78    rsp = tc->readIntReg(X86ISA::INTREG_RSP);
79    rbp = tc->readIntReg(X86ISA::INTREG_RBP);
80    rsi = tc->readIntReg(X86ISA::INTREG_RSI);
81    rdi = tc->readIntReg(X86ISA::INTREG_RDI);
82    r8 = tc->readIntReg(X86ISA::INTREG_R8);
83    r9 = tc->readIntReg(X86ISA::INTREG_R9);
84    r10 = tc->readIntReg(X86ISA::INTREG_R10);
85    r11 = tc->readIntReg(X86ISA::INTREG_R11);
86    r12 = tc->readIntReg(X86ISA::INTREG_R12);
87    r13 = tc->readIntReg(X86ISA::INTREG_R13);
88    r14 = tc->readIntReg(X86ISA::INTREG_R14);
89    r15 = tc->readIntReg(X86ISA::INTREG_R15);
90    rip = tc->pcState().npc();
91    //This should be expanded if x87 registers are considered
92    for (int i = 0; i < 8; i++)
93        mmx[i] = tc->readFloatReg(X86ISA::FLOATREG_MMX(i));
94    for (int i = 0; i < 32; i++)
95        xmm[i] = tc->readFloatReg(X86ISA::FLOATREG_XMM_BASE + i);
96}
97
98
99X86NativeTrace::X86NativeTrace(const Params *p)
100    : NativeTrace(p)
101{
102    checkRcx = true;
103    checkR11 = true;
104}
105
106bool
107X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
108{
109    if (!checkRcx)
110        checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
111    if (checkRcx)
112        return checkReg(name, mVal, nVal);
113    return true;
114}
115
116bool
117X86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
118{
119    if (!checkR11)
120        checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
121    if (checkR11)
122        return checkReg(name, mVal, nVal);
123    return true;
124}
125
126bool
127X86NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
128{
129    if (mXmmBuf[num * 2]     != nXmmBuf[num * 2] ||
130        mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
131        DPRINTF(ExecRegDelta,
132                "Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
133                num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
134                     mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
135        return false;
136    }
137    return true;
138}
139
140void
141X86NativeTrace::check(NativeTraceRecord *record)
142{
143    nState.update(this);
144    mState.update(record->getThread());
145
146    if (record->getStaticInst()->isSyscall())
147    {
148        checkRcx = false;
149        checkR11 = false;
150        oldRcxVal = mState.rcx;
151        oldRealRcxVal = nState.rcx;
152        oldR11Val = mState.r11;
153        oldRealR11Val = nState.r11;
154    }
155
156    checkReg("rax", mState.rax, nState.rax);
157    checkRcxReg("rcx", mState.rcx, nState.rcx);
158    checkReg("rdx", mState.rdx, nState.rdx);
159    checkReg("rbx", mState.rbx, nState.rbx);
160    checkReg("rsp", mState.rsp, nState.rsp);
161    checkReg("rbp", mState.rbp, nState.rbp);
162    checkReg("rsi", mState.rsi, nState.rsi);
163    checkReg("rdi", mState.rdi, nState.rdi);
164    checkReg("r8",  mState.r8,  nState.r8);
165    checkReg("r9",  mState.r9,  nState.r9);
166    checkReg("r10", mState.r10, nState.r10);
167    checkR11Reg("r11", mState.r11, nState.r11);
168    checkReg("r12", mState.r12, nState.r12);
169    checkReg("r13", mState.r13, nState.r13);
170    checkReg("r14", mState.r14, nState.r14);
171    checkReg("r15", mState.r15, nState.r15);
172    checkReg("rip", mState.rip, nState.rip);
173    checkXMM(0, mState.xmm, nState.xmm);
174    checkXMM(1, mState.xmm, nState.xmm);
175    checkXMM(2, mState.xmm, nState.xmm);
176    checkXMM(3, mState.xmm, nState.xmm);
177    checkXMM(4, mState.xmm, nState.xmm);
178    checkXMM(5, mState.xmm, nState.xmm);
179    checkXMM(6, mState.xmm, nState.xmm);
180    checkXMM(7, mState.xmm, nState.xmm);
181    checkXMM(8, mState.xmm, nState.xmm);
182    checkXMM(9, mState.xmm, nState.xmm);
183    checkXMM(10, mState.xmm, nState.xmm);
184    checkXMM(11, mState.xmm, nState.xmm);
185    checkXMM(12, mState.xmm, nState.xmm);
186    checkXMM(13, mState.xmm, nState.xmm);
187    checkXMM(14, mState.xmm, nState.xmm);
188    checkXMM(15, mState.xmm, nState.xmm);
189}
190
191} // namespace Trace
192
193////////////////////////////////////////////////////////////////////////
194//
195//  ExeTracer Simulation Object
196//
197Trace::X86NativeTrace *
198X86NativeTraceParams::create()
199{
200    return new Trace::X86NativeTrace(this);
201}
202