isa_traits.hh revision 5121 
1/*
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42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_ISATRAITS_HH__
59#define __ARCH_X86_ISATRAITS_HH__
60
61#include "arch/x86/intregs.hh"
62#include "arch/x86/types.hh"
63#include "arch/x86/x86_traits.hh"
64#include "sim/host.hh"
65
66class StaticInstPtr;
67
68namespace LittleEndianGuest {}
69
70namespace X86ISA
71{
72    //This makes sure the little endian version of certain functions
73    //are used.
74    using namespace LittleEndianGuest;
75
76    // X86 does not have a delay slot
77#define ISA_HAS_DELAY_SLOT 0
78
79    // X86 NOP (XCHG rAX, rAX)
80    //XXX This needs to be set to an intermediate instruction struct
81    //which encodes this instruction
82
83    // These enumerate all the registers for dependence tracking.
84    enum DependenceTags {
85        //There are 16 microcode registers at the moment. This is an
86        //unusually large constant to make sure there isn't overflow.
87        FP_Base_DepTag = 128,
88        Ctrl_Base_DepTag =
89            FP_Base_DepTag +
90            //mmx/x87 registers
91            8 +
92            //xmm registers
93            16 * 2 +
94            //The microcode fp registers
95            8 +
96            //The indices that are mapped over the fp stack
97            8
98    };
99
100    // semantically meaningful register indices
101    //There is no such register in X86
102    const int ZeroReg = NUM_INTREGS;
103    const int StackPointerReg = INTREG_RSP;
104    //X86 doesn't seem to have a link register
105    const int ReturnAddressReg = 0;
106    const int ReturnValueReg = INTREG_RAX;
107    const int FramePointerReg = INTREG_RBP;
108    const int ArgumentReg[] = {
109        INTREG_RDI,
110        INTREG_RSI,
111        INTREG_RDX,
112        //This argument register is r10 for syscalls and rcx for C.
113        INTREG_R10W,
114        //INTREG_RCX,
115        INTREG_R8W,
116        INTREG_R9W
117    };
118    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
119
120    // Some OS syscalls use a second register (rdx) to return a second
121    // value
122    const int SyscallPseudoReturnReg = INTREG_RDX;
123
124    //XXX These numbers are bogus
125    const int MaxInstSrcRegs = 10;
126    const int MaxInstDestRegs = 10;
127
128    //4k. This value is not constant on x86.
129    const int LogVMPageSize = 12;
130    const int VMPageSize = (1 << LogVMPageSize);
131
132    const int PageShift = 13;
133    const int PageBytes = 1ULL << PageShift;
134
135    const int BranchPredAddrShiftAmt = 0;
136
137    StaticInstPtr decodeInst(ExtMachInst);
138
139    const Addr LoadAddrMask = ULL(0xffffffffff);
140};
141
142#endif // __ARCH_X86_ISATRAITS_HH__
143