isa_traits.hh revision 7087
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. 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IN NO EVENT SHALL THE COPYRIGHT 294120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364120Sgblack@eecs.umich.edu * 374120Sgblack@eecs.umich.edu * Authors: Gabe Black 384120Sgblack@eecs.umich.edu */ 394120Sgblack@eecs.umich.edu 404120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_ISATRAITS_HH__ 414120Sgblack@eecs.umich.edu#define __ARCH_X86_ISATRAITS_HH__ 424120Sgblack@eecs.umich.edu 434141Sgblack@eecs.umich.edu#include "arch/x86/types.hh" 444136Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 456214Snate@binkert.org#include "base/types.hh" 464136Sgblack@eecs.umich.edu 474141Sgblack@eecs.umich.educlass StaticInstPtr; 484141Sgblack@eecs.umich.edu 494121Sgblack@eecs.umich.edunamespace LittleEndianGuest {} 504120Sgblack@eecs.umich.edu 514120Sgblack@eecs.umich.edunamespace X86ISA 524120Sgblack@eecs.umich.edu{ 534121Sgblack@eecs.umich.edu //This makes sure the little endian version of certain functions 544121Sgblack@eecs.umich.edu //are used. 554121Sgblack@eecs.umich.edu using namespace LittleEndianGuest; 564121Sgblack@eecs.umich.edu 574121Sgblack@eecs.umich.edu // X86 does not have a delay slot 584121Sgblack@eecs.umich.edu#define ISA_HAS_DELAY_SLOT 0 594121Sgblack@eecs.umich.edu 604121Sgblack@eecs.umich.edu // X86 NOP (XCHG rAX, rAX) 614121Sgblack@eecs.umich.edu //XXX This needs to be set to an intermediate instruction struct 624121Sgblack@eecs.umich.edu //which encodes this instruction 634121Sgblack@eecs.umich.edu 644121Sgblack@eecs.umich.edu //4k. This value is not constant on x86. 654141Sgblack@eecs.umich.edu const int LogVMPageSize = 12; 664141Sgblack@eecs.umich.edu const int VMPageSize = (1 << LogVMPageSize); 674141Sgblack@eecs.umich.edu 685127Sgblack@eecs.umich.edu const int PageShift = 12; 694141Sgblack@eecs.umich.edu const int PageBytes = 1ULL << PageShift; 704121Sgblack@eecs.umich.edu 714121Sgblack@eecs.umich.edu const int BranchPredAddrShiftAmt = 0; 724141Sgblack@eecs.umich.edu 734141Sgblack@eecs.umich.edu StaticInstPtr decodeInst(ExtMachInst); 745086Sgblack@eecs.umich.edu 755152Sgblack@eecs.umich.edu const Addr LoadAddrMask = ULL(-1); 766974Stjones1@inf.ed.ac.uk 776974Stjones1@inf.ed.ac.uk // Memory accesses can be unaligned 786974Stjones1@inf.ed.ac.uk const bool HasUnalignedMemAcc = true; 794120Sgblack@eecs.umich.edu}; 804120Sgblack@eecs.umich.edu 814120Sgblack@eecs.umich.edu#endif // __ARCH_X86_ISATRAITS_HH__ 82