isa_traits.hh revision 4587
12810SN/A/* 22810SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use of this software in source and binary forms, 62810SN/A * with or without modification, are permitted provided that the 72810SN/A * following conditions are met: 82810SN/A * 92810SN/A * The software must be used only for Non-Commercial Use which means any 102810SN/A * use which is NOT directed to receiving any direct monetary 112810SN/A * compensation for, or commercial advantage from such use. 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Redistributions 282810SN/A * in binary form must reproduce the above copyright notice, this list of 294458SN/A * conditions and the following disclaimer in the documentation and/or 304458SN/A * other materials provided with the distribution. Neither the name of 312810SN/A * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 322810SN/A * contributors may be used to endorse or promote products derived from 332810SN/A * this software without specific prior written permission. No right of 342810SN/A * sublicense is granted herewith. Derivatives of the software and 352810SN/A * output created using the software may be prepared, but only for 362810SN/A * Non-Commercial Uses. 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IN NO EVENT SHALL THE COPYRIGHT 472810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 482810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 496215Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 506978SLisa.Hsu@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 518232Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 528232Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535338Sstever@gmail.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 542810SN/A * 552810SN/A * Authors: Gabe Black 568229Snate@binkert.org */ 574626SN/A 585034SN/A#ifndef __ARCH_X86_ISATRAITS_HH__ 592811SN/A#define __ARCH_X86_ISATRAITS_HH__ 604626SN/A 612810SN/A#include "arch/x86/intregs.hh" 623194SN/A#include "arch/x86/types.hh" 632810SN/A#include "arch/x86/x86_traits.hh" 642810SN/A 652810SN/Aclass StaticInstPtr; 662810SN/A 672810SN/Anamespace LittleEndianGuest {} 684628SN/A 694628SN/Anamespace X86ISA 704628SN/A{ 714628SN/A //This makes sure the little endian version of certain functions 724628SN/A //are used. 734628SN/A using namespace LittleEndianGuest; 744628SN/A 754628SN/A // X86 does not have a delay slot 764628SN/A#define ISA_HAS_DELAY_SLOT 0 774628SN/A 784628SN/A // X86 NOP (XCHG rAX, rAX) 794628SN/A //XXX This needs to be set to an intermediate instruction struct 804628SN/A //which encodes this instruction 814628SN/A 824628SN/A // These enumerate all the registers for dependence tracking. 834628SN/A enum DependenceTags { 844628SN/A //There are 16 microcode registers at the moment 854628SN/A FP_Base_DepTag = 32, 864628SN/A Ctrl_Base_DepTag = 874628SN/A FP_Base_DepTag + 884628SN/A //mmx/x87 registers 894628SN/A 8 + 904628SN/A //xmm registers 914628SN/A 16 924628SN/A }; 934628SN/A 944628SN/A // semantically meaningful register indices 954628SN/A //There is no such register in X86 964628SN/A const int ZeroReg = NUM_INTREGS; 974628SN/A const int StackPointerReg = INTREG_RSP; 984628SN/A //X86 doesn't seem to have a link register 994626SN/A const int ReturnAddressReg = 0; 1002810SN/A const int ReturnValueReg = INTREG_RAX; 1012844SN/A const int FramePointerReg = INTREG_RBP; 1022810SN/A const int ArgumentReg0 = INTREG_RDI; 1032810SN/A const int ArgumentReg1 = INTREG_RSI; 1043738SN/A const int ArgumentReg2 = INTREG_RDX; 1054965SN/A const int ArgumentReg3 = INTREG_RCX; 1066122SSteve.Reinhardt@amd.com const int ArgumentReg4 = INTREG_R8W; 1074458SN/A const int ArgumentReg5 = INTREG_R9W; 1082810SN/A 1092810SN/A // Some OS syscalls use a second register (rdx) to return a second 1106227Snate@binkert.org // value 1112810SN/A const int SyscallPseudoReturnReg = INTREG_RDX; 1124458SN/A 1133013SN/A //XXX These numbers are bogus 1144666SN/A const int MaxInstSrcRegs = 10; 1154666SN/A const int MaxInstDestRegs = 10; 1164666SN/A 1175314SN/A //4k. This value is not constant on x86. 1185314SN/A const int LogVMPageSize = 12; 1192811SN/A const int VMPageSize = (1 << LogVMPageSize); 1204458SN/A 1214458SN/A const int PageShift = 13; 1222810SN/A const int PageBytes = 1ULL << PageShift; 1232810SN/A 1242810SN/A const int BranchPredAddrShiftAmt = 0; 1252810SN/A 1265314SN/A StaticInstPtr decodeInst(ExtMachInst); 1273606SN/A}; 1284458SN/A 1294458SN/A#endif // __ARCH_X86_ISATRAITS_HH__ 1302810SN/A