isa_traits.hh revision 4141
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554120Sgblack@eecs.umich.edu * Authors: Gabe Black
564120Sgblack@eecs.umich.edu */
574120Sgblack@eecs.umich.edu
584120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_ISATRAITS_HH__
594120Sgblack@eecs.umich.edu#define __ARCH_X86_ISATRAITS_HH__
604120Sgblack@eecs.umich.edu
614141Sgblack@eecs.umich.edu#include "arch/x86/types.hh"
624136Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh"
634136Sgblack@eecs.umich.edu
644141Sgblack@eecs.umich.educlass StaticInstPtr;
654141Sgblack@eecs.umich.edu
664121Sgblack@eecs.umich.edunamespace LittleEndianGuest {}
674120Sgblack@eecs.umich.edu
684120Sgblack@eecs.umich.edunamespace X86ISA
694120Sgblack@eecs.umich.edu{
704121Sgblack@eecs.umich.edu    //This makes sure the little endian version of certain functions
714121Sgblack@eecs.umich.edu    //are used.
724121Sgblack@eecs.umich.edu    using namespace LittleEndianGuest;
734121Sgblack@eecs.umich.edu
744121Sgblack@eecs.umich.edu    // X86 does not have a delay slot
754121Sgblack@eecs.umich.edu#define ISA_HAS_DELAY_SLOT 0
764121Sgblack@eecs.umich.edu
774121Sgblack@eecs.umich.edu    // X86 NOP (XCHG rAX, rAX)
784121Sgblack@eecs.umich.edu    //XXX This needs to be set to an intermediate instruction struct
794121Sgblack@eecs.umich.edu    //which encodes this instruction
804121Sgblack@eecs.umich.edu
814121Sgblack@eecs.umich.edu    // These enumerate all the registers for dependence tracking.
824121Sgblack@eecs.umich.edu    enum DependenceTags {
834121Sgblack@eecs.umich.edu        //The number of microcode registers needs to be added to this
844121Sgblack@eecs.umich.edu        FP_Base_DepTag = 16,
854121Sgblack@eecs.umich.edu        Ctrl_Base_DepTag =
864121Sgblack@eecs.umich.edu            FP_Base_DepTag +
874121Sgblack@eecs.umich.edu            //mmx/x87 registers
884121Sgblack@eecs.umich.edu            8 +
894121Sgblack@eecs.umich.edu            //xmm registers
904121Sgblack@eecs.umich.edu            16
914121Sgblack@eecs.umich.edu    };
924121Sgblack@eecs.umich.edu
934121Sgblack@eecs.umich.edu    // semantically meaningful register indices
944121Sgblack@eecs.umich.edu    //There is no such register in X86
954121Sgblack@eecs.umich.edu    const int ZeroReg = 0;
964121Sgblack@eecs.umich.edu    const int StackPointerReg = 4; //RSP
974121Sgblack@eecs.umich.edu    //X86 doesn't seem to have a link register
984121Sgblack@eecs.umich.edu    const int ReturnAddressReg = 0;
994121Sgblack@eecs.umich.edu    const int ReturnValueReg = 0; //RAX
1004121Sgblack@eecs.umich.edu    const int FramePointerReg = 5; //RBP
1014121Sgblack@eecs.umich.edu    const int ArgumentReg0 = 7; //RDI
1024121Sgblack@eecs.umich.edu    const int ArgumentReg1 = 6; //RSI
1034121Sgblack@eecs.umich.edu    const int ArgumentReg2 = 2; //RDX
1044121Sgblack@eecs.umich.edu    const int ArgumentReg3 = 1; //RCX
1054121Sgblack@eecs.umich.edu    const int ArgumentReg4 = 8; //R8W
1064121Sgblack@eecs.umich.edu    const int ArgumentReg5 = 9; //R9W
1074121Sgblack@eecs.umich.edu
1084121Sgblack@eecs.umich.edu    // Some OS syscalls use a second register (rdx) to return a second
1094121Sgblack@eecs.umich.edu    // value
1104121Sgblack@eecs.umich.edu    const int SyscallPseudoReturnReg = 2; //RDX
1114121Sgblack@eecs.umich.edu
1124121Sgblack@eecs.umich.edu    //XXX These numbers are bogus
1134121Sgblack@eecs.umich.edu    const int MaxInstSrcRegs = 10;
1144121Sgblack@eecs.umich.edu    const int MaxInstDestRegs = 10;
1154121Sgblack@eecs.umich.edu
1164121Sgblack@eecs.umich.edu    //4k. This value is not constant on x86.
1174141Sgblack@eecs.umich.edu    const int LogVMPageSize = 12;
1184141Sgblack@eecs.umich.edu    const int VMPageSize = (1 << LogVMPageSize);
1194141Sgblack@eecs.umich.edu
1204141Sgblack@eecs.umich.edu    const int PageShift = 13;
1214141Sgblack@eecs.umich.edu    const int PageBytes = 1ULL << PageShift;
1224121Sgblack@eecs.umich.edu
1234121Sgblack@eecs.umich.edu    const int BranchPredAddrShiftAmt = 0;
1244141Sgblack@eecs.umich.edu
1254141Sgblack@eecs.umich.edu    StaticInstPtr decodeInst(ExtMachInst);
1264120Sgblack@eecs.umich.edu};
1274120Sgblack@eecs.umich.edu
1284120Sgblack@eecs.umich.edu#endif // __ARCH_X86_ISATRAITS_HH__
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