isa_traits.hh revision 11800
14120Sgblack@eecs.umich.edu/*
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364120Sgblack@eecs.umich.edu *
374120Sgblack@eecs.umich.edu * Authors: Gabe Black
384120Sgblack@eecs.umich.edu */
394120Sgblack@eecs.umich.edu
404120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_ISATRAITS_HH__
414120Sgblack@eecs.umich.edu#define __ARCH_X86_ISATRAITS_HH__
424120Sgblack@eecs.umich.edu
434141Sgblack@eecs.umich.edu#include "arch/x86/types.hh"
444136Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh"
4511800Sbrandon.potter@amd.com#include "base/compiler.hh"
466214Snate@binkert.org#include "base/types.hh"
474141Sgblack@eecs.umich.edu
484121Sgblack@eecs.umich.edunamespace LittleEndianGuest {}
494120Sgblack@eecs.umich.edu
504120Sgblack@eecs.umich.edunamespace X86ISA
514120Sgblack@eecs.umich.edu{
524121Sgblack@eecs.umich.edu    //This makes sure the little endian version of certain functions
534121Sgblack@eecs.umich.edu    //are used.
544121Sgblack@eecs.umich.edu    using namespace LittleEndianGuest;
554121Sgblack@eecs.umich.edu
564121Sgblack@eecs.umich.edu    // X86 does not have a delay slot
574121Sgblack@eecs.umich.edu#define ISA_HAS_DELAY_SLOT 0
584121Sgblack@eecs.umich.edu
594121Sgblack@eecs.umich.edu    // X86 NOP (XCHG rAX, rAX)
604121Sgblack@eecs.umich.edu    //XXX This needs to be set to an intermediate instruction struct
614121Sgblack@eecs.umich.edu    //which encodes this instruction
624121Sgblack@eecs.umich.edu
6310318Sandreas.hansson@arm.com    const Addr PageShift = 12;
6410318Sandreas.hansson@arm.com    const Addr PageBytes = ULL(1) << PageShift;
654141Sgblack@eecs.umich.edu
666974Stjones1@inf.ed.ac.uk    // Memory accesses can be unaligned
676974Stjones1@inf.ed.ac.uk    const bool HasUnalignedMemAcc = true;
687623Sgblack@eecs.umich.edu
699329Sdam.sunwoo@arm.com    const bool CurThreadInfoImplemented = false;
709329Sdam.sunwoo@arm.com    const int CurThreadInfoReg = -1;
719329Sdam.sunwoo@arm.com
7210835Sandreas.hansson@arm.com    const ExtMachInst NoopMachInst M5_VAR_USED = {
739057SAli.Saidi@ARM.com        0x0,                            // No legacy prefixes.
749057SAli.Saidi@ARM.com        0x0,                            // No rex prefix.
7510924Snilay@cs.wisc.edu        0x0,                            // No two / three byte escape sequence
7610924Snilay@cs.wisc.edu        { OneByteOpcode, 0x90 },        // One opcode byte, 0x90.
779057SAli.Saidi@ARM.com        0x0, 0x0,                       // No modrm or sib.
789057SAli.Saidi@ARM.com        0, 0,                           // No immediate or displacement.
799057SAli.Saidi@ARM.com        8, 8, 8,                        // All sizes are 8.
809057SAli.Saidi@ARM.com        0,                              // Displacement size is 0.
819057SAli.Saidi@ARM.com        SixtyFourBitMode                // Behave as if we're in 64 bit
829057SAli.Saidi@ARM.com                                        // mode (this doesn't actually matter).
839057SAli.Saidi@ARM.com    };
848902Sandreas.hansson@arm.com}
854120Sgblack@eecs.umich.edu
864120Sgblack@eecs.umich.edu#endif // __ARCH_X86_ISATRAITS_HH__
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