outputblock.isa revision 4366 
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any
9// use which is NOT directed to receiving any direct monetary
10// compensation for, or commercial advantage from such use.  Illustrative
11// examples of non-commercial use are academic research, personal study,
12// teaching, education and corporate research & development.
13// Illustrative examples of commercial use are distributing products for
14// commercial advantage and providing services using the software for
15// commercial advantage.
16//
17// If you wish to use this software or functionality therein that may be
18// covered by patents for commercial use, please contact:
19//     Director of Intellectual Property Licensing
20//     Office of Strategy and Technology
21//     Hewlett-Packard Company
22//     1501 Page Mill Road
23//     Palo Alto, California  94304
24//
25// Redistributions of source code must retain the above copyright notice,
26// this list of conditions and the following disclaimer.  Redistributions
27// in binary form must reproduce the above copyright notice, this list of
28// conditions and the following disclaimer in the documentation and/or
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30// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
31// contributors may be used to endorse or promote products derived from
32// this software without specific prior written permission.  No right of
33// sublicense is granted herewith.  Derivatives of the software and
34// output created using the software may be prepared, but only for
35// Non-Commercial Uses.  Derivatives of the software may be shared with
36// others provided: (i) the others agree to abide by the list of
37// conditions herein which includes the Non-Commercial Use restrictions;
38// and (ii) such Derivatives of the software include the above copyright
39// notice to acknowledge the contribution from this software where
40// applicable, this list of conditions and the disclaimer below.
41//
42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53//
54// Authors: Gabe Black
55
56////////////////////////////////////////////////////////////////////
57//
58// Base class for sparc instructions, and some support functions
59//
60
61let {{
62    # This class will help make dealing with output a little less verbose
63    class OutputBlocks(object):
64        def __init__(self, header_output="",
65                           decoder_output="",
66                           decode_block="",
67                           exec_output=""):
68            self.header_output = header_output
69            self.decoder_output = decoder_output
70            self.decode_block = decode_block
71            self.exec_output = exec_output
72
73        def append(self, blocks):
74            if isinstance(blocks, list) or isinstance(blocks, tuple):
75                assert(len(blocks) == 4)
76                self.header_output += blocks[0]
77                self.decoder_output += blocks[1]
78                self.decode_block += blocks[2]
79                self.exec_output += blocks[3]
80            else:
81                self.header_output += blocks.header_output
82                self.decoder_output += blocks.decoder_output
83                self.decode_block += blocks.decode_block
84                self.exec_output += blocks.exec_output
85
86        def makeList(self):
87            return (self.header_output,
88                    self.decoder_output,
89                    self.decode_block,
90                    self.exec_output)
91}};
92
93output header {{
94
95        /**
96         * Base class for all X86 static instructions.
97         */
98        class X86StaticInst : public StaticInst
99        {
100          protected:
101            // Constructor.
102            X86StaticInst(const char *mnem,
103                 ExtMachInst _machInst, OpClass __opClass)
104                    : StaticInst(mnem, _machInst, __opClass)
105                {
106                }
107
108            std::string generateDisassembly(Addr pc,
109                const SymbolTable *symtab) const;
110
111            void printReg(std::ostream &os, int reg) const;
112            void printSrcReg(std::ostream &os, int reg) const;
113            void printDestReg(std::ostream &os, int reg) const;
114
115            inline uint64_t merge(uint64_t into, uint64_t val, int size) const
116            {
117                //FIXME This needs to be significantly more sophisticated
118                return val;
119            }
120
121        };
122}};
123
124output decoder {{
125
126        inline void printMnemonic(std::ostream &os, const char * mnemonic)
127        {
128            ccprintf(os, "\t%s   ", mnemonic);
129        }
130
131        void
132        X86StaticInst::printSrcReg(std::ostream &os, int reg) const
133        {
134            if(_numSrcRegs > reg)
135                printReg(os, _srcRegIdx[reg]);
136        }
137
138        void
139        X86StaticInst::printDestReg(std::ostream &os, int reg) const
140        {
141            if(_numDestRegs > reg)
142                printReg(os, _destRegIdx[reg]);
143        }
144
145        void
146        X86StaticInst::printReg(std::ostream &os, int reg) const
147        {
148            if (reg < FP_Base_DepTag) {
149                //FIXME These should print differently depending on the
150                //mode etc, but for now this will get the point across
151                switch (reg) {
152                  case INTREG_RAX:
153                    ccprintf(os, "rax");
154                    break;
155                  case INTREG_RBX:
156                    ccprintf(os, "rbx");
157                    break;
158                  case INTREG_RCX:
159                    ccprintf(os, "rcx");
160                    break;
161                  case INTREG_RDX:
162                    ccprintf(os, "rdx");
163                    break;
164                  case INTREG_RSP:
165                    ccprintf(os, "rsp");
166                    break;
167                  case INTREG_RBP:
168                    ccprintf(os, "rbp");
169                    break;
170                  case INTREG_RSI:
171                    ccprintf(os, "rsi");
172                    break;
173                  case INTREG_RDI:
174                    ccprintf(os, "rdi");
175                    break;
176                  case INTREG_R8W:
177                    ccprintf(os, "r8");
178                    break;
179                  case INTREG_R9W:
180                    ccprintf(os, "r9");
181                    break;
182                  case INTREG_R10W:
183                    ccprintf(os, "r10");
184                    break;
185                  case INTREG_R11W:
186                    ccprintf(os, "r11");
187                    break;
188                  case INTREG_R12W:
189                    ccprintf(os, "r12");
190                    break;
191                  case INTREG_R13W:
192                    ccprintf(os, "r13");
193                    break;
194                  case INTREG_R14W:
195                    ccprintf(os, "r14");
196                    break;
197                  case INTREG_R15W:
198                    ccprintf(os, "r15");
199                    break;
200                }
201            } else if (reg < Ctrl_Base_DepTag) {
202                ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
203            } else {
204                switch (reg - Ctrl_Base_DepTag) {
205                  default:
206                    ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
207                }
208            }
209        }
210
211        std::string X86StaticInst::generateDisassembly(Addr pc,
212            const SymbolTable *symtab) const
213        {
214            std::stringstream ss;
215
216            printMnemonic(ss, mnemonic);
217
218            return ss.str();
219        }
220}};
221