specop.isa revision 7682:37c56be05af0 
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38//////////////////////////////////////////////////////////////////////////
39//
40// Fault Microop
41//
42//////////////////////////////////////////////////////////////////////////
43
44output header {{
45    class MicroFaultBase : public X86ISA::X86MicroopBase
46    {
47      protected:
48        Fault fault;
49        uint8_t cc;
50
51      public:
52        MicroFaultBase(ExtMachInst _machInst, const char * instMnem,
53                uint64_t setFlags, Fault _fault, uint8_t _cc);
54
55        std::string generateDisassembly(Addr pc,
56                const SymbolTable *symtab) const;
57    };
58
59    class MicroHalt : public X86ISA::X86MicroopBase
60    {
61      public:
62        MicroHalt(ExtMachInst _machInst, const char * instMnem,
63                uint64_t setFlags) :
64            X86MicroopBase(_machInst, "halt", instMnem,
65                           setFlags | (ULL(1) << StaticInst::IsNonSpeculative),
66                           No_OpClass)
67        {
68        }
69
70        %(BasicExecDeclare)s
71
72        std::string generateDisassembly(Addr pc,
73                const SymbolTable *symtab) const;
74    };
75}};
76
77def template MicroFaultDeclare {{
78    class %(class_name)s : public %(base_class)s
79    {
80      public:
81        %(class_name)s(ExtMachInst _machInst, const char * instMnem,
82                uint64_t setFlags, Fault _fault, uint8_t _cc);
83
84        %(BasicExecDeclare)s
85    };
86}};
87
88def template MicroFaultExecute {{
89        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
90                Trace::InstRecord *traceData) const
91        {
92            %(op_decl)s;
93            %(op_rd)s;
94            if (%(cond_test)s) {
95                //Return the fault we were constructed with
96                return fault;
97            } else {
98                return NoFault;
99            }
100        }
101}};
102
103output exec {{
104    Fault
105    MicroHalt::execute(%(CPU_exec_context)s *xc,
106            Trace::InstRecord * traceData) const
107    {
108        xc->tcBase()->suspend();
109        return NoFault;
110    }
111}};
112
113output decoder {{
114    inline MicroFaultBase::MicroFaultBase(
115            ExtMachInst machInst, const char * instMnem,
116            uint64_t setFlags, Fault _fault, uint8_t _cc) :
117        X86MicroopBase(machInst, "fault", instMnem, setFlags, No_OpClass),
118                fault(_fault), cc(_cc)
119    {
120    }
121}};
122
123def template MicroFaultConstructor {{
124    inline %(class_name)s::%(class_name)s(
125            ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
126            Fault _fault, uint8_t _cc) :
127        %(base_class)s(machInst, instMnem, setFlags, _fault, _cc)
128    {
129        %(constructor)s;
130    }
131}};
132
133output decoder {{
134    std::string MicroFaultBase::generateDisassembly(Addr pc,
135            const SymbolTable *symtab) const
136    {
137        std::stringstream response;
138
139        printMnemonic(response, instMnem, mnemonic);
140        if(fault)
141            response << fault->name();
142        else
143            response << "No Fault";
144
145        return response.str();
146    }
147
148    std::string MicroHalt::generateDisassembly(Addr pc,
149            const SymbolTable *symtab) const
150    {
151        std::stringstream response;
152
153        printMnemonic(response, instMnem, mnemonic);
154
155        return response.str();
156    }
157}};
158
159let {{
160    class Fault(X86Microop):
161        className = "MicroFault"
162        def __init__(self, fault, flags=None):
163            self.fault = fault
164            if flags:
165                if not isinstance(flags, (list, tuple)):
166                    raise Exception, "flags must be a list or tuple of flags"
167                self.cond = " | ".join(flags)
168                self.className += "Flags"
169            else:
170                self.cond = "0"
171
172        def getAllocator(self, microFlags):
173            allocator = '''new %(class_name)s(machInst, macrocodeBlock,
174                    %(flags)s, %(fault)s, %(cc)s)''' % {
175                "class_name" : self.className,
176                "flags" : self.microFlagsText(microFlags),
177                "fault" : self.fault,
178                "cc" : self.cond}
179            return allocator
180
181    iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase",
182            {"code": "",
183             "cond_test": "checkCondition(ccFlagBits, cc)"})
184    exec_output = MicroFaultExecute.subst(iop)
185    header_output = MicroFaultDeclare.subst(iop)
186    decoder_output = MicroFaultConstructor.subst(iop)
187    iop = InstObjParams("fault", "MicroFault", "MicroFaultBase",
188            {"code": "",
189             "cond_test": "true"})
190    exec_output += MicroFaultExecute.subst(iop)
191    header_output += MicroFaultDeclare.subst(iop)
192    decoder_output += MicroFaultConstructor.subst(iop)
193    microopClasses["fault"] = Fault
194
195    class Halt(X86Microop):
196        className = "MicroHalt"
197        def __init__(self):
198            pass
199
200        def getAllocator(self, microFlags):
201            return "new MicroHalt(machInst, macrocodeBlock, %s)" % \
202                    self.microFlagsText(microFlags)
203
204    microopClasses["halt"] = Halt
205}};
206