specop.isa revision 7626
12SN/A// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 29608Sandreas.hansson@arm.com// All rights reserved. 38707Sandreas.hansson@arm.com// 48707Sandreas.hansson@arm.com// The license below extends only to copyright in the software and shall 58707Sandreas.hansson@arm.com// not be construed as granting a license to any other intellectual 68707Sandreas.hansson@arm.com// property including but not limited to intellectual property relating 78707Sandreas.hansson@arm.com// to a hardware implementation of the functionality of the software 88707Sandreas.hansson@arm.com// licensed hereunder. You may use the software subject to the license 98707Sandreas.hansson@arm.com// terms below provided that you ensure that this notice is replicated 108707Sandreas.hansson@arm.com// unmodified and in its entirety in all distributions of the software, 118707Sandreas.hansson@arm.com// modified or unmodified, in source code or in binary form. 128707Sandreas.hansson@arm.com// 138707Sandreas.hansson@arm.com// Redistribution and use in source and binary forms, with or without 141762SN/A// modification, are permitted provided that the following conditions are 157897Shestness@cs.utexas.edu// met: redistributions of source code must retain the above copyright 162SN/A// notice, this list of conditions and the following disclaimer; 172SN/A// redistributions in binary form must reproduce the above copyright 182SN/A// notice, this list of conditions and the following disclaimer in the 192SN/A// documentation and/or other materials provided with the distribution; 202SN/A// neither the name of the copyright holders nor the names of its 212SN/A// contributors may be used to endorse or promote products derived from 222SN/A// this software without specific prior written permission. 232SN/A// 242SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 312SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 322SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 332SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 342SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 352SN/A// 362SN/A// Authors: Gabe Black 372SN/A 382SN/A////////////////////////////////////////////////////////////////////////// 392SN/A// 402665Ssaidi@eecs.umich.edu// Fault Microop 412665Ssaidi@eecs.umich.edu// 422665Ssaidi@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 437897Shestness@cs.utexas.edu 442SN/Aoutput header {{ 452SN/A class MicroFaultBase : public X86ISA::X86MicroopBase 461717SN/A { 471717SN/A protected: 482SN/A Fault fault; 492SN/A uint8_t cc; 502SN/A 518745Sgblack@eecs.umich.edu public: 524182Sgblack@eecs.umich.edu MicroFaultBase(ExtMachInst _machInst, const char * instMnem, 535664Sgblack@eecs.umich.edu uint64_t setFlags, Fault _fault, uint8_t _cc); 54707SN/A 556658Snate@binkert.org std::string generateDisassembly(Addr pc, 568229Snate@binkert.org const SymbolTable *symtab) const; 5756SN/A }; 588779Sgblack@eecs.umich.edu 594776Sgblack@eecs.umich.edu class MicroHalt : public X86ISA::X86MicroopBase 602SN/A { 618901Sandreas.hansson@arm.com public: 622190SN/A MicroHalt(ExtMachInst _machInst, const char * instMnem, 632315SN/A uint64_t setFlags) : 642680Sktlim@umich.edu X86MicroopBase(_machInst, "halt", instMnem, setFlags, No_OpClass) 652SN/A { 662SN/A } 672356SN/A 682356SN/A %(BasicExecDeclare)s 692356SN/A 706144Sksewell@umich.edu std::string generateDisassembly(Addr pc, 712356SN/A const SymbolTable *symtab) const; 722356SN/A }; 736144Sksewell@umich.edu}}; 742356SN/A 752356SN/Adef template MicroFaultDeclare {{ 766144Sksewell@umich.edu class %(class_name)s : public %(base_class)s 772356SN/A { 782356SN/A public: 792356SN/A %(class_name)s(ExtMachInst _machInst, const char * instMnem, 806144Sksewell@umich.edu uint64_t setFlags, Fault _fault, uint8_t _cc); 816144Sksewell@umich.edu 826144Sksewell@umich.edu %(BasicExecDeclare)s 836144Sksewell@umich.edu }; 846144Sksewell@umich.edu}}; 855336Shines@cs.fsu.edu 862356SN/Adef template MicroFaultExecute {{ 872356SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 882856Srdreslin@umich.edu Trace::InstRecord *traceData) const 892SN/A { 901634SN/A %(op_decl)s; 919157Sandreas.hansson@arm.com %(op_rd)s; 923814Ssaidi@eecs.umich.edu if (%(cond_test)s) { 933814Ssaidi@eecs.umich.edu //Return the fault we were constructed with 945712Shsul@eecs.umich.edu return fault; 955712Shsul@eecs.umich.edu } else { 965715Shsul@eecs.umich.edu return NoFault; 975712Shsul@eecs.umich.edu } 985712Shsul@eecs.umich.edu } 991634SN/A}}; 1008832SAli.Saidi@ARM.com 1018832SAli.Saidi@ARM.comoutput exec {{ 1028832SAli.Saidi@ARM.com Fault 1038832SAli.Saidi@ARM.com MicroHalt::execute(%(CPU_exec_context)s *xc, 1048832SAli.Saidi@ARM.com Trace::InstRecord * traceData) const 1058832SAli.Saidi@ARM.com { 1069332Sdam.sunwoo@arm.com xc->tcBase()->suspend(); 1079332Sdam.sunwoo@arm.com return NoFault; 1089332Sdam.sunwoo@arm.com } 1099332Sdam.sunwoo@arm.com}}; 1109332Sdam.sunwoo@arm.com 1119332Sdam.sunwoo@arm.comoutput decoder {{ 1129332Sdam.sunwoo@arm.com inline MicroFaultBase::MicroFaultBase( 1139332Sdam.sunwoo@arm.com ExtMachInst machInst, const char * instMnem, 1149332Sdam.sunwoo@arm.com uint64_t setFlags, Fault _fault, uint8_t _cc) : 1159332Sdam.sunwoo@arm.com X86MicroopBase(machInst, "fault", instMnem, setFlags, No_OpClass), 1169332Sdam.sunwoo@arm.com fault(_fault), cc(_cc) 1179430SAndreas.Sandberg@ARM.com { 1189430SAndreas.Sandberg@ARM.com } 1199430SAndreas.Sandberg@ARM.com}}; 1201634SN/A 1218850Sandreas.hansson@arm.comdef template MicroFaultConstructor {{ 1228850Sandreas.hansson@arm.com inline %(class_name)s::%(class_name)s( 1238850Sandreas.hansson@arm.com ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1248850Sandreas.hansson@arm.com Fault _fault, uint8_t _cc) : 1258850Sandreas.hansson@arm.com %(base_class)s(machInst, instMnem, setFlags, _fault, _cc) 1268850Sandreas.hansson@arm.com { 1278850Sandreas.hansson@arm.com %(constructor)s; 1289608Sandreas.hansson@arm.com } 1298850Sandreas.hansson@arm.com}}; 1308850Sandreas.hansson@arm.com 1318850Sandreas.hansson@arm.comoutput decoder {{ 1328850Sandreas.hansson@arm.com std::string MicroFaultBase::generateDisassembly(Addr pc, 1338850Sandreas.hansson@arm.com const SymbolTable *symtab) const 1348850Sandreas.hansson@arm.com { 1358850Sandreas.hansson@arm.com std::stringstream response; 1369608Sandreas.hansson@arm.com 1378850Sandreas.hansson@arm.com printMnemonic(response, instMnem, mnemonic); 1385712Shsul@eecs.umich.edu if(fault) 1395712Shsul@eecs.umich.edu response << fault->name(); 1405712Shsul@eecs.umich.edu else 1418832SAli.Saidi@ARM.com response << "No Fault"; 1428832SAli.Saidi@ARM.com 1438832SAli.Saidi@ARM.com return response.str(); 1448832SAli.Saidi@ARM.com } 1458832SAli.Saidi@ARM.com 1468850Sandreas.hansson@arm.com std::string MicroHalt::generateDisassembly(Addr pc, 1478926Sandreas.hansson@arm.com const SymbolTable *symtab) const 1488926Sandreas.hansson@arm.com { 1498926Sandreas.hansson@arm.com std::stringstream response; 1508850Sandreas.hansson@arm.com 1518850Sandreas.hansson@arm.com printMnemonic(response, instMnem, mnemonic); 1528850Sandreas.hansson@arm.com 1538850Sandreas.hansson@arm.com return response.str(); 1548922Swilliam.wang@arm.com } 1558850Sandreas.hansson@arm.com}}; 1569294Sandreas.hansson@arm.com 1579294Sandreas.hansson@arm.comlet {{ 1588850Sandreas.hansson@arm.com class Fault(X86Microop): 1599332Sdam.sunwoo@arm.com className = "MicroFault" 1609332Sdam.sunwoo@arm.com def __init__(self, fault, flags=None): 1619332Sdam.sunwoo@arm.com self.fault = fault 1629332Sdam.sunwoo@arm.com if flags: 1639332Sdam.sunwoo@arm.com if not isinstance(flags, (list, tuple)): 1649332Sdam.sunwoo@arm.com raise Exception, "flags must be a list or tuple of flags" 1659332Sdam.sunwoo@arm.com self.cond = " | ".join(flags) 1669332Sdam.sunwoo@arm.com self.className += "Flags" 1677914SBrad.Beckmann@amd.com else: 1687914SBrad.Beckmann@amd.com self.cond = "0" 1693814Ssaidi@eecs.umich.edu 1703814Ssaidi@eecs.umich.edu def getAllocator(self, microFlags): 1711634SN/A allocator = '''new %(class_name)s(machInst, macrocodeBlock, 1725664Sgblack@eecs.umich.edu %(flags)s, %(fault)s, %(cc)s)''' % { 1735664Sgblack@eecs.umich.edu "class_name" : self.className, 1742SN/A "flags" : self.microFlagsText(microFlags), 1755704Snate@binkert.org "fault" : self.fault, 1762SN/A "cc" : self.cond} 1772SN/A return allocator 1785645Sgblack@eecs.umich.edu 1795645Sgblack@eecs.umich.edu iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase", 1805645Sgblack@eecs.umich.edu {"code": "", 1815647Sgblack@eecs.umich.edu "cond_test": "checkCondition(ccFlagBits, cc)"}) 1825645Sgblack@eecs.umich.edu exec_output = MicroFaultExecute.subst(iop) 1835645Sgblack@eecs.umich.edu header_output = MicroFaultDeclare.subst(iop) 1845807Snate@binkert.org decoder_output = MicroFaultConstructor.subst(iop) 1855807Snate@binkert.org iop = InstObjParams("fault", "MicroFault", "MicroFaultBase", 1865807Snate@binkert.org {"code": "", 1875807Snate@binkert.org "cond_test": "true"}) 1885807Snate@binkert.org exec_output += MicroFaultExecute.subst(iop) 1895807Snate@binkert.org header_output += MicroFaultDeclare.subst(iop) 1908779Sgblack@eecs.umich.edu decoder_output += MicroFaultConstructor.subst(iop) 1918779Sgblack@eecs.umich.edu microopClasses["fault"] = Fault 1925807Snate@binkert.org 1935807Snate@binkert.org class Halt(X86Microop): 1945807Snate@binkert.org className = "MicroHalt" 1955807Snate@binkert.org def __init__(self): 1965807Snate@binkert.org pass 1975807Snate@binkert.org 1985807Snate@binkert.org def getAllocator(self, microFlags): 1995807Snate@binkert.org return "new MicroHalt(machInst, macrocodeBlock, %s)" % \ 2005807Snate@binkert.org self.microFlagsText(microFlags) 2015807Snate@binkert.org 2025807Snate@binkert.org microopClasses["halt"] = Halt 2035807Snate@binkert.org}}; 2045807Snate@binkert.org