regop.isa revision 8626
1955SN/A// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2955SN/A// All rights reserved. 31762SN/A// 4955SN/A// The license below extends only to copyright in the software and shall 5955SN/A// not be construed as granting a license to any other intellectual 6955SN/A// property including but not limited to intellectual property relating 7955SN/A// to a hardware implementation of the functionality of the software 8955SN/A// licensed hereunder. You may use the software subject to the license 9955SN/A// terms below provided that you ensure that this notice is replicated 10955SN/A// unmodified and in its entirety in all distributions of the software, 11955SN/A// modified or unmodified, in source code or in binary form. 12955SN/A// 13955SN/A// Redistribution and use in source and binary forms, with or without 14955SN/A// modification, are permitted provided that the following conditions are 15955SN/A// met: redistributions of source code must retain the above copyright 16955SN/A// notice, this list of conditions and the following disclaimer; 17955SN/A// redistributions in binary form must reproduce the above copyright 18955SN/A// notice, this list of conditions and the following disclaimer in the 19955SN/A// documentation and/or other materials provided with the distribution; 20955SN/A// neither the name of the copyright holders nor the names of its 21955SN/A// contributors may be used to endorse or promote products derived from 22955SN/A// this software without specific prior written permission. 23955SN/A// 24955SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25955SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26955SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27955SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282665Ssaidi@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292665Ssaidi@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30955SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31955SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32955SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 333583Sbinkertn@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34955SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35955SN/A// 36955SN/A// Authors: Gabe Black 37955SN/A 38955SN/A////////////////////////////////////////////////////////////////////////// 39955SN/A// 40955SN/A// RegOp Microop templates 41955SN/A// 42955SN/A////////////////////////////////////////////////////////////////////////// 43955SN/A 44955SN/Adef template MicroRegOpExecute {{ 45955SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 46955SN/A Trace::InstRecord *traceData) const 47955SN/A { 482023SN/A Fault fault = NoFault; 49955SN/A 503089Ssaidi@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 51955SN/A %(op_decl)s; 52955SN/A %(op_rd)s; 53955SN/A 54955SN/A IntReg result M5_VAR_USED; 55955SN/A 56955SN/A if(%(cond_check)s) 57955SN/A { 58955SN/A %(code)s; 591031SN/A %(flag_code)s; 60955SN/A } 611388SN/A else 62955SN/A { 63955SN/A %(else_code)s; 641296SN/A } 65955SN/A 66955SN/A //Write the resulting state to the execution context 67955SN/A if(fault == NoFault) 68955SN/A { 69955SN/A %(op_wb)s; 70955SN/A } 71955SN/A return fault; 72955SN/A } 73955SN/A}}; 74955SN/A 75955SN/Adef template MicroRegOpImmExecute {{ 76955SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 773584Ssaidi@eecs.umich.edu Trace::InstRecord *traceData) const 78955SN/A { 79955SN/A Fault fault = NoFault; 80955SN/A 81955SN/A %(op_decl)s; 82955SN/A %(op_rd)s; 83955SN/A 84955SN/A IntReg result M5_VAR_USED; 852325SN/A 861717SN/A if(%(cond_check)s) 872652Ssaidi@eecs.umich.edu { 88955SN/A %(code)s; 892736Sktlim@umich.edu %(flag_code)s; 902410SN/A } 91955SN/A else 922290SN/A { 93955SN/A %(else_code)s; 942683Sktlim@umich.edu } 952683Sktlim@umich.edu 962669Sktlim@umich.edu //Write the resulting state to the execution context 972568SN/A if(fault == NoFault) 982568SN/A { 993012Ssaidi@eecs.umich.edu %(op_wb)s; 1002462SN/A } 1012568SN/A return fault; 1022395SN/A } 1032405SN/A}}; 1042914Ssaidi@eecs.umich.edu 105955SN/Adef template MicroRegOpDeclare {{ 1062811Srdreslin@umich.edu class %(class_name)s : public %(base_class)s 1072811Srdreslin@umich.edu { 1082811Srdreslin@umich.edu public: 1092811Srdreslin@umich.edu %(class_name)s(ExtMachInst _machInst, 1102811Srdreslin@umich.edu const char * instMnem, uint64_t setFlags, 1113719Sstever@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1122811Srdreslin@umich.edu uint8_t _dataSize, uint16_t _ext); 1132811Srdreslin@umich.edu 1142811Srdreslin@umich.edu %(BasicExecDeclare)s 1152811Srdreslin@umich.edu }; 1162811Srdreslin@umich.edu}}; 1172811Srdreslin@umich.edu 1182811Srdreslin@umich.edudef template MicroRegOpImmDeclare {{ 1192811Srdreslin@umich.edu 1202811Srdreslin@umich.edu class %(class_name)s : public %(base_class)s 1212814Srdreslin@umich.edu { 1222811Srdreslin@umich.edu public: 1232811Srdreslin@umich.edu %(class_name)s(ExtMachInst _machInst, 1242811Srdreslin@umich.edu const char * instMnem, uint64_t setFlags, 1252811Srdreslin@umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1262811Srdreslin@umich.edu uint8_t _dataSize, uint16_t _ext); 1272811Srdreslin@umich.edu 1282811Srdreslin@umich.edu %(BasicExecDeclare)s 1292813Srdreslin@umich.edu }; 1302813Srdreslin@umich.edu}}; 1313868Sbinkertn@umich.edu 1323645Sbinkertn@umich.edudef template MicroRegOpConstructor {{ 1333624Sbinkertn@umich.edu inline %(class_name)s::%(class_name)s( 1343871Sbinkertn@umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1353871Sbinkertn@umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1363624Sbinkertn@umich.edu uint8_t _dataSize, uint16_t _ext) : 137955SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 138955SN/A _src1, _src2, _dest, _dataSize, _ext, 139955SN/A %(op_class)s) 1402090SN/A { 141955SN/A %(constructor)s; 142955SN/A %(cond_control_flag_init)s; 1431696SN/A } 144955SN/A}}; 145955SN/A 146955SN/Adef template MicroRegOpImmConstructor {{ 1471127SN/A inline %(class_name)s::%(class_name)s( 148955SN/A ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 149955SN/A InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1502379SN/A uint8_t _dataSize, uint16_t _ext) : 151955SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 152955SN/A _src1, _imm8, _dest, _dataSize, _ext, 153955SN/A %(op_class)s) 1542422SN/A { 1552422SN/A %(constructor)s; 1562422SN/A %(cond_control_flag_init)s; 1572422SN/A } 1582422SN/A}}; 1592422SN/A 1602422SN/Aoutput header {{ 1612397SN/A void 1622397SN/A divide(uint64_t dividend, uint64_t divisor, 1632422SN/A uint64_t "ient, uint64_t &remainder); 1642422SN/A 165955SN/A enum SegmentSelectorCheck { 166955SN/A SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 167955SN/A SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 168955SN/A SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 169955SN/A }; 170955SN/A 171955SN/A enum LongModeDescriptorType { 172955SN/A LDT64 = 2, 1731078SN/A AvailableTSS64 = 9, 174955SN/A BusyTSS64 = 0xb, 175955SN/A CallGate64 = 0xc, 176955SN/A IntGate64 = 0xe, 177955SN/A TrapGate64 = 0xf 1781917SN/A }; 179955SN/A}}; 180955SN/A 1811730SN/Aoutput decoder {{ 182955SN/A void 1832521SN/A divide(uint64_t dividend, uint64_t divisor, 1842521SN/A uint64_t "ient, uint64_t &remainder) 1852507SN/A { 1862507SN/A //Check for divide by zero. 1872989Ssaidi@eecs.umich.edu assert(divisor != 0); 1883408Ssaidi@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 1892507SN/A if (divisor <= dividend) { 1902507SN/A //Shift the divisor so it's msb lines up with the dividend. 1912507SN/A int dividendMsb = findMsbSet(dividend); 192955SN/A int divisorMsb = findMsbSet(divisor); 193955SN/A int shift = dividendMsb - divisorMsb; 194955SN/A divisor <<= shift; 195955SN/A //Compute what we'll add to the quotient if the divisor isn't 196955SN/A //now larger than the dividend. 197955SN/A uint64_t quotientBit = 1; 198955SN/A quotientBit <<= shift; 199955SN/A //If we need to step back a bit (no pun intended) because the 2002520SN/A //divisor got too to large, do that here. This is the "or two" 2012517SN/A //part of one or two bit division. 2022253SN/A if (divisor > dividend) { 2032253SN/A quotientBit >>= 1; 2042253SN/A divisor >>= 1; 2052253SN/A } 2062553SN/A //Decrement the remainder and increment the quotient. 2072553SN/A quotient += quotientBit; 2082553SN/A remainder -= divisor; 2092553SN/A } 2102507SN/A } 2112400SN/A}}; 2122400SN/A 213955SN/Alet {{ 214955SN/A # Make these empty strings so that concatenating onto 2152667Sstever@eecs.umich.edu # them will always work. 2162667Sstever@eecs.umich.edu header_output = "" 2172667Sstever@eecs.umich.edu decoder_output = "" 2182667Sstever@eecs.umich.edu exec_output = "" 2192667Sstever@eecs.umich.edu 2202667Sstever@eecs.umich.edu immTemplates = ( 2212037SN/A MicroRegOpImmDeclare, 2222037SN/A MicroRegOpImmConstructor, 2232037SN/A MicroRegOpImmExecute) 2243534Sgblack@eecs.umich.edu 2252139SN/A regTemplates = ( 2263534Sgblack@eecs.umich.edu MicroRegOpDeclare, 2273534Sgblack@eecs.umich.edu MicroRegOpConstructor, 2283542Sgblack@eecs.umich.edu MicroRegOpExecute) 2293583Sbinkertn@umich.edu 2303583Sbinkertn@umich.edu class RegOpMeta(type): 2313542Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, code, big_code, \ 2323499Ssaidi@eecs.umich.edu flag_code, cond_check, else_code, cond_control_flag_init): 2333583Sbinkertn@umich.edu 2343583Sbinkertn@umich.edu # Globals to stick the output in 2353547Sgblack@eecs.umich.edu global header_output 2362155SN/A global decoder_output 237955SN/A global exec_output 2382155SN/A 239955SN/A # Stick all the code together so it can be searched at once 2403583Sbinkertn@umich.edu allCode = "|".join((code, flag_code, cond_check, else_code, 2413583Sbinkertn@umich.edu cond_control_flag_init)) 2423583Sbinkertn@umich.edu allBigCode = "|".join((big_code, flag_code, cond_check, else_code, 2433583Sbinkertn@umich.edu cond_control_flag_init)) 2443583Sbinkertn@umich.edu 245955SN/A # If op2 is used anywhere, make register and immediate versions 246955SN/A # of this code. 247955SN/A matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?") 248955SN/A match = matcher.search(allCode + allBigCode) 249955SN/A if match: 2501858SN/A typeQual = "" 251955SN/A if match.group("typeQual"): 2521858SN/A typeQual = match.group("typeQual") 2531858SN/A src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 2541858SN/A self.buildCppClasses(name, Name, suffix, 2551085SN/A matcher.sub(src2_name, code), 256955SN/A matcher.sub(src2_name, big_code), 257955SN/A matcher.sub(src2_name, flag_code), 258955SN/A matcher.sub(src2_name, cond_check), 259955SN/A matcher.sub(src2_name, else_code), 260955SN/A matcher.sub(src2_name, cond_control_flag_init)) 261955SN/A imm_name = "%simm8" % match.group("prefix") 262955SN/A self.buildCppClasses(name + "i", Name, suffix + "Imm", 263955SN/A matcher.sub(imm_name, code), 264955SN/A matcher.sub(imm_name, big_code), 265955SN/A matcher.sub(imm_name, flag_code), 266955SN/A matcher.sub(imm_name, cond_check), 267955SN/A matcher.sub(imm_name, else_code), 2682667Sstever@eecs.umich.edu matcher.sub(imm_name, cond_control_flag_init)) 2691045SN/A return 270955SN/A 271955SN/A # If there's something optional to do with flags, generate 272955SN/A # a version without it and fix up this version to use it. 273955SN/A if flag_code != "" or cond_check != "true": 2741108SN/A self.buildCppClasses(name, Name, suffix, 275955SN/A code, big_code, "", "true", else_code, "") 276955SN/A suffix = "Flags" + suffix 277955SN/A 278955SN/A # If psrc1 or psrc2 is used, we need to actually insert code to 279955SN/A # compute it. 280955SN/A for (big, all) in ((False, allCode), (True, allBigCode)): 281955SN/A prefix = "" 282955SN/A for (rex, decl) in ( 283955SN/A ("(?<!\w)psrc1(?!\w)", 284955SN/A "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"), 285955SN/A ("(?<!\w)psrc2(?!\w)", 286955SN/A "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"), 287955SN/A ("(?<!\w)spsrc1(?!\w)", 288955SN/A "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"), 289955SN/A ("(?<!\w)spsrc2(?!\w)", 290955SN/A "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"), 2912655Sstever@eecs.umich.edu ("(?<!\w)simm8(?!\w)", 2922655Sstever@eecs.umich.edu "int8_t simm8 = imm8;")): 2932655Sstever@eecs.umich.edu matcher = re.compile(rex) 2942655Sstever@eecs.umich.edu if matcher.search(all): 2952655Sstever@eecs.umich.edu prefix += decl + "\n" 2962655Sstever@eecs.umich.edu if big: 2972655Sstever@eecs.umich.edu if big_code != "": 2982655Sstever@eecs.umich.edu big_code = prefix + big_code 2992655Sstever@eecs.umich.edu else: 3002655Sstever@eecs.umich.edu code = prefix + code 3012655Sstever@eecs.umich.edu 3022655Sstever@eecs.umich.edu base = "X86ISA::RegOp" 3032655Sstever@eecs.umich.edu 3042655Sstever@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3052655Sstever@eecs.umich.edu # not, hopefully the register ones will be correct. 3062655Sstever@eecs.umich.edu templates = regTemplates 3072655Sstever@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3082655Sstever@eecs.umich.edu if matcher.search(allCode): 3092655Sstever@eecs.umich.edu base += "Imm" 3102655Sstever@eecs.umich.edu templates = immTemplates 3112655Sstever@eecs.umich.edu 3122655Sstever@eecs.umich.edu # Get everything ready for the substitution 313955SN/A iops = [InstObjParams(name, Name + suffix, base, 3143918Ssaidi@eecs.umich.edu {"code" : code, 3153918Ssaidi@eecs.umich.edu "flag_code" : flag_code, 3163918Ssaidi@eecs.umich.edu "cond_check" : cond_check, 3173918Ssaidi@eecs.umich.edu "else_code" : else_code, 3183918Ssaidi@eecs.umich.edu "cond_control_flag_init" : cond_control_flag_init})] 3193918Ssaidi@eecs.umich.edu if big_code != "": 3203918Ssaidi@eecs.umich.edu iops += [InstObjParams(name, Name + suffix + "Big", base, 3213918Ssaidi@eecs.umich.edu {"code" : big_code, 3223918Ssaidi@eecs.umich.edu "flag_code" : flag_code, 3233918Ssaidi@eecs.umich.edu "cond_check" : cond_check, 3243918Ssaidi@eecs.umich.edu "else_code" : else_code, 3253918Ssaidi@eecs.umich.edu "cond_control_flag_init" : 3263918Ssaidi@eecs.umich.edu cond_control_flag_init})] 3273918Ssaidi@eecs.umich.edu 3283940Ssaidi@eecs.umich.edu # Generate the actual code (finally!) 3293940Ssaidi@eecs.umich.edu for iop in iops: 3303940Ssaidi@eecs.umich.edu header_output += templates[0].subst(iop) 3313942Ssaidi@eecs.umich.edu decoder_output += templates[1].subst(iop) 3323940Ssaidi@eecs.umich.edu exec_output += templates[2].subst(iop) 3333515Ssaidi@eecs.umich.edu 3343918Ssaidi@eecs.umich.edu 3353918Ssaidi@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3363515Ssaidi@eecs.umich.edu abstract = False 3372655Sstever@eecs.umich.edu name = Name.lower() 3383918Ssaidi@eecs.umich.edu if "abstract" in dict: 3393619Sbinkertn@umich.edu abstract = dict['abstract'] 340955SN/A del dict['abstract'] 341955SN/A 3422655Sstever@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3433918Ssaidi@eecs.umich.edu if not abstract: 3443619Sbinkertn@umich.edu cls.className = Name 345955SN/A cls.base_mnemonic = name 346955SN/A code = cls.code 3472655Sstever@eecs.umich.edu big_code = cls.big_code 3483918Ssaidi@eecs.umich.edu flag_code = cls.flag_code 3493619Sbinkertn@umich.edu cond_check = cls.cond_check 350955SN/A else_code = cls.else_code 351955SN/A cond_control_flag_init = cls.cond_control_flag_init 3522655Sstever@eecs.umich.edu 3533918Ssaidi@eecs.umich.edu # Set up the C++ classes 3543683Sstever@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", code, big_code, 3552655Sstever@eecs.umich.edu flag_code, cond_check, else_code, 3561869SN/A cond_control_flag_init) 3571869SN/A 358 # Hook into the microassembler dict 359 global microopClasses 360 microopClasses[name] = cls 361 362 allCode = "|".join((code, flag_code, cond_check, else_code, 363 cond_control_flag_init)) 364 365 # If op2 is used anywhere, make register and immediate versions 366 # of this code. 367 matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?") 368 if matcher.search(allCode): 369 microopClasses[name + 'i'] = cls 370 return cls 371 372 373 class RegOp(X86Microop): 374 __metaclass__ = RegOpMeta 375 # This class itself doesn't act as a microop 376 abstract = True 377 378 # Default template parameter values 379 big_code = "" 380 flag_code = "" 381 cond_check = "true" 382 else_code = ";" 383 cond_control_flag_init = "" 384 385 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 386 self.dest = dest 387 self.src1 = src1 388 self.op2 = op2 389 self.flags = flags 390 self.dataSize = dataSize 391 if flags is None: 392 self.ext = 0 393 else: 394 if not isinstance(flags, (list, tuple)): 395 raise Exception, "flags must be a list or tuple of flags" 396 self.ext = " | ".join(flags) 397 self.className += "Flags" 398 399 def getAllocator(self, microFlags): 400 if self.big_code != "": 401 className = self.className 402 if self.mnemonic == self.base_mnemonic + 'i': 403 className += "Imm" 404 allocString = ''' 405 (%(dataSize)s >= 4) ? 406 (StaticInstPtr)(new %(class_name)sBig(machInst, 407 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 408 %(dest)s, %(dataSize)s, %(ext)s)) : 409 (StaticInstPtr)(new %(class_name)s(machInst, 410 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 411 %(dest)s, %(dataSize)s, %(ext)s)) 412 ''' 413 allocator = allocString % { 414 "class_name" : className, 415 "flags" : self.microFlagsText(microFlags), 416 "src1" : self.src1, "op2" : self.op2, 417 "dest" : self.dest, 418 "dataSize" : self.dataSize, 419 "ext" : self.ext} 420 return allocator 421 else: 422 className = self.className 423 if self.mnemonic == self.base_mnemonic + 'i': 424 className += "Imm" 425 allocator = '''new %(class_name)s(machInst, macrocodeBlock, 426 %(flags)s, %(src1)s, %(op2)s, %(dest)s, 427 %(dataSize)s, %(ext)s)''' % { 428 "class_name" : className, 429 "flags" : self.microFlagsText(microFlags), 430 "src1" : self.src1, "op2" : self.op2, 431 "dest" : self.dest, 432 "dataSize" : self.dataSize, 433 "ext" : self.ext} 434 return allocator 435 436 class LogicRegOp(RegOp): 437 abstract = True 438 flag_code = ''' 439 //Don't have genFlags handle the OF or CF bits 440 uint64_t mask = CFBit | ECFBit | OFBit; 441 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2); 442 //If a logic microop wants to set these, it wants to set them to 0. 443 ccFlagBits &= ~(CFBit & ext); 444 ccFlagBits &= ~(ECFBit & ext); 445 ccFlagBits &= ~(OFBit & ext); 446 ''' 447 448 class FlagRegOp(RegOp): 449 abstract = True 450 flag_code = \ 451 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);" 452 453 class SubRegOp(RegOp): 454 abstract = True 455 flag_code = \ 456 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);" 457 458 class CondRegOp(RegOp): 459 abstract = True 460 cond_check = "checkCondition(ccFlagBits, ext)" 461 cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];" 462 463 class RdRegOp(RegOp): 464 abstract = True 465 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 466 if not src1: 467 src1 = dest 468 super(RdRegOp, self).__init__(dest, src1, \ 469 "InstRegIndex(NUM_INTREGS)", None, dataSize) 470 471 class WrRegOp(RegOp): 472 abstract = True 473 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 474 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 475 src1, src2, flags, dataSize) 476 477 class Add(FlagRegOp): 478 code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' 479 big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' 480 481 class Or(LogicRegOp): 482 code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' 483 big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' 484 485 class Adc(FlagRegOp): 486 code = ''' 487 CCFlagBits flags = ccFlagBits; 488 DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); 489 ''' 490 big_code = ''' 491 CCFlagBits flags = ccFlagBits; 492 DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); 493 ''' 494 495 class Sbb(SubRegOp): 496 code = ''' 497 CCFlagBits flags = ccFlagBits; 498 DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); 499 ''' 500 big_code = ''' 501 CCFlagBits flags = ccFlagBits; 502 DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); 503 ''' 504 505 class And(LogicRegOp): 506 code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' 507 big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' 508 509 class Sub(SubRegOp): 510 code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' 511 big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' 512 513 class Xor(LogicRegOp): 514 code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' 515 big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)' 516 517 class Mul1s(WrRegOp): 518 code = ''' 519 ProdLow = psrc1 * op2; 520 int halfSize = (dataSize * 8) / 2; 521 uint64_t shifter = (ULL(1) << halfSize); 522 uint64_t hiResult; 523 uint64_t psrc1_h = psrc1 / shifter; 524 uint64_t psrc1_l = psrc1 & mask(halfSize); 525 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 526 uint64_t psrc2_l = op2 & mask(halfSize); 527 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 528 ((psrc1_l * psrc2_l) / shifter)) /shifter) + 529 psrc1_h * psrc2_h; 530 if (bits(psrc1, dataSize * 8 - 1)) 531 hiResult -= op2; 532 if (bits(op2, dataSize * 8 - 1)) 533 hiResult -= psrc1; 534 ProdHi = hiResult; 535 ''' 536 flag_code = ''' 537 if ((-ProdHi & mask(dataSize * 8)) != 538 bits(ProdLow, dataSize * 8 - 1)) { 539 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 540 } else { 541 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 542 } 543 ''' 544 545 class Mul1u(WrRegOp): 546 code = ''' 547 ProdLow = psrc1 * op2; 548 int halfSize = (dataSize * 8) / 2; 549 uint64_t shifter = (ULL(1) << halfSize); 550 uint64_t psrc1_h = psrc1 / shifter; 551 uint64_t psrc1_l = psrc1 & mask(halfSize); 552 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 553 uint64_t psrc2_l = op2 & mask(halfSize); 554 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 555 ((psrc1_l * psrc2_l) / shifter)) / shifter) + 556 psrc1_h * psrc2_h; 557 ''' 558 flag_code = ''' 559 if (ProdHi) { 560 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 561 } else { 562 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 563 } 564 ''' 565 566 class Mulel(RdRegOp): 567 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 568 big_code = 'DestReg = ProdLow & mask(dataSize * 8);' 569 570 class Muleh(RdRegOp): 571 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 572 if not src1: 573 src1 = dest 574 super(RdRegOp, self).__init__(dest, src1, \ 575 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 576 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 577 big_code = 'DestReg = ProdHi & mask(dataSize * 8);' 578 579 # One or two bit divide 580 class Div1(WrRegOp): 581 code = ''' 582 //These are temporaries so that modifying them later won't make 583 //the ISA parser think they're also sources. 584 uint64_t quotient = 0; 585 uint64_t remainder = psrc1; 586 //Similarly, this is a temporary so changing it doesn't make it 587 //a source. 588 uint64_t divisor = op2; 589 //This is a temporary just for consistency and clarity. 590 uint64_t dividend = remainder; 591 //Do the division. 592 if (divisor == 0) { 593 fault = new DivideByZero; 594 } else { 595 divide(dividend, divisor, quotient, remainder); 596 //Record the final results. 597 Remainder = remainder; 598 Quotient = quotient; 599 Divisor = divisor; 600 } 601 ''' 602 603 # Step divide 604 class Div2(RegOp): 605 divCode = ''' 606 uint64_t dividend = Remainder; 607 uint64_t divisor = Divisor; 608 uint64_t quotient = Quotient; 609 uint64_t remainder = dividend; 610 int remaining = op2; 611 //If we overshot, do nothing. This lets us unrool division loops a 612 //little. 613 if (divisor == 0) { 614 fault = new DivideByZero; 615 } else if (remaining) { 616 if (divisor & (ULL(1) << 63)) { 617 while (remaining && !(dividend & (ULL(1) << 63))) { 618 dividend = (dividend << 1) | 619 bits(SrcReg1, remaining - 1); 620 quotient <<= 1; 621 remaining--; 622 } 623 if (dividend & (ULL(1) << 63)) { 624 bool highBit = false; 625 if (dividend < divisor && remaining) { 626 highBit = true; 627 dividend = (dividend << 1) | 628 bits(SrcReg1, remaining - 1); 629 quotient <<= 1; 630 remaining--; 631 } 632 if (highBit || divisor <= dividend) { 633 quotient++; 634 dividend -= divisor; 635 } 636 } 637 remainder = dividend; 638 } else { 639 //Shift in bits from the low order portion of the dividend 640 while (dividend < divisor && remaining) { 641 dividend = (dividend << 1) | 642 bits(SrcReg1, remaining - 1); 643 quotient <<= 1; 644 remaining--; 645 } 646 remainder = dividend; 647 //Do the division. 648 divide(dividend, divisor, quotient, remainder); 649 } 650 } 651 //Keep track of how many bits there are still to pull in. 652 %s 653 //Record the final results 654 Remainder = remainder; 655 Quotient = quotient; 656 ''' 657 code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" 658 big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" 659 flag_code = ''' 660 if (remaining == 0) 661 ccFlagBits = ccFlagBits | (ext & EZFBit); 662 else 663 ccFlagBits = ccFlagBits & ~(ext & EZFBit); 664 ''' 665 666 class Divq(RdRegOp): 667 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 668 big_code = 'DestReg = Quotient & mask(dataSize * 8);' 669 670 class Divr(RdRegOp): 671 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 672 big_code = 'DestReg = Remainder & mask(dataSize * 8);' 673 674 class Mov(CondRegOp): 675 code = 'DestReg = merge(SrcReg1, op2, dataSize)' 676 else_code = 'DestReg = DestReg;' 677 678 # Shift instructions 679 680 class Sll(RegOp): 681 code = ''' 682 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 683 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 684 ''' 685 big_code = ''' 686 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 687 DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); 688 ''' 689 flag_code = ''' 690 // If the shift amount is zero, no flags should be modified. 691 if (shiftAmt) { 692 //Zero out any flags we might modify. This way we only have to 693 //worry about setting them. 694 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 695 int CFBits = 0; 696 //Figure out if we -would- set the CF bits if requested. 697 if (shiftAmt <= dataSize * 8 && 698 bits(SrcReg1, dataSize * 8 - shiftAmt)) { 699 CFBits = 1; 700 } 701 //If some combination of the CF bits need to be set, set them. 702 if ((ext & (CFBit | ECFBit)) && CFBits) 703 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 704 //Figure out what the OF bit should be. 705 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 706 ccFlagBits = ccFlagBits | OFBit; 707 //Use the regular mechanisms to calculate the other flags. 708 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 709 DestReg, psrc1, op2); 710 } 711 ''' 712 713 class Srl(RegOp): 714 # Because what happens to the bits shift -in- on a right shift 715 # is not defined in the C/C++ standard, we have to mask them out 716 # to be sure they're zero. 717 code = ''' 718 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 719 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 720 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 721 ''' 722 big_code = ''' 723 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 724 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 725 DestReg = (psrc1 >> shiftAmt) & logicalMask; 726 ''' 727 flag_code = ''' 728 // If the shift amount is zero, no flags should be modified. 729 if (shiftAmt) { 730 //Zero out any flags we might modify. This way we only have to 731 //worry about setting them. 732 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 733 //If some combination of the CF bits need to be set, set them. 734 if ((ext & (CFBit | ECFBit)) && 735 shiftAmt <= dataSize * 8 && 736 bits(SrcReg1, shiftAmt - 1)) { 737 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 738 } 739 //Figure out what the OF bit should be. 740 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 741 ccFlagBits = ccFlagBits | OFBit; 742 //Use the regular mechanisms to calculate the other flags. 743 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 744 DestReg, psrc1, op2); 745 } 746 ''' 747 748 class Sra(RegOp): 749 # Because what happens to the bits shift -in- on a right shift 750 # is not defined in the C/C++ standard, we have to sign extend 751 # them manually to be sure. 752 code = ''' 753 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 754 uint64_t arithMask = (shiftAmt == 0) ? 0 : 755 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 756 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 757 ''' 758 big_code = ''' 759 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 760 uint64_t arithMask = (shiftAmt == 0) ? 0 : 761 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 762 DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); 763 ''' 764 flag_code = ''' 765 // If the shift amount is zero, no flags should be modified. 766 if (shiftAmt) { 767 //Zero out any flags we might modify. This way we only have to 768 //worry about setting them. 769 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 770 //If some combination of the CF bits need to be set, set them. 771 uint8_t effectiveShift = 772 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 773 if ((ext & (CFBit | ECFBit)) && 774 bits(SrcReg1, effectiveShift - 1)) { 775 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 776 } 777 //Use the regular mechanisms to calculate the other flags. 778 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 779 DestReg, psrc1, op2); 780 } 781 ''' 782 783 class Ror(RegOp): 784 code = ''' 785 uint8_t shiftAmt = 786 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 787 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 788 if (realShiftAmt) { 789 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 790 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 791 DestReg = merge(DestReg, top | bottom, dataSize); 792 } else 793 DestReg = merge(DestReg, DestReg, dataSize); 794 ''' 795 flag_code = ''' 796 // If the shift amount is zero, no flags should be modified. 797 if (shiftAmt) { 798 //Zero out any flags we might modify. This way we only have to 799 //worry about setting them. 800 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 801 //Find the most and second most significant bits of the result. 802 int msb = bits(DestReg, dataSize * 8 - 1); 803 int smsb = bits(DestReg, dataSize * 8 - 2); 804 //If some combination of the CF bits need to be set, set them. 805 if ((ext & (CFBit | ECFBit)) && msb) 806 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 807 //Figure out what the OF bit should be. 808 if ((ext & OFBit) && (msb ^ smsb)) 809 ccFlagBits = ccFlagBits | OFBit; 810 //Use the regular mechanisms to calculate the other flags. 811 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 812 DestReg, psrc1, op2); 813 } 814 ''' 815 816 class Rcr(RegOp): 817 code = ''' 818 uint8_t shiftAmt = 819 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 820 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 821 if (realShiftAmt) { 822 CCFlagBits flags = ccFlagBits; 823 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 824 if (realShiftAmt > 1) 825 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 826 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 827 DestReg = merge(DestReg, top | bottom, dataSize); 828 } else 829 DestReg = merge(DestReg, DestReg, dataSize); 830 ''' 831 flag_code = ''' 832 // If the shift amount is zero, no flags should be modified. 833 if (shiftAmt) { 834 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 835 //Zero out any flags we might modify. This way we only have to 836 //worry about setting them. 837 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 838 //Figure out what the OF bit should be. 839 if ((ext & OFBit) && (origCFBit ^ 840 bits(SrcReg1, dataSize * 8 - 1))) { 841 ccFlagBits = ccFlagBits | OFBit; 842 } 843 //If some combination of the CF bits need to be set, set them. 844 if ((ext & (CFBit | ECFBit)) && 845 (realShiftAmt == 0) ? origCFBit : 846 bits(SrcReg1, realShiftAmt - 1)) { 847 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 848 } 849 //Use the regular mechanisms to calculate the other flags. 850 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 851 DestReg, psrc1, op2); 852 } 853 ''' 854 855 class Rol(RegOp): 856 code = ''' 857 uint8_t shiftAmt = 858 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 859 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 860 if (realShiftAmt) { 861 uint64_t top = psrc1 << realShiftAmt; 862 uint64_t bottom = 863 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 864 DestReg = merge(DestReg, top | bottom, dataSize); 865 } else 866 DestReg = merge(DestReg, DestReg, dataSize); 867 ''' 868 flag_code = ''' 869 // If the shift amount is zero, no flags should be modified. 870 if (shiftAmt) { 871 //Zero out any flags we might modify. This way we only have to 872 //worry about setting them. 873 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 874 //The CF bits, if set, would be set to the lsb of the result. 875 int lsb = DestReg & 0x1; 876 int msb = bits(DestReg, dataSize * 8 - 1); 877 //If some combination of the CF bits need to be set, set them. 878 if ((ext & (CFBit | ECFBit)) && lsb) 879 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 880 //Figure out what the OF bit should be. 881 if ((ext & OFBit) && (msb ^ lsb)) 882 ccFlagBits = ccFlagBits | OFBit; 883 //Use the regular mechanisms to calculate the other flags. 884 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 885 DestReg, psrc1, op2); 886 } 887 ''' 888 889 class Rcl(RegOp): 890 code = ''' 891 uint8_t shiftAmt = 892 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 893 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 894 if (realShiftAmt) { 895 CCFlagBits flags = ccFlagBits; 896 uint64_t top = psrc1 << realShiftAmt; 897 uint64_t bottom = flags.cf << (realShiftAmt - 1); 898 if(shiftAmt > 1) 899 bottom |= 900 bits(psrc1, dataSize * 8 - 1, 901 dataSize * 8 - realShiftAmt + 1); 902 DestReg = merge(DestReg, top | bottom, dataSize); 903 } else 904 DestReg = merge(DestReg, DestReg, dataSize); 905 ''' 906 flag_code = ''' 907 // If the shift amount is zero, no flags should be modified. 908 if (shiftAmt) { 909 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 910 //Zero out any flags we might modify. This way we only have to 911 //worry about setting them. 912 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 913 int msb = bits(DestReg, dataSize * 8 - 1); 914 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 915 //If some combination of the CF bits need to be set, set them. 916 if ((ext & (CFBit | ECFBit)) && 917 (realShiftAmt == 0) ? origCFBit : CFBits) 918 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 919 //Figure out what the OF bit should be. 920 if ((ext & OFBit) && (msb ^ CFBits)) 921 ccFlagBits = ccFlagBits | OFBit; 922 //Use the regular mechanisms to calculate the other flags. 923 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 924 DestReg, psrc1, op2); 925 } 926 ''' 927 928 class Sld(RegOp): 929 sldCode = ''' 930 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 931 uint8_t dataBits = dataSize * 8; 932 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 933 uint64_t result; 934 if (realShiftAmt == 0) { 935 result = psrc1; 936 } else if (realShiftAmt < dataBits) { 937 result = (psrc1 << realShiftAmt) | 938 (DoubleBits >> (dataBits - realShiftAmt)); 939 } else { 940 result = (DoubleBits << (realShiftAmt - dataBits)) | 941 (psrc1 >> (2 * dataBits - realShiftAmt)); 942 } 943 %s 944 ''' 945 code = sldCode % "DestReg = merge(DestReg, result, dataSize);" 946 big_code = sldCode % "DestReg = result & mask(dataSize * 8);" 947 flag_code = ''' 948 // If the shift amount is zero, no flags should be modified. 949 if (shiftAmt) { 950 //Zero out any flags we might modify. This way we only have to 951 //worry about setting them. 952 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 953 int CFBits = 0; 954 //Figure out if we -would- set the CF bits if requested. 955 if ((realShiftAmt == 0 && 956 bits(DoubleBits, 0)) || 957 (realShiftAmt <= dataBits && 958 bits(SrcReg1, dataBits - realShiftAmt)) || 959 (realShiftAmt > dataBits && 960 bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 961 CFBits = 1; 962 } 963 //If some combination of the CF bits need to be set, set them. 964 if ((ext & (CFBit | ECFBit)) && CFBits) 965 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 966 //Figure out what the OF bit should be. 967 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 968 bits(result, dataBits - 1))) 969 ccFlagBits = ccFlagBits | OFBit; 970 //Use the regular mechanisms to calculate the other flags. 971 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 972 DestReg, psrc1, op2); 973 } 974 ''' 975 976 class Srd(RegOp): 977 srdCode = ''' 978 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 979 uint8_t dataBits = dataSize * 8; 980 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 981 uint64_t result; 982 if (realShiftAmt == 0) { 983 result = psrc1; 984 } else if (realShiftAmt < dataBits) { 985 // Because what happens to the bits shift -in- on a right 986 // shift is not defined in the C/C++ standard, we have to 987 // mask them out to be sure they're zero. 988 uint64_t logicalMask = mask(dataBits - realShiftAmt); 989 result = ((psrc1 >> realShiftAmt) & logicalMask) | 990 (DoubleBits << (dataBits - realShiftAmt)); 991 } else { 992 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 993 result = ((DoubleBits >> (realShiftAmt - dataBits)) & 994 logicalMask) | 995 (psrc1 << (2 * dataBits - realShiftAmt)); 996 } 997 %s 998 ''' 999 code = srdCode % "DestReg = merge(DestReg, result, dataSize);" 1000 big_code = srdCode % "DestReg = result & mask(dataSize * 8);" 1001 flag_code = ''' 1002 // If the shift amount is zero, no flags should be modified. 1003 if (shiftAmt) { 1004 //Zero out any flags we might modify. This way we only have to 1005 //worry about setting them. 1006 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 1007 int CFBits = 0; 1008 //If some combination of the CF bits need to be set, set them. 1009 if ((realShiftAmt == 0 && 1010 bits(DoubleBits, dataBits - 1)) || 1011 (realShiftAmt <= dataBits && 1012 bits(SrcReg1, realShiftAmt - 1)) || 1013 (realShiftAmt > dataBits && 1014 bits(DoubleBits, realShiftAmt - dataBits - 1))) { 1015 CFBits = 1; 1016 } 1017 //If some combination of the CF bits need to be set, set them. 1018 if ((ext & (CFBit | ECFBit)) && CFBits) 1019 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 1020 //Figure out what the OF bit should be. 1021 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 1022 bits(result, dataBits - 1))) 1023 ccFlagBits = ccFlagBits | OFBit; 1024 //Use the regular mechanisms to calculate the other flags. 1025 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 1026 DestReg, psrc1, op2); 1027 } 1028 ''' 1029 1030 class Mdb(WrRegOp): 1031 code = 'DoubleBits = psrc1 ^ op2;' 1032 1033 class Wrip(WrRegOp, CondRegOp): 1034 code = 'NRIP = psrc1 + sop2 + CSBase;' 1035 else_code = "NRIP = NRIP;" 1036 1037 class Wruflags(WrRegOp): 1038 code = 'ccFlagBits = psrc1 ^ op2' 1039 1040 class Wrflags(WrRegOp): 1041 code = ''' 1042 MiscReg newFlags = psrc1 ^ op2; 1043 MiscReg userFlagMask = 0xDD5; 1044 // Get only the user flags 1045 ccFlagBits = newFlags & userFlagMask; 1046 // Get everything else 1047 nccFlagBits = newFlags & ~userFlagMask; 1048 ''' 1049 1050 class Rdip(RdRegOp): 1051 code = 'DestReg = NRIP - CSBase;' 1052 1053 class Ruflags(RdRegOp): 1054 code = 'DestReg = ccFlagBits' 1055 1056 class Rflags(RdRegOp): 1057 code = 'DestReg = ccFlagBits | nccFlagBits' 1058 1059 class Ruflag(RegOp): 1060 code = ''' 1061 int flag = bits(ccFlagBits, imm8); 1062 DestReg = merge(DestReg, flag, dataSize); 1063 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1064 (ccFlagBits & ~EZFBit); 1065 ''' 1066 big_code = ''' 1067 int flag = bits(ccFlagBits, imm8); 1068 DestReg = flag & mask(dataSize * 8); 1069 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1070 (ccFlagBits & ~EZFBit); 1071 ''' 1072 def __init__(self, dest, imm, flags=None, \ 1073 dataSize="env.dataSize"): 1074 super(Ruflag, self).__init__(dest, \ 1075 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 1076 1077 class Rflag(RegOp): 1078 code = ''' 1079 MiscReg flagMask = 0x3F7FDD5; 1080 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 1081 int flag = bits(flags, imm8); 1082 DestReg = merge(DestReg, flag, dataSize); 1083 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1084 (ccFlagBits & ~EZFBit); 1085 ''' 1086 big_code = ''' 1087 MiscReg flagMask = 0x3F7FDD5; 1088 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 1089 int flag = bits(flags, imm8); 1090 DestReg = flag & mask(dataSize * 8); 1091 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1092 (ccFlagBits & ~EZFBit); 1093 ''' 1094 def __init__(self, dest, imm, flags=None, \ 1095 dataSize="env.dataSize"): 1096 super(Rflag, self).__init__(dest, \ 1097 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 1098 1099 class Sext(RegOp): 1100 code = ''' 1101 IntReg val = psrc1; 1102 // Mask the bit position so that it wraps. 1103 int bitPos = op2 & (dataSize * 8 - 1); 1104 int sign_bit = bits(val, bitPos, bitPos); 1105 uint64_t maskVal = mask(bitPos+1); 1106 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 1107 DestReg = merge(DestReg, val, dataSize); 1108 ''' 1109 big_code = ''' 1110 IntReg val = psrc1; 1111 // Mask the bit position so that it wraps. 1112 int bitPos = op2 & (dataSize * 8 - 1); 1113 int sign_bit = bits(val, bitPos, bitPos); 1114 uint64_t maskVal = mask(bitPos+1); 1115 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 1116 DestReg = val & mask(dataSize * 8); 1117 ''' 1118 flag_code = ''' 1119 if (!sign_bit) 1120 ccFlagBits = ccFlagBits & 1121 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1122 else 1123 ccFlagBits = ccFlagBits | 1124 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1125 ''' 1126 1127 class Zext(RegOp): 1128 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 1129 big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' 1130 1131 class Rddr(RegOp): 1132 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1133 super(Rddr, self).__init__(dest, \ 1134 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1135 rdrCode = ''' 1136 CR4 cr4 = CR4Op; 1137 DR7 dr7 = DR7Op; 1138 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 1139 fault = new InvalidOpcode(); 1140 } else if (dr7.gd) { 1141 fault = new DebugException(); 1142 } else { 1143 %s 1144 } 1145 ''' 1146 code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" 1147 big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" 1148 1149 class Wrdr(RegOp): 1150 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1151 super(Wrdr, self).__init__(dest, \ 1152 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1153 code = ''' 1154 CR4 cr4 = CR4Op; 1155 DR7 dr7 = DR7Op; 1156 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 1157 fault = new InvalidOpcode(); 1158 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 1159 machInst.mode.mode == LongMode) { 1160 fault = new GeneralProtection(0); 1161 } else if (dr7.gd) { 1162 fault = new DebugException(); 1163 } else { 1164 DebugDest = psrc1; 1165 } 1166 ''' 1167 1168 class Rdcr(RegOp): 1169 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1170 super(Rdcr, self).__init__(dest, \ 1171 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1172 rdcrCode = ''' 1173 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 1174 fault = new InvalidOpcode(); 1175 } else { 1176 %s 1177 } 1178 ''' 1179 code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" 1180 big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" 1181 1182 class Wrcr(RegOp): 1183 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1184 super(Wrcr, self).__init__(dest, \ 1185 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1186 code = ''' 1187 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 1188 fault = new InvalidOpcode(); 1189 } else { 1190 // There are *s in the line below so it doesn't confuse the 1191 // parser. They may be unnecessary. 1192 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 1193 MiscReg newVal = psrc1; 1194 1195 // Check for any modifications that would cause a fault. 1196 switch(dest) { 1197 case 0: 1198 { 1199 Efer efer = EferOp; 1200 CR0 cr0 = newVal; 1201 CR4 oldCr4 = CR4Op; 1202 if (bits(newVal, 63, 32) || 1203 (!cr0.pe && cr0.pg) || 1204 (!cr0.cd && cr0.nw) || 1205 (cr0.pg && efer.lme && !oldCr4.pae)) 1206 fault = new GeneralProtection(0); 1207 } 1208 break; 1209 case 2: 1210 break; 1211 case 3: 1212 break; 1213 case 4: 1214 { 1215 CR4 cr4 = newVal; 1216 // PAE can't be disabled in long mode. 1217 if (bits(newVal, 63, 11) || 1218 (machInst.mode.mode == LongMode && !cr4.pae)) 1219 fault = new GeneralProtection(0); 1220 } 1221 break; 1222 case 8: 1223 { 1224 if (bits(newVal, 63, 4)) 1225 fault = new GeneralProtection(0); 1226 } 1227 default: 1228 panic("Unrecognized control register %d.\\n", dest); 1229 } 1230 ControlDest = newVal; 1231 } 1232 ''' 1233 1234 # Microops for manipulating segmentation registers 1235 class SegOp(CondRegOp): 1236 abstract = True 1237 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1238 super(SegOp, self).__init__(dest, \ 1239 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1240 1241 class Wrbase(SegOp): 1242 code = ''' 1243 SegBaseDest = psrc1; 1244 ''' 1245 1246 class Wrlimit(SegOp): 1247 code = ''' 1248 SegLimitDest = psrc1; 1249 ''' 1250 1251 class Wrsel(SegOp): 1252 code = ''' 1253 SegSelDest = psrc1; 1254 ''' 1255 1256 class WrAttr(SegOp): 1257 code = ''' 1258 SegAttrDest = psrc1; 1259 ''' 1260 1261 class Rdbase(SegOp): 1262 code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' 1263 big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' 1264 1265 class Rdlimit(SegOp): 1266 code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' 1267 big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' 1268 1269 class RdAttr(SegOp): 1270 code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' 1271 big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' 1272 1273 class Rdsel(SegOp): 1274 code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' 1275 big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' 1276 1277 class Rdval(RegOp): 1278 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1279 super(Rdval, self).__init__(dest, src1, \ 1280 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1281 code = ''' 1282 DestReg = MiscRegSrc1; 1283 ''' 1284 1285 class Wrval(RegOp): 1286 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1287 super(Wrval, self).__init__(dest, src1, \ 1288 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1289 code = ''' 1290 MiscRegDest = SrcReg1; 1291 ''' 1292 1293 class Chks(RegOp): 1294 def __init__(self, dest, src1, src2=0, 1295 flags=None, dataSize="env.dataSize"): 1296 super(Chks, self).__init__(dest, 1297 src1, src2, flags, dataSize) 1298 code = ''' 1299 // The selector is in source 1 and can be at most 16 bits. 1300 SegSelector selector = DestReg; 1301 SegDescriptor desc = SrcReg1; 1302 HandyM5Reg m5reg = M5Reg; 1303 1304 switch (imm8) 1305 { 1306 case SegNoCheck: 1307 break; 1308 case SegCSCheck: 1309 // Make sure it's the right type 1310 if (desc.s == 0 || desc.type.codeOrData != 1) { 1311 fault = new GeneralProtection(0); 1312 } else if (m5reg.cpl != desc.dpl) { 1313 fault = new GeneralProtection(0); 1314 } 1315 break; 1316 case SegCallGateCheck: 1317 panic("CS checks for far calls/jumps through call gates" 1318 "not implemented.\\n"); 1319 break; 1320 case SegSoftIntGateCheck: 1321 // Check permissions. 1322 if (desc.dpl < m5reg.cpl) { 1323 fault = new GeneralProtection(selector); 1324 break; 1325 } 1326 // Fall through on purpose 1327 case SegIntGateCheck: 1328 // Make sure the gate's the right type. 1329 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 1330 ((desc.type & 0x6) != 0x6)) { 1331 fault = new GeneralProtection(0); 1332 } 1333 break; 1334 case SegSSCheck: 1335 if (selector.si || selector.ti) { 1336 if (!desc.p) { 1337 fault = new StackFault(selector); 1338 } else if (!(desc.s == 1 && desc.type.codeOrData == 0 && 1339 desc.type.w) || 1340 (desc.dpl != m5reg.cpl) || 1341 (selector.rpl != m5reg.cpl)) { 1342 fault = new GeneralProtection(selector); 1343 } 1344 } else if (m5reg.submode != SixtyFourBitMode || 1345 m5reg.cpl == 3) { 1346 fault = new GeneralProtection(selector); 1347 } 1348 break; 1349 case SegIretCheck: 1350 { 1351 if ((!selector.si && !selector.ti) || 1352 (selector.rpl < m5reg.cpl) || 1353 !(desc.s == 1 && desc.type.codeOrData == 1) || 1354 (!desc.type.c && desc.dpl != selector.rpl) || 1355 (desc.type.c && desc.dpl > selector.rpl)) { 1356 fault = new GeneralProtection(selector); 1357 } else if (!desc.p) { 1358 fault = new SegmentNotPresent(selector); 1359 } 1360 break; 1361 } 1362 case SegIntCSCheck: 1363 if (m5reg.mode == LongMode) { 1364 if (desc.l != 1 || desc.d != 0) { 1365 fault = new GeneralProtection(selector); 1366 } 1367 } else { 1368 panic("Interrupt CS checks not implemented " 1369 "in legacy mode.\\n"); 1370 } 1371 break; 1372 case SegTRCheck: 1373 if (!selector.si || selector.ti) { 1374 fault = new GeneralProtection(selector); 1375 } 1376 break; 1377 case SegTSSCheck: 1378 if (!desc.p) { 1379 fault = new SegmentNotPresent(selector); 1380 } else if (!(desc.type == 0x9 || 1381 (desc.type == 1 && 1382 m5reg.mode != LongMode))) { 1383 fault = new GeneralProtection(selector); 1384 } 1385 break; 1386 case SegInGDTCheck: 1387 if (selector.ti) { 1388 fault = new GeneralProtection(selector); 1389 } 1390 break; 1391 case SegLDTCheck: 1392 if (!desc.p) { 1393 fault = new SegmentNotPresent(selector); 1394 } else if (desc.type != 0x2) { 1395 fault = new GeneralProtection(selector); 1396 } 1397 break; 1398 default: 1399 panic("Undefined segment check type.\\n"); 1400 } 1401 ''' 1402 flag_code = ''' 1403 // Check for a NULL selector and set ZF,EZF appropriately. 1404 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 1405 if (!selector.si && !selector.ti) 1406 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 1407 ''' 1408 1409 class Wrdh(RegOp): 1410 code = ''' 1411 SegDescriptor desc = SrcReg1; 1412 1413 uint64_t target = bits(SrcReg2, 31, 0) << 32; 1414 switch(desc.type) { 1415 case LDT64: 1416 case AvailableTSS64: 1417 case BusyTSS64: 1418 replaceBits(target, 23, 0, desc.baseLow); 1419 replaceBits(target, 31, 24, desc.baseHigh); 1420 break; 1421 case CallGate64: 1422 case IntGate64: 1423 case TrapGate64: 1424 replaceBits(target, 15, 0, bits(desc, 15, 0)); 1425 replaceBits(target, 31, 16, bits(desc, 63, 48)); 1426 break; 1427 default: 1428 panic("Wrdh used with wrong descriptor type!\\n"); 1429 } 1430 DestReg = target; 1431 ''' 1432 1433 class Wrtsc(WrRegOp): 1434 code = ''' 1435 TscOp = psrc1; 1436 ''' 1437 1438 class Rdtsc(RdRegOp): 1439 code = ''' 1440 DestReg = TscOp; 1441 ''' 1442 1443 class Rdm5reg(RdRegOp): 1444 code = ''' 1445 DestReg = M5Reg; 1446 ''' 1447 1448 class Wrdl(RegOp): 1449 code = ''' 1450 SegDescriptor desc = SrcReg1; 1451 SegSelector selector = SrcReg2; 1452 if (selector.si || selector.ti) { 1453 if (!desc.p) 1454 panic("Segment not present.\\n"); 1455 SegAttr attr = 0; 1456 attr.dpl = desc.dpl; 1457 attr.unusable = 0; 1458 attr.defaultSize = desc.d; 1459 attr.longMode = desc.l; 1460 attr.avl = desc.avl; 1461 attr.granularity = desc.g; 1462 attr.present = desc.p; 1463 attr.system = desc.s; 1464 attr.type = desc.type; 1465 if (!desc.s) { 1466 // The expand down bit happens to be set for gates. 1467 if (desc.type.e) { 1468 panic("Gate descriptor encountered.\\n"); 1469 } 1470 attr.readable = 1; 1471 attr.writable = 1; 1472 attr.expandDown = 0; 1473 } else { 1474 if (desc.type.codeOrData) { 1475 attr.expandDown = 0; 1476 attr.readable = desc.type.r; 1477 attr.writable = 0; 1478 } else { 1479 attr.expandDown = desc.type.e; 1480 attr.readable = 1; 1481 attr.writable = desc.type.w; 1482 } 1483 } 1484 Addr base = desc.baseLow | (desc.baseHigh << 24); 1485 Addr limit = desc.limitLow | (desc.limitHigh << 16); 1486 if (desc.g) 1487 limit = (limit << 12) | mask(12); 1488 SegBaseDest = base; 1489 SegLimitDest = limit; 1490 SegAttrDest = attr; 1491 } else { 1492 SegBaseDest = SegBaseDest; 1493 SegLimitDest = SegLimitDest; 1494 SegAttrDest = SegAttrDest; 1495 } 1496 ''' 1497}}; 1498