regop.isa revision 7720:65d338a8dba4
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35// 36// Authors: Gabe Black 37 38////////////////////////////////////////////////////////////////////////// 39// 40// RegOp Microop templates 41// 42////////////////////////////////////////////////////////////////////////// 43 44def template MicroRegOpExecute {{ 45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 46 Trace::InstRecord *traceData) const 47 { 48 Fault fault = NoFault; 49 50 DPRINTF(X86, "The data size is %d\n", dataSize); 51 %(op_decl)s; 52 %(op_rd)s; 53 54 if(%(cond_check)s) 55 { 56 %(code)s; 57 %(flag_code)s; 58 } 59 else 60 { 61 %(else_code)s; 62 } 63 64 //Write the resulting state to the execution context 65 if(fault == NoFault) 66 { 67 %(op_wb)s; 68 } 69 return fault; 70 } 71}}; 72 73def template MicroRegOpImmExecute {{ 74 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 75 Trace::InstRecord *traceData) const 76 { 77 Fault fault = NoFault; 78 79 %(op_decl)s; 80 %(op_rd)s; 81 82 if(%(cond_check)s) 83 { 84 %(code)s; 85 %(flag_code)s; 86 } 87 else 88 { 89 %(else_code)s; 90 } 91 92 //Write the resulting state to the execution context 93 if(fault == NoFault) 94 { 95 %(op_wb)s; 96 } 97 return fault; 98 } 99}}; 100 101def template MicroRegOpDeclare {{ 102 class %(class_name)s : public %(base_class)s 103 { 104 public: 105 %(class_name)s(ExtMachInst _machInst, 106 const char * instMnem, uint64_t setFlags, 107 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 108 uint8_t _dataSize, uint16_t _ext); 109 110 %(BasicExecDeclare)s 111 }; 112}}; 113 114def template MicroRegOpImmDeclare {{ 115 116 class %(class_name)s : public %(base_class)s 117 { 118 public: 119 %(class_name)s(ExtMachInst _machInst, 120 const char * instMnem, uint64_t setFlags, 121 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 122 uint8_t _dataSize, uint16_t _ext); 123 124 %(BasicExecDeclare)s 125 }; 126}}; 127 128def template MicroRegOpConstructor {{ 129 inline %(class_name)s::%(class_name)s( 130 ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 131 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 132 uint8_t _dataSize, uint16_t _ext) : 133 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 134 _src1, _src2, _dest, _dataSize, _ext, 135 %(op_class)s) 136 { 137 %(constructor)s; 138 } 139}}; 140 141def template MicroRegOpImmConstructor {{ 142 inline %(class_name)s::%(class_name)s( 143 ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 144 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 145 uint8_t _dataSize, uint16_t _ext) : 146 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 147 _src1, _imm8, _dest, _dataSize, _ext, 148 %(op_class)s) 149 { 150 %(constructor)s; 151 } 152}}; 153 154output header {{ 155 void 156 divide(uint64_t dividend, uint64_t divisor, 157 uint64_t "ient, uint64_t &remainder); 158 159 enum SegmentSelectorCheck { 160 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 161 SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 162 SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 163 }; 164 165 enum LongModeDescriptorType { 166 LDT64 = 2, 167 AvailableTSS64 = 9, 168 BusyTSS64 = 0xb, 169 CallGate64 = 0xc, 170 IntGate64 = 0xe, 171 TrapGate64 = 0xf 172 }; 173}}; 174 175output decoder {{ 176 void 177 divide(uint64_t dividend, uint64_t divisor, 178 uint64_t "ient, uint64_t &remainder) 179 { 180 //Check for divide by zero. 181 assert(divisor != 0); 182 //If the divisor is bigger than the dividend, don't do anything. 183 if (divisor <= dividend) { 184 //Shift the divisor so it's msb lines up with the dividend. 185 int dividendMsb = findMsbSet(dividend); 186 int divisorMsb = findMsbSet(divisor); 187 int shift = dividendMsb - divisorMsb; 188 divisor <<= shift; 189 //Compute what we'll add to the quotient if the divisor isn't 190 //now larger than the dividend. 191 uint64_t quotientBit = 1; 192 quotientBit <<= shift; 193 //If we need to step back a bit (no pun intended) because the 194 //divisor got too to large, do that here. This is the "or two" 195 //part of one or two bit division. 196 if (divisor > dividend) { 197 quotientBit >>= 1; 198 divisor >>= 1; 199 } 200 //Decrement the remainder and increment the quotient. 201 quotient += quotientBit; 202 remainder -= divisor; 203 } 204 } 205}}; 206 207let {{ 208 # Make these empty strings so that concatenating onto 209 # them will always work. 210 header_output = "" 211 decoder_output = "" 212 exec_output = "" 213 214 immTemplates = ( 215 MicroRegOpImmDeclare, 216 MicroRegOpImmConstructor, 217 MicroRegOpImmExecute) 218 219 regTemplates = ( 220 MicroRegOpDeclare, 221 MicroRegOpConstructor, 222 MicroRegOpExecute) 223 224 class RegOpMeta(type): 225 def buildCppClasses(self, name, Name, suffix, \ 226 code, flag_code, cond_check, else_code): 227 228 # Globals to stick the output in 229 global header_output 230 global decoder_output 231 global exec_output 232 233 # Stick all the code together so it can be searched at once 234 allCode = "|".join((code, flag_code, cond_check, else_code)) 235 236 # If op2 is used anywhere, make register and immediate versions 237 # of this code. 238 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 239 match = matcher.search(allCode) 240 if match: 241 typeQual = "" 242 if match.group("typeQual"): 243 typeQual = match.group("typeQual") 244 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 245 self.buildCppClasses(name, Name, suffix, 246 matcher.sub(src2_name, code), 247 matcher.sub(src2_name, flag_code), 248 matcher.sub(src2_name, cond_check), 249 matcher.sub(src2_name, else_code)) 250 imm_name = "%simm8" % match.group("prefix") 251 self.buildCppClasses(name + "i", Name, suffix + "Imm", 252 matcher.sub(imm_name, code), 253 matcher.sub(imm_name, flag_code), 254 matcher.sub(imm_name, cond_check), 255 matcher.sub(imm_name, else_code)) 256 return 257 258 # If there's something optional to do with flags, generate 259 # a version without it and fix up this version to use it. 260 if flag_code != "" or cond_check != "true": 261 self.buildCppClasses(name, Name, suffix, 262 code, "", "true", else_code) 263 suffix = "Flags" + suffix 264 265 # If psrc1 or psrc2 is used, we need to actually insert code to 266 # compute it. 267 matcher = re.compile("(?<!\w)psrc1(?!\w)") 268 if matcher.search(allCode): 269 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 270 matcher = re.compile("(?<!\w)psrc2(?!\w)") 271 if matcher.search(allCode): 272 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 273 # Also make available versions which do sign extension 274 matcher = re.compile("(?<!\w)spsrc1(?!\w)") 275 if matcher.search(allCode): 276 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 277 matcher = re.compile("(?<!\w)spsrc2(?!\w)") 278 if matcher.search(allCode): 279 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 280 matcher = re.compile("(?<!\w)simm8(?!\w)") 281 if matcher.search(allCode): 282 code = "int8_t simm8 = imm8;" + code 283 284 base = "X86ISA::RegOp" 285 286 # If imm8 shows up in the code, use the immediate templates, if 287 # not, hopefully the register ones will be correct. 288 templates = regTemplates 289 matcher = re.compile("(?<!\w)s?imm8(?!\w)") 290 if matcher.search(allCode): 291 base += "Imm" 292 templates = immTemplates 293 294 # Get everything ready for the substitution 295 iop = InstObjParams(name, Name + suffix, base, 296 {"code" : code, 297 "flag_code" : flag_code, 298 "cond_check" : cond_check, 299 "else_code" : else_code}) 300 301 # Generate the actual code (finally!) 302 header_output += templates[0].subst(iop) 303 decoder_output += templates[1].subst(iop) 304 exec_output += templates[2].subst(iop) 305 306 307 def __new__(mcls, Name, bases, dict): 308 abstract = False 309 name = Name.lower() 310 if "abstract" in dict: 311 abstract = dict['abstract'] 312 del dict['abstract'] 313 314 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 315 if not abstract: 316 cls.className = Name 317 cls.base_mnemonic = name 318 code = cls.code 319 flag_code = cls.flag_code 320 cond_check = cls.cond_check 321 else_code = cls.else_code 322 323 # Set up the C++ classes 324 mcls.buildCppClasses(cls, name, Name, "", 325 code, flag_code, cond_check, else_code) 326 327 # Hook into the microassembler dict 328 global microopClasses 329 microopClasses[name] = cls 330 331 allCode = "|".join((code, flag_code, cond_check, else_code)) 332 333 # If op2 is used anywhere, make register and immediate versions 334 # of this code. 335 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 336 if matcher.search(allCode): 337 microopClasses[name + 'i'] = cls 338 return cls 339 340 341 class RegOp(X86Microop): 342 __metaclass__ = RegOpMeta 343 # This class itself doesn't act as a microop 344 abstract = True 345 346 # Default template parameter values 347 flag_code = "" 348 cond_check = "true" 349 else_code = ";" 350 351 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 352 self.dest = dest 353 self.src1 = src1 354 self.op2 = op2 355 self.flags = flags 356 self.dataSize = dataSize 357 if flags is None: 358 self.ext = 0 359 else: 360 if not isinstance(flags, (list, tuple)): 361 raise Exception, "flags must be a list or tuple of flags" 362 self.ext = " | ".join(flags) 363 self.className += "Flags" 364 365 def getAllocator(self, microFlags): 366 className = self.className 367 if self.mnemonic == self.base_mnemonic + 'i': 368 className += "Imm" 369 allocator = '''new %(class_name)s(machInst, macrocodeBlock, 370 %(flags)s, %(src1)s, %(op2)s, %(dest)s, 371 %(dataSize)s, %(ext)s)''' % { 372 "class_name" : className, 373 "flags" : self.microFlagsText(microFlags), 374 "src1" : self.src1, "op2" : self.op2, 375 "dest" : self.dest, 376 "dataSize" : self.dataSize, 377 "ext" : self.ext} 378 return allocator 379 380 class LogicRegOp(RegOp): 381 abstract = True 382 flag_code = ''' 383 //Don't have genFlags handle the OF or CF bits 384 uint64_t mask = CFBit | ECFBit | OFBit; 385 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 386 //If a logic microop wants to set these, it wants to set them to 0. 387 ccFlagBits &= ~(CFBit & ext); 388 ccFlagBits &= ~(ECFBit & ext); 389 ccFlagBits &= ~(OFBit & ext); 390 ''' 391 392 class FlagRegOp(RegOp): 393 abstract = True 394 flag_code = \ 395 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 396 397 class SubRegOp(RegOp): 398 abstract = True 399 flag_code = \ 400 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 401 402 class CondRegOp(RegOp): 403 abstract = True 404 cond_check = "checkCondition(ccFlagBits, ext)" 405 406 class RdRegOp(RegOp): 407 abstract = True 408 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 409 if not src1: 410 src1 = dest 411 super(RdRegOp, self).__init__(dest, src1, \ 412 "InstRegIndex(NUM_INTREGS)", None, dataSize) 413 414 class WrRegOp(RegOp): 415 abstract = True 416 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 417 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 418 src1, src2, flags, dataSize) 419 420 class Add(FlagRegOp): 421 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 422 423 class Or(LogicRegOp): 424 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 425 426 class Adc(FlagRegOp): 427 code = ''' 428 CCFlagBits flags = ccFlagBits; 429 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 430 ''' 431 432 class Sbb(SubRegOp): 433 code = ''' 434 CCFlagBits flags = ccFlagBits; 435 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 436 ''' 437 438 class And(LogicRegOp): 439 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 440 441 class Sub(SubRegOp): 442 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 443 444 class Xor(LogicRegOp): 445 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 446 447 class Mul1s(WrRegOp): 448 code = ''' 449 ProdLow = psrc1 * op2; 450 int halfSize = (dataSize * 8) / 2; 451 uint64_t shifter = (ULL(1) << halfSize); 452 uint64_t hiResult; 453 uint64_t psrc1_h = psrc1 / shifter; 454 uint64_t psrc1_l = psrc1 & mask(halfSize); 455 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 456 uint64_t psrc2_l = op2 & mask(halfSize); 457 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 458 ((psrc1_l * psrc2_l) / shifter)) /shifter) + 459 psrc1_h * psrc2_h; 460 if (bits(psrc1, dataSize * 8 - 1)) 461 hiResult -= op2; 462 if (bits(op2, dataSize * 8 - 1)) 463 hiResult -= psrc1; 464 ProdHi = hiResult; 465 ''' 466 flag_code = ''' 467 if ((-ProdHi & mask(dataSize * 8)) != 468 bits(ProdLow, dataSize * 8 - 1)) { 469 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 470 } else { 471 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 472 } 473 ''' 474 475 class Mul1u(WrRegOp): 476 code = ''' 477 ProdLow = psrc1 * op2; 478 int halfSize = (dataSize * 8) / 2; 479 uint64_t shifter = (ULL(1) << halfSize); 480 uint64_t psrc1_h = psrc1 / shifter; 481 uint64_t psrc1_l = psrc1 & mask(halfSize); 482 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 483 uint64_t psrc2_l = op2 & mask(halfSize); 484 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 485 ((psrc1_l * psrc2_l) / shifter)) / shifter) + 486 psrc1_h * psrc2_h; 487 ''' 488 flag_code = ''' 489 if (ProdHi) { 490 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 491 } else { 492 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 493 } 494 ''' 495 496 class Mulel(RdRegOp): 497 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 498 499 class Muleh(RdRegOp): 500 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 501 if not src1: 502 src1 = dest 503 super(RdRegOp, self).__init__(dest, src1, \ 504 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 505 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 506 507 # One or two bit divide 508 class Div1(WrRegOp): 509 code = ''' 510 //These are temporaries so that modifying them later won't make 511 //the ISA parser think they're also sources. 512 uint64_t quotient = 0; 513 uint64_t remainder = psrc1; 514 //Similarly, this is a temporary so changing it doesn't make it 515 //a source. 516 uint64_t divisor = op2; 517 //This is a temporary just for consistency and clarity. 518 uint64_t dividend = remainder; 519 //Do the division. 520 if (divisor == 0) { 521 fault = new DivideByZero; 522 } else { 523 divide(dividend, divisor, quotient, remainder); 524 //Record the final results. 525 Remainder = remainder; 526 Quotient = quotient; 527 Divisor = divisor; 528 } 529 ''' 530 531 # Step divide 532 class Div2(RegOp): 533 code = ''' 534 uint64_t dividend = Remainder; 535 uint64_t divisor = Divisor; 536 uint64_t quotient = Quotient; 537 uint64_t remainder = dividend; 538 int remaining = op2; 539 //If we overshot, do nothing. This lets us unrool division loops a 540 //little. 541 if (divisor == 0) { 542 fault = new DivideByZero; 543 } else if (remaining) { 544 if (divisor & (ULL(1) << 63)) { 545 while (remaining && !(dividend & (ULL(1) << 63))) { 546 dividend = (dividend << 1) | 547 bits(SrcReg1, remaining - 1); 548 quotient <<= 1; 549 remaining--; 550 } 551 if (dividend & (ULL(1) << 63)) { 552 bool highBit = false; 553 if (dividend < divisor && remaining) { 554 highBit = true; 555 dividend = (dividend << 1) | 556 bits(SrcReg1, remaining - 1); 557 quotient <<= 1; 558 remaining--; 559 } 560 if (highBit || divisor <= dividend) { 561 quotient++; 562 dividend -= divisor; 563 } 564 } 565 remainder = dividend; 566 } else { 567 //Shift in bits from the low order portion of the dividend 568 while (dividend < divisor && remaining) { 569 dividend = (dividend << 1) | 570 bits(SrcReg1, remaining - 1); 571 quotient <<= 1; 572 remaining--; 573 } 574 remainder = dividend; 575 //Do the division. 576 divide(dividend, divisor, quotient, remainder); 577 } 578 } 579 //Keep track of how many bits there are still to pull in. 580 DestReg = merge(DestReg, remaining, dataSize); 581 //Record the final results 582 Remainder = remainder; 583 Quotient = quotient; 584 ''' 585 flag_code = ''' 586 if (remaining == 0) 587 ccFlagBits = ccFlagBits | (ext & EZFBit); 588 else 589 ccFlagBits = ccFlagBits & ~(ext & EZFBit); 590 ''' 591 592 class Divq(RdRegOp): 593 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 594 595 class Divr(RdRegOp): 596 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 597 598 class Mov(CondRegOp): 599 code = 'DestReg = merge(SrcReg1, op2, dataSize)' 600 else_code = 'DestReg = DestReg;' 601 602 # Shift instructions 603 604 class Sll(RegOp): 605 code = ''' 606 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 607 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 608 ''' 609 flag_code = ''' 610 // If the shift amount is zero, no flags should be modified. 611 if (shiftAmt) { 612 //Zero out any flags we might modify. This way we only have to 613 //worry about setting them. 614 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 615 int CFBits = 0; 616 //Figure out if we -would- set the CF bits if requested. 617 if (shiftAmt <= dataSize * 8 && 618 bits(SrcReg1, dataSize * 8 - shiftAmt)) { 619 CFBits = 1; 620 } 621 //If some combination of the CF bits need to be set, set them. 622 if ((ext & (CFBit | ECFBit)) && CFBits) 623 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 624 //Figure out what the OF bit should be. 625 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 626 ccFlagBits = ccFlagBits | OFBit; 627 //Use the regular mechanisms to calculate the other flags. 628 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 629 DestReg, psrc1, op2); 630 } 631 ''' 632 633 class Srl(RegOp): 634 code = ''' 635 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 636 // Because what happens to the bits shift -in- on a right shift 637 // is not defined in the C/C++ standard, we have to mask them out 638 // to be sure they're zero. 639 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 640 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 641 ''' 642 flag_code = ''' 643 // If the shift amount is zero, no flags should be modified. 644 if (shiftAmt) { 645 //Zero out any flags we might modify. This way we only have to 646 //worry about setting them. 647 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 648 //If some combination of the CF bits need to be set, set them. 649 if ((ext & (CFBit | ECFBit)) && 650 shiftAmt <= dataSize * 8 && 651 bits(SrcReg1, shiftAmt - 1)) { 652 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 653 } 654 //Figure out what the OF bit should be. 655 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 656 ccFlagBits = ccFlagBits | OFBit; 657 //Use the regular mechanisms to calculate the other flags. 658 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 659 DestReg, psrc1, op2); 660 } 661 ''' 662 663 class Sra(RegOp): 664 code = ''' 665 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 666 // Because what happens to the bits shift -in- on a right shift 667 // is not defined in the C/C++ standard, we have to sign extend 668 // them manually to be sure. 669 uint64_t arithMask = (shiftAmt == 0) ? 0 : 670 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 671 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 672 ''' 673 flag_code = ''' 674 // If the shift amount is zero, no flags should be modified. 675 if (shiftAmt) { 676 //Zero out any flags we might modify. This way we only have to 677 //worry about setting them. 678 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 679 //If some combination of the CF bits need to be set, set them. 680 uint8_t effectiveShift = 681 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 682 if ((ext & (CFBit | ECFBit)) && 683 bits(SrcReg1, effectiveShift - 1)) { 684 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 685 } 686 //Use the regular mechanisms to calculate the other flags. 687 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 688 DestReg, psrc1, op2); 689 } 690 ''' 691 692 class Ror(RegOp): 693 code = ''' 694 uint8_t shiftAmt = 695 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 696 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 697 if(realShiftAmt) 698 { 699 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 700 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 701 DestReg = merge(DestReg, top | bottom, dataSize); 702 } 703 else 704 DestReg = merge(DestReg, DestReg, dataSize); 705 ''' 706 flag_code = ''' 707 // If the shift amount is zero, no flags should be modified. 708 if (shiftAmt) { 709 //Zero out any flags we might modify. This way we only have to 710 //worry about setting them. 711 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 712 //Find the most and second most significant bits of the result. 713 int msb = bits(DestReg, dataSize * 8 - 1); 714 int smsb = bits(DestReg, dataSize * 8 - 2); 715 //If some combination of the CF bits need to be set, set them. 716 if ((ext & (CFBit | ECFBit)) && msb) 717 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 718 //Figure out what the OF bit should be. 719 if ((ext & OFBit) && (msb ^ smsb)) 720 ccFlagBits = ccFlagBits | OFBit; 721 //Use the regular mechanisms to calculate the other flags. 722 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 723 DestReg, psrc1, op2); 724 } 725 ''' 726 727 class Rcr(RegOp): 728 code = ''' 729 uint8_t shiftAmt = 730 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 731 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 732 if(realShiftAmt) 733 { 734 CCFlagBits flags = ccFlagBits; 735 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 736 if (realShiftAmt > 1) 737 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 738 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 739 DestReg = merge(DestReg, top | bottom, dataSize); 740 } 741 else 742 DestReg = merge(DestReg, DestReg, dataSize); 743 ''' 744 flag_code = ''' 745 // If the shift amount is zero, no flags should be modified. 746 if (shiftAmt) { 747 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 748 //Zero out any flags we might modify. This way we only have to 749 //worry about setting them. 750 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 751 //Figure out what the OF bit should be. 752 if ((ext & OFBit) && (origCFBit ^ 753 bits(SrcReg1, dataSize * 8 - 1))) { 754 ccFlagBits = ccFlagBits | OFBit; 755 } 756 //If some combination of the CF bits need to be set, set them. 757 if ((ext & (CFBit | ECFBit)) && 758 (realShiftAmt == 0) ? origCFBit : 759 bits(SrcReg1, realShiftAmt - 1)) { 760 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 761 } 762 //Use the regular mechanisms to calculate the other flags. 763 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 764 DestReg, psrc1, op2); 765 } 766 ''' 767 768 class Rol(RegOp): 769 code = ''' 770 uint8_t shiftAmt = 771 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 772 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 773 if(realShiftAmt) 774 { 775 uint64_t top = psrc1 << realShiftAmt; 776 uint64_t bottom = 777 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 778 DestReg = merge(DestReg, top | bottom, dataSize); 779 } 780 else 781 DestReg = merge(DestReg, DestReg, dataSize); 782 ''' 783 flag_code = ''' 784 // If the shift amount is zero, no flags should be modified. 785 if (shiftAmt) { 786 //Zero out any flags we might modify. This way we only have to 787 //worry about setting them. 788 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 789 //The CF bits, if set, would be set to the lsb of the result. 790 int lsb = DestReg & 0x1; 791 int msb = bits(DestReg, dataSize * 8 - 1); 792 //If some combination of the CF bits need to be set, set them. 793 if ((ext & (CFBit | ECFBit)) && lsb) 794 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 795 //Figure out what the OF bit should be. 796 if ((ext & OFBit) && (msb ^ lsb)) 797 ccFlagBits = ccFlagBits | OFBit; 798 //Use the regular mechanisms to calculate the other flags. 799 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 800 DestReg, psrc1, op2); 801 } 802 ''' 803 804 class Rcl(RegOp): 805 code = ''' 806 uint8_t shiftAmt = 807 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 808 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 809 if(realShiftAmt) 810 { 811 CCFlagBits flags = ccFlagBits; 812 uint64_t top = psrc1 << realShiftAmt; 813 uint64_t bottom = flags.cf << (realShiftAmt - 1); 814 if(shiftAmt > 1) 815 bottom |= 816 bits(psrc1, dataSize * 8 - 1, 817 dataSize * 8 - realShiftAmt + 1); 818 DestReg = merge(DestReg, top | bottom, dataSize); 819 } 820 else 821 DestReg = merge(DestReg, DestReg, dataSize); 822 ''' 823 flag_code = ''' 824 // If the shift amount is zero, no flags should be modified. 825 if (shiftAmt) { 826 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 827 //Zero out any flags we might modify. This way we only have to 828 //worry about setting them. 829 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 830 int msb = bits(DestReg, dataSize * 8 - 1); 831 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 832 //If some combination of the CF bits need to be set, set them. 833 if ((ext & (CFBit | ECFBit)) && 834 (realShiftAmt == 0) ? origCFBit : CFBits) 835 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 836 //Figure out what the OF bit should be. 837 if ((ext & OFBit) && (msb ^ CFBits)) 838 ccFlagBits = ccFlagBits | OFBit; 839 //Use the regular mechanisms to calculate the other flags. 840 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 841 DestReg, psrc1, op2); 842 } 843 ''' 844 845 class Sld(RegOp): 846 code = ''' 847 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 848 uint8_t dataBits = dataSize * 8; 849 uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 850 uint64_t result; 851 if (realShiftAmt == 0) { 852 result = psrc1; 853 } else if (realShiftAmt < dataBits) { 854 result = (psrc1 << realShiftAmt) | 855 (DoubleBits >> (dataBits - realShiftAmt)); 856 } else { 857 result = (DoubleBits << (realShiftAmt - dataBits)) | 858 (psrc1 >> (2 * dataBits - realShiftAmt)); 859 } 860 DestReg = merge(DestReg, result, dataSize); 861 ''' 862 flag_code = ''' 863 // If the shift amount is zero, no flags should be modified. 864 if (shiftAmt) { 865 //Zero out any flags we might modify. This way we only have to 866 //worry about setting them. 867 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 868 int CFBits = 0; 869 //Figure out if we -would- set the CF bits if requested. 870 if ((realShiftAmt == 0 && 871 bits(DoubleBits, 0)) || 872 (realShiftAmt <= dataBits && 873 bits(SrcReg1, dataBits - realShiftAmt)) || 874 (realShiftAmt > dataBits && 875 bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 876 CFBits = 1; 877 } 878 //If some combination of the CF bits need to be set, set them. 879 if ((ext & (CFBit | ECFBit)) && CFBits) 880 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 881 //Figure out what the OF bit should be. 882 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 883 bits(result, dataBits - 1))) 884 ccFlagBits = ccFlagBits | OFBit; 885 //Use the regular mechanisms to calculate the other flags. 886 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 887 DestReg, psrc1, op2); 888 } 889 ''' 890 891 class Srd(RegOp): 892 code = ''' 893 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 894 uint8_t dataBits = dataSize * 8; 895 uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 896 uint64_t result; 897 if (realShiftAmt == 0) { 898 result = psrc1; 899 } else if (realShiftAmt < dataBits) { 900 // Because what happens to the bits shift -in- on a right 901 // shift is not defined in the C/C++ standard, we have to 902 // mask them out to be sure they're zero. 903 uint64_t logicalMask = mask(dataBits - realShiftAmt); 904 result = ((psrc1 >> realShiftAmt) & logicalMask) | 905 (DoubleBits << (dataBits - realShiftAmt)); 906 } else { 907 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 908 result = ((DoubleBits >> (realShiftAmt - dataBits)) & 909 logicalMask) | 910 (psrc1 << (2 * dataBits - realShiftAmt)); 911 } 912 DestReg = merge(DestReg, result, dataSize); 913 ''' 914 flag_code = ''' 915 // If the shift amount is zero, no flags should be modified. 916 if (shiftAmt) { 917 //Zero out any flags we might modify. This way we only have to 918 //worry about setting them. 919 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 920 int CFBits = 0; 921 //If some combination of the CF bits need to be set, set them. 922 if ((realShiftAmt == 0 && 923 bits(DoubleBits, dataBits - 1)) || 924 (realShiftAmt <= dataBits && 925 bits(SrcReg1, realShiftAmt - 1)) || 926 (realShiftAmt > dataBits && 927 bits(DoubleBits, realShiftAmt - dataBits - 1))) { 928 CFBits = 1; 929 } 930 //If some combination of the CF bits need to be set, set them. 931 if ((ext & (CFBit | ECFBit)) && CFBits) 932 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 933 //Figure out what the OF bit should be. 934 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 935 bits(result, dataBits - 1))) 936 ccFlagBits = ccFlagBits | OFBit; 937 //Use the regular mechanisms to calculate the other flags. 938 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 939 DestReg, psrc1, op2); 940 } 941 ''' 942 943 class Mdb(WrRegOp): 944 code = 'DoubleBits = psrc1 ^ op2;' 945 946 class Wrip(WrRegOp, CondRegOp): 947 code = ''' 948 X86ISA::PCState pc = PCS; 949 pc.npc(psrc1 + sop2 + CSBase); 950 PCS = pc; 951 ''' 952 else_code = "PCS = PCS;" 953 954 class Wruflags(WrRegOp): 955 code = 'ccFlagBits = psrc1 ^ op2' 956 957 class Wrflags(WrRegOp): 958 code = ''' 959 MiscReg newFlags = psrc1 ^ op2; 960 MiscReg userFlagMask = 0xDD5; 961 // Get only the user flags 962 ccFlagBits = newFlags & userFlagMask; 963 // Get everything else 964 nccFlagBits = newFlags & ~userFlagMask; 965 ''' 966 967 class Rdip(RdRegOp): 968 code = ''' 969 X86ISA::PCState pc = PCS; 970 DestReg = pc.npc() - CSBase; 971 ''' 972 973 class Ruflags(RdRegOp): 974 code = 'DestReg = ccFlagBits' 975 976 class Rflags(RdRegOp): 977 code = 'DestReg = ccFlagBits | nccFlagBits' 978 979 class Ruflag(RegOp): 980 code = ''' 981 int flag = bits(ccFlagBits, imm8); 982 DestReg = merge(DestReg, flag, dataSize); 983 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 984 (ccFlagBits & ~EZFBit); 985 ''' 986 def __init__(self, dest, imm, flags=None, \ 987 dataSize="env.dataSize"): 988 super(Ruflag, self).__init__(dest, \ 989 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 990 991 class Rflag(RegOp): 992 code = ''' 993 MiscReg flagMask = 0x3F7FDD5; 994 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 995 int flag = bits(flags, imm8); 996 DestReg = merge(DestReg, flag, dataSize); 997 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 998 (ccFlagBits & ~EZFBit); 999 ''' 1000 def __init__(self, dest, imm, flags=None, \ 1001 dataSize="env.dataSize"): 1002 super(Rflag, self).__init__(dest, \ 1003 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 1004 1005 class Sext(RegOp): 1006 code = ''' 1007 IntReg val = psrc1; 1008 // Mask the bit position so that it wraps. 1009 int bitPos = op2 & (dataSize * 8 - 1); 1010 int sign_bit = bits(val, bitPos, bitPos); 1011 uint64_t maskVal = mask(bitPos+1); 1012 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 1013 DestReg = merge(DestReg, val, dataSize); 1014 ''' 1015 flag_code = ''' 1016 if (!sign_bit) 1017 ccFlagBits = ccFlagBits & 1018 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1019 else 1020 ccFlagBits = ccFlagBits | 1021 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1022 ''' 1023 1024 class Zext(RegOp): 1025 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 1026 1027 class Rddr(RegOp): 1028 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1029 super(Rddr, self).__init__(dest, \ 1030 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1031 code = ''' 1032 CR4 cr4 = CR4Op; 1033 DR7 dr7 = DR7Op; 1034 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 1035 fault = new InvalidOpcode(); 1036 } else if (dr7.gd) { 1037 fault = new DebugException(); 1038 } else { 1039 DestReg = merge(DestReg, DebugSrc1, dataSize); 1040 } 1041 ''' 1042 1043 class Wrdr(RegOp): 1044 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1045 super(Wrdr, self).__init__(dest, \ 1046 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1047 code = ''' 1048 CR4 cr4 = CR4Op; 1049 DR7 dr7 = DR7Op; 1050 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 1051 fault = new InvalidOpcode(); 1052 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 1053 machInst.mode.mode == LongMode) { 1054 fault = new GeneralProtection(0); 1055 } else if (dr7.gd) { 1056 fault = new DebugException(); 1057 } else { 1058 DebugDest = psrc1; 1059 } 1060 ''' 1061 1062 class Rdcr(RegOp): 1063 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1064 super(Rdcr, self).__init__(dest, \ 1065 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1066 code = ''' 1067 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 1068 fault = new InvalidOpcode(); 1069 } else { 1070 DestReg = merge(DestReg, ControlSrc1, dataSize); 1071 } 1072 ''' 1073 1074 class Wrcr(RegOp): 1075 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1076 super(Wrcr, self).__init__(dest, \ 1077 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1078 code = ''' 1079 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 1080 fault = new InvalidOpcode(); 1081 } else { 1082 // There are *s in the line below so it doesn't confuse the 1083 // parser. They may be unnecessary. 1084 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 1085 MiscReg newVal = psrc1; 1086 1087 // Check for any modifications that would cause a fault. 1088 switch(dest) { 1089 case 0: 1090 { 1091 Efer efer = EferOp; 1092 CR0 cr0 = newVal; 1093 CR4 oldCr4 = CR4Op; 1094 if (bits(newVal, 63, 32) || 1095 (!cr0.pe && cr0.pg) || 1096 (!cr0.cd && cr0.nw) || 1097 (cr0.pg && efer.lme && !oldCr4.pae)) 1098 fault = new GeneralProtection(0); 1099 } 1100 break; 1101 case 2: 1102 break; 1103 case 3: 1104 break; 1105 case 4: 1106 { 1107 CR4 cr4 = newVal; 1108 // PAE can't be disabled in long mode. 1109 if (bits(newVal, 63, 11) || 1110 (machInst.mode.mode == LongMode && !cr4.pae)) 1111 fault = new GeneralProtection(0); 1112 } 1113 break; 1114 case 8: 1115 { 1116 if (bits(newVal, 63, 4)) 1117 fault = new GeneralProtection(0); 1118 } 1119 default: 1120 panic("Unrecognized control register %d.\\n", dest); 1121 } 1122 ControlDest = newVal; 1123 } 1124 ''' 1125 1126 # Microops for manipulating segmentation registers 1127 class SegOp(CondRegOp): 1128 abstract = True 1129 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1130 super(SegOp, self).__init__(dest, \ 1131 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1132 1133 class Wrbase(SegOp): 1134 code = ''' 1135 SegBaseDest = psrc1; 1136 ''' 1137 1138 class Wrlimit(SegOp): 1139 code = ''' 1140 SegLimitDest = psrc1; 1141 ''' 1142 1143 class Wrsel(SegOp): 1144 code = ''' 1145 SegSelDest = psrc1; 1146 ''' 1147 1148 class WrAttr(SegOp): 1149 code = ''' 1150 SegAttrDest = psrc1; 1151 ''' 1152 1153 class Rdbase(SegOp): 1154 code = ''' 1155 DestReg = merge(DestReg, SegBaseSrc1, dataSize); 1156 ''' 1157 1158 class Rdlimit(SegOp): 1159 code = ''' 1160 DestReg = merge(DestReg, SegLimitSrc1, dataSize); 1161 ''' 1162 1163 class RdAttr(SegOp): 1164 code = ''' 1165 DestReg = merge(DestReg, SegAttrSrc1, dataSize); 1166 ''' 1167 1168 class Rdsel(SegOp): 1169 code = ''' 1170 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1171 ''' 1172 1173 class Rdval(RegOp): 1174 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1175 super(Rdval, self).__init__(dest, src1, \ 1176 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1177 code = ''' 1178 DestReg = MiscRegSrc1; 1179 ''' 1180 1181 class Wrval(RegOp): 1182 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1183 super(Wrval, self).__init__(dest, src1, \ 1184 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1185 code = ''' 1186 MiscRegDest = SrcReg1; 1187 ''' 1188 1189 class Chks(RegOp): 1190 def __init__(self, dest, src1, src2=0, 1191 flags=None, dataSize="env.dataSize"): 1192 super(Chks, self).__init__(dest, 1193 src1, src2, flags, dataSize) 1194 code = ''' 1195 // The selector is in source 1 and can be at most 16 bits. 1196 SegSelector selector = DestReg; 1197 SegDescriptor desc = SrcReg1; 1198 HandyM5Reg m5reg = M5Reg; 1199 1200 switch (imm8) 1201 { 1202 case SegNoCheck: 1203 break; 1204 case SegCSCheck: 1205 // Make sure it's the right type 1206 if (desc.s == 0 || desc.type.codeOrData != 1) { 1207 fault = new GeneralProtection(0); 1208 } else if (m5reg.cpl != desc.dpl) { 1209 fault = new GeneralProtection(0); 1210 } 1211 break; 1212 case SegCallGateCheck: 1213 panic("CS checks for far calls/jumps through call gates" 1214 "not implemented.\\n"); 1215 break; 1216 case SegSoftIntGateCheck: 1217 // Check permissions. 1218 if (desc.dpl < m5reg.cpl) { 1219 fault = new GeneralProtection(selector); 1220 break; 1221 } 1222 // Fall through on purpose 1223 case SegIntGateCheck: 1224 // Make sure the gate's the right type. 1225 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 1226 ((desc.type & 0x6) != 0x6)) { 1227 fault = new GeneralProtection(0); 1228 } 1229 break; 1230 case SegSSCheck: 1231 if (selector.si || selector.ti) { 1232 if (!desc.p) { 1233 fault = new StackFault(selector); 1234 } 1235 } else { 1236 if ((m5reg.submode != SixtyFourBitMode || 1237 m5reg.cpl == 3) || 1238 !(desc.s == 1 && 1239 desc.type.codeOrData == 0 && desc.type.w) || 1240 (desc.dpl != m5reg.cpl) || 1241 (selector.rpl != m5reg.cpl)) { 1242 fault = new GeneralProtection(selector); 1243 } 1244 } 1245 break; 1246 case SegIretCheck: 1247 { 1248 if ((!selector.si && !selector.ti) || 1249 (selector.rpl < m5reg.cpl) || 1250 !(desc.s == 1 && desc.type.codeOrData == 1) || 1251 (!desc.type.c && desc.dpl != selector.rpl) || 1252 (desc.type.c && desc.dpl > selector.rpl)) { 1253 fault = new GeneralProtection(selector); 1254 } else if (!desc.p) { 1255 fault = new SegmentNotPresent(selector); 1256 } 1257 break; 1258 } 1259 case SegIntCSCheck: 1260 if (m5reg.mode == LongMode) { 1261 if (desc.l != 1 || desc.d != 0) { 1262 fault = new GeneralProtection(selector); 1263 } 1264 } else { 1265 panic("Interrupt CS checks not implemented " 1266 "in legacy mode.\\n"); 1267 } 1268 break; 1269 case SegTRCheck: 1270 if (!selector.si || selector.ti) { 1271 fault = new GeneralProtection(selector); 1272 } 1273 break; 1274 case SegTSSCheck: 1275 if (!desc.p) { 1276 fault = new SegmentNotPresent(selector); 1277 } else if (!(desc.type == 0x9 || 1278 (desc.type == 1 && 1279 m5reg.mode != LongMode))) { 1280 fault = new GeneralProtection(selector); 1281 } 1282 break; 1283 case SegInGDTCheck: 1284 if (selector.ti) { 1285 fault = new GeneralProtection(selector); 1286 } 1287 break; 1288 case SegLDTCheck: 1289 if (!desc.p) { 1290 fault = new SegmentNotPresent(selector); 1291 } else if (desc.type != 0x2) { 1292 fault = new GeneralProtection(selector); 1293 } 1294 break; 1295 default: 1296 panic("Undefined segment check type.\\n"); 1297 } 1298 ''' 1299 flag_code = ''' 1300 // Check for a NULL selector and set ZF,EZF appropriately. 1301 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 1302 if (!selector.si && !selector.ti) 1303 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 1304 ''' 1305 1306 class Wrdh(RegOp): 1307 code = ''' 1308 SegDescriptor desc = SrcReg1; 1309 1310 uint64_t target = bits(SrcReg2, 31, 0) << 32; 1311 switch(desc.type) { 1312 case LDT64: 1313 case AvailableTSS64: 1314 case BusyTSS64: 1315 replaceBits(target, 23, 0, desc.baseLow); 1316 replaceBits(target, 31, 24, desc.baseHigh); 1317 break; 1318 case CallGate64: 1319 case IntGate64: 1320 case TrapGate64: 1321 replaceBits(target, 15, 0, bits(desc, 15, 0)); 1322 replaceBits(target, 31, 16, bits(desc, 63, 48)); 1323 break; 1324 default: 1325 panic("Wrdh used with wrong descriptor type!\\n"); 1326 } 1327 DestReg = target; 1328 ''' 1329 1330 class Wrtsc(WrRegOp): 1331 code = ''' 1332 TscOp = psrc1; 1333 ''' 1334 1335 class Rdtsc(RdRegOp): 1336 code = ''' 1337 DestReg = TscOp; 1338 ''' 1339 1340 class Rdm5reg(RdRegOp): 1341 code = ''' 1342 DestReg = M5Reg; 1343 ''' 1344 1345 class Wrdl(RegOp): 1346 code = ''' 1347 SegDescriptor desc = SrcReg1; 1348 SegSelector selector = SrcReg2; 1349 if (selector.si || selector.ti) { 1350 if (!desc.p) 1351 panic("Segment not present.\\n"); 1352 SegAttr attr = 0; 1353 attr.dpl = desc.dpl; 1354 attr.unusable = 0; 1355 attr.defaultSize = desc.d; 1356 attr.longMode = desc.l; 1357 attr.avl = desc.avl; 1358 attr.granularity = desc.g; 1359 attr.present = desc.p; 1360 attr.system = desc.s; 1361 attr.type = desc.type; 1362 if (!desc.s) { 1363 // The expand down bit happens to be set for gates. 1364 if (desc.type.e) { 1365 panic("Gate descriptor encountered.\\n"); 1366 } 1367 attr.readable = 1; 1368 attr.writable = 1; 1369 attr.expandDown = 0; 1370 } else { 1371 if (desc.type.codeOrData) { 1372 attr.expandDown = 0; 1373 attr.readable = desc.type.r; 1374 attr.writable = 0; 1375 } else { 1376 attr.expandDown = desc.type.e; 1377 attr.readable = 1; 1378 attr.writable = desc.type.w; 1379 } 1380 } 1381 Addr base = desc.baseLow | (desc.baseHigh << 24); 1382 Addr limit = desc.limitLow | (desc.limitHigh << 16); 1383 if (desc.g) 1384 limit = (limit << 12) | mask(12); 1385 SegBaseDest = base; 1386 SegLimitDest = limit; 1387 SegAttrDest = attr; 1388 } else { 1389 SegBaseDest = SegBaseDest; 1390 SegLimitDest = SegLimitDest; 1391 SegAttrDest = SegAttrDest; 1392 } 1393 ''' 1394}}; 1395