regop.isa revision 7719
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38//////////////////////////////////////////////////////////////////////////
39//
40// RegOp Microop templates
41//
42//////////////////////////////////////////////////////////////////////////
43
44def template MicroRegOpExecute {{
45        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46                Trace::InstRecord *traceData) const
47        {
48            Fault fault = NoFault;
49
50            DPRINTF(X86, "The data size is %d\n", dataSize);
51            %(op_decl)s;
52            %(op_rd)s;
53
54            if(%(cond_check)s)
55            {
56                %(code)s;
57                %(flag_code)s;
58            }
59            else
60            {
61                %(else_code)s;
62            }
63
64            //Write the resulting state to the execution context
65            if(fault == NoFault)
66            {
67                %(op_wb)s;
68            }
69            return fault;
70        }
71}};
72
73def template MicroRegOpImmExecute {{
74        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
75                Trace::InstRecord *traceData) const
76        {
77            Fault fault = NoFault;
78
79            %(op_decl)s;
80            %(op_rd)s;
81
82            if(%(cond_check)s)
83            {
84                %(code)s;
85                %(flag_code)s;
86            }
87            else
88            {
89                %(else_code)s;
90            }
91
92            //Write the resulting state to the execution context
93            if(fault == NoFault)
94            {
95                %(op_wb)s;
96            }
97            return fault;
98        }
99}};
100
101def template MicroRegOpDeclare {{
102    class %(class_name)s : public %(base_class)s
103    {
104      public:
105        %(class_name)s(ExtMachInst _machInst,
106                const char * instMnem, uint64_t setFlags,
107                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
108                uint8_t _dataSize, uint16_t _ext);
109
110        %(BasicExecDeclare)s
111    };
112}};
113
114def template MicroRegOpImmDeclare {{
115
116    class %(class_name)s : public %(base_class)s
117    {
118      public:
119        %(class_name)s(ExtMachInst _machInst,
120                const char * instMnem, uint64_t setFlags,
121                InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
122                uint8_t _dataSize, uint16_t _ext);
123
124        %(BasicExecDeclare)s
125    };
126}};
127
128def template MicroRegOpConstructor {{
129    inline %(class_name)s::%(class_name)s(
130            ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
131            InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
132            uint8_t _dataSize, uint16_t _ext) :
133        %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
134                _src1, _src2, _dest, _dataSize, _ext,
135                %(op_class)s)
136    {
137        %(constructor)s;
138    }
139}};
140
141def template MicroRegOpImmConstructor {{
142    inline %(class_name)s::%(class_name)s(
143            ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
144            InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
145            uint8_t _dataSize, uint16_t _ext) :
146        %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
147                _src1, _imm8, _dest, _dataSize, _ext,
148                %(op_class)s)
149    {
150        %(constructor)s;
151    }
152}};
153
154output header {{
155    void
156    divide(uint64_t dividend, uint64_t divisor,
157            uint64_t &quotient, uint64_t &remainder);
158
159    enum SegmentSelectorCheck {
160      SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
161      SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
162      SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck
163    };
164
165    enum LongModeDescriptorType {
166        LDT64 = 2,
167        AvailableTSS64 = 9,
168        BusyTSS64 = 0xb,
169        CallGate64 = 0xc,
170        IntGate64 = 0xe,
171        TrapGate64 = 0xf
172    };
173}};
174
175output decoder {{
176    void
177    divide(uint64_t dividend, uint64_t divisor,
178            uint64_t &quotient, uint64_t &remainder)
179    {
180        //Check for divide by zero.
181        assert(divisor != 0);
182        //If the divisor is bigger than the dividend, don't do anything.
183        if (divisor <= dividend) {
184            //Shift the divisor so it's msb lines up with the dividend.
185            int dividendMsb = findMsbSet(dividend);
186            int divisorMsb = findMsbSet(divisor);
187            int shift = dividendMsb - divisorMsb;
188            divisor <<= shift;
189            //Compute what we'll add to the quotient if the divisor isn't
190            //now larger than the dividend.
191            uint64_t quotientBit = 1;
192            quotientBit <<= shift;
193            //If we need to step back a bit (no pun intended) because the
194            //divisor got too to large, do that here. This is the "or two"
195            //part of one or two bit division.
196            if (divisor > dividend) {
197                quotientBit >>= 1;
198                divisor >>= 1;
199            }
200            //Decrement the remainder and increment the quotient.
201            quotient += quotientBit;
202            remainder -= divisor;
203        }
204    }
205}};
206
207let {{
208    # Make these empty strings so that concatenating onto
209    # them will always work.
210    header_output = ""
211    decoder_output = ""
212    exec_output = ""
213
214    immTemplates = (
215            MicroRegOpImmDeclare,
216            MicroRegOpImmConstructor,
217            MicroRegOpImmExecute)
218
219    regTemplates = (
220            MicroRegOpDeclare,
221            MicroRegOpConstructor,
222            MicroRegOpExecute)
223
224    class RegOpMeta(type):
225        def buildCppClasses(self, name, Name, suffix, \
226                code, flag_code, cond_check, else_code):
227
228            # Globals to stick the output in
229            global header_output
230            global decoder_output
231            global exec_output
232
233            # Stick all the code together so it can be searched at once
234            allCode = "|".join((code, flag_code, cond_check, else_code))
235
236            # If op2 is used anywhere, make register and immediate versions
237            # of this code.
238            matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
239            match = matcher.search(allCode)
240            if match:
241                typeQual = ""
242                if match.group("typeQual"):
243                    typeQual = match.group("typeQual")
244                src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
245                self.buildCppClasses(name, Name, suffix,
246                        matcher.sub(src2_name, code),
247                        matcher.sub(src2_name, flag_code),
248                        matcher.sub(src2_name, cond_check),
249                        matcher.sub(src2_name, else_code))
250                imm_name = "%simm8" % match.group("prefix")
251                self.buildCppClasses(name + "i", Name, suffix + "Imm",
252                        matcher.sub(imm_name, code),
253                        matcher.sub(imm_name, flag_code),
254                        matcher.sub(imm_name, cond_check),
255                        matcher.sub(imm_name, else_code))
256                return
257
258            # If there's something optional to do with flags, generate
259            # a version without it and fix up this version to use it.
260            if flag_code != "" or cond_check != "true":
261                self.buildCppClasses(name, Name, suffix,
262                        code, "", "true", else_code)
263                suffix = "Flags" + suffix
264
265            # If psrc1 or psrc2 is used, we need to actually insert code to
266            # compute it.
267            matcher = re.compile("(?<!\w)psrc1(?!\w)")
268            if matcher.search(allCode):
269                code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
270            matcher = re.compile("(?<!\w)psrc2(?!\w)")
271            if matcher.search(allCode):
272                code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
273            # Also make available versions which do sign extension
274            matcher = re.compile("(?<!\w)spsrc1(?!\w)")
275            if matcher.search(allCode):
276                code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
277            matcher = re.compile("(?<!\w)spsrc2(?!\w)")
278            if matcher.search(allCode):
279                code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
280            matcher = re.compile("(?<!\w)simm8(?!\w)")
281            if matcher.search(allCode):
282                code = "int8_t simm8 = imm8;" + code
283
284            base = "X86ISA::RegOp"
285
286            # If imm8 shows up in the code, use the immediate templates, if
287            # not, hopefully the register ones will be correct.
288            templates = regTemplates
289            matcher = re.compile("(?<!\w)s?imm8(?!\w)")
290            if matcher.search(allCode):
291                base += "Imm"
292                templates = immTemplates
293
294            # Get everything ready for the substitution
295            iop = InstObjParams(name, Name + suffix, base,
296                    {"code" : code,
297                     "flag_code" : flag_code,
298                     "cond_check" : cond_check,
299                     "else_code" : else_code})
300
301            # Generate the actual code (finally!)
302            header_output += templates[0].subst(iop)
303            decoder_output += templates[1].subst(iop)
304            exec_output += templates[2].subst(iop)
305
306
307        def __new__(mcls, Name, bases, dict):
308            abstract = False
309            name = Name.lower()
310            if "abstract" in dict:
311                abstract = dict['abstract']
312                del dict['abstract']
313
314            cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
315            if not abstract:
316                cls.className = Name
317                cls.base_mnemonic = name
318                code = cls.code
319                flag_code = cls.flag_code
320                cond_check = cls.cond_check
321                else_code = cls.else_code
322
323                # Set up the C++ classes
324                mcls.buildCppClasses(cls, name, Name, "",
325                        code, flag_code, cond_check, else_code)
326
327                # Hook into the microassembler dict
328                global microopClasses
329                microopClasses[name] = cls
330
331                allCode = "|".join((code, flag_code, cond_check, else_code))
332
333                # If op2 is used anywhere, make register and immediate versions
334                # of this code.
335                matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
336                if matcher.search(allCode):
337                    microopClasses[name + 'i'] = cls
338            return cls
339
340
341    class RegOp(X86Microop):
342        __metaclass__ = RegOpMeta
343        # This class itself doesn't act as a microop
344        abstract = True
345
346        # Default template parameter values
347        flag_code = ""
348        cond_check = "true"
349        else_code = ";"
350
351        def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
352            self.dest = dest
353            self.src1 = src1
354            self.op2 = op2
355            self.flags = flags
356            self.dataSize = dataSize
357            if flags is None:
358                self.ext = 0
359            else:
360                if not isinstance(flags, (list, tuple)):
361                    raise Exception, "flags must be a list or tuple of flags"
362                self.ext = " | ".join(flags)
363                self.className += "Flags"
364
365        def getAllocator(self, microFlags):
366            className = self.className
367            if self.mnemonic == self.base_mnemonic + 'i':
368                className += "Imm"
369            allocator = '''new %(class_name)s(machInst, macrocodeBlock,
370                    %(flags)s, %(src1)s, %(op2)s, %(dest)s,
371                    %(dataSize)s, %(ext)s)''' % {
372                "class_name" : className,
373                "flags" : self.microFlagsText(microFlags),
374                "src1" : self.src1, "op2" : self.op2,
375                "dest" : self.dest,
376                "dataSize" : self.dataSize,
377                "ext" : self.ext}
378            return allocator
379
380    class LogicRegOp(RegOp):
381        abstract = True
382        flag_code = '''
383            //Don't have genFlags handle the OF or CF bits
384            uint64_t mask = CFBit | ECFBit | OFBit;
385            ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
386            //If a logic microop wants to set these, it wants to set them to 0.
387            ccFlagBits &= ~(CFBit & ext);
388            ccFlagBits &= ~(ECFBit & ext);
389            ccFlagBits &= ~(OFBit & ext);
390        '''
391
392    class FlagRegOp(RegOp):
393        abstract = True
394        flag_code = \
395            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
396
397    class SubRegOp(RegOp):
398        abstract = True
399        flag_code = \
400            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
401
402    class CondRegOp(RegOp):
403        abstract = True
404        cond_check = "checkCondition(ccFlagBits, ext)"
405
406    class RdRegOp(RegOp):
407        abstract = True
408        def __init__(self, dest, src1=None, dataSize="env.dataSize"):
409            if not src1:
410                src1 = dest
411            super(RdRegOp, self).__init__(dest, src1, \
412                    "InstRegIndex(NUM_INTREGS)", None, dataSize)
413
414    class WrRegOp(RegOp):
415        abstract = True
416        def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
417            super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
418                    src1, src2, flags, dataSize)
419
420    class Add(FlagRegOp):
421        code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
422
423    class Or(LogicRegOp):
424        code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
425
426    class Adc(FlagRegOp):
427        code = '''
428            CCFlagBits flags = ccFlagBits;
429            DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
430            '''
431
432    class Sbb(SubRegOp):
433        code = '''
434            CCFlagBits flags = ccFlagBits;
435            DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
436            '''
437
438    class And(LogicRegOp):
439        code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
440
441    class Sub(SubRegOp):
442        code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
443
444    class Xor(LogicRegOp):
445        code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
446
447    class Mul1s(WrRegOp):
448        code = '''
449            ProdLow = psrc1 * op2;
450            int halfSize = (dataSize * 8) / 2;
451            uint64_t shifter = (ULL(1) << halfSize);
452            uint64_t hiResult;
453            uint64_t psrc1_h = psrc1 / shifter;
454            uint64_t psrc1_l = psrc1 & mask(halfSize);
455            uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
456            uint64_t psrc2_l = op2 & mask(halfSize);
457            hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
458                        ((psrc1_l * psrc2_l) / shifter)) /shifter) +
459                       psrc1_h * psrc2_h;
460            if (bits(psrc1, dataSize * 8 - 1))
461                hiResult -= op2;
462            if (bits(op2, dataSize * 8 - 1))
463                hiResult -= psrc1;
464            ProdHi = hiResult;
465            '''
466        flag_code = '''
467            if ((-ProdHi & mask(dataSize * 8)) !=
468                    bits(ProdLow, dataSize * 8 - 1)) {
469                ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
470            } else {
471                ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
472            }
473        '''
474
475    class Mul1u(WrRegOp):
476        code = '''
477            ProdLow = psrc1 * op2;
478            int halfSize = (dataSize * 8) / 2;
479            uint64_t shifter = (ULL(1) << halfSize);
480            uint64_t psrc1_h = psrc1 / shifter;
481            uint64_t psrc1_l = psrc1 & mask(halfSize);
482            uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
483            uint64_t psrc2_l = op2 & mask(halfSize);
484            ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
485                      ((psrc1_l * psrc2_l) / shifter)) / shifter) +
486                     psrc1_h * psrc2_h;
487            '''
488        flag_code = '''
489            if (ProdHi) {
490                ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
491            } else {
492                ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
493            }
494        '''
495
496    class Mulel(RdRegOp):
497        code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
498
499    class Muleh(RdRegOp):
500        def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
501            if not src1:
502                src1 = dest
503            super(RdRegOp, self).__init__(dest, src1, \
504                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
505        code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
506
507    # One or two bit divide
508    class Div1(WrRegOp):
509        code = '''
510            //These are temporaries so that modifying them later won't make
511            //the ISA parser think they're also sources.
512            uint64_t quotient = 0;
513            uint64_t remainder = psrc1;
514            //Similarly, this is a temporary so changing it doesn't make it
515            //a source.
516            uint64_t divisor = op2;
517            //This is a temporary just for consistency and clarity.
518            uint64_t dividend = remainder;
519            //Do the division.
520            if (divisor == 0) {
521                fault = new DivideByZero;
522            } else {
523                divide(dividend, divisor, quotient, remainder);
524                //Record the final results.
525                Remainder = remainder;
526                Quotient = quotient;
527                Divisor = divisor;
528            }
529            '''
530
531    # Step divide
532    class Div2(RegOp):
533        code = '''
534            uint64_t dividend = Remainder;
535            uint64_t divisor = Divisor;
536            uint64_t quotient = Quotient;
537            uint64_t remainder = dividend;
538            int remaining = op2;
539            //If we overshot, do nothing. This lets us unrool division loops a
540            //little.
541            if (divisor == 0) {
542                fault = new DivideByZero;
543            } else if (remaining) {
544                if (divisor & (ULL(1) << 63)) {
545                    while (remaining && !(dividend & (ULL(1) << 63))) {
546                        dividend = (dividend << 1) |
547                            bits(SrcReg1, remaining - 1);
548                        quotient <<= 1;
549                        remaining--;
550                    }
551                    if (dividend & (ULL(1) << 63)) {
552                        bool highBit = false;
553                        if (dividend < divisor && remaining) {
554                            highBit = true;
555                            dividend = (dividend << 1) |
556                                bits(SrcReg1, remaining - 1);
557                            quotient <<= 1;
558                            remaining--;
559                        }
560                        if (highBit || divisor <= dividend) {
561                            quotient++;
562                            dividend -= divisor;
563                        }
564                    }
565                    remainder = dividend;
566                } else {
567                    //Shift in bits from the low order portion of the dividend
568                    while (dividend < divisor && remaining) {
569                        dividend = (dividend << 1) |
570                            bits(SrcReg1, remaining - 1);
571                        quotient <<= 1;
572                        remaining--;
573                    }
574                    remainder = dividend;
575                    //Do the division.
576                    divide(dividend, divisor, quotient, remainder);
577                }
578            }
579            //Keep track of how many bits there are still to pull in.
580            DestReg = merge(DestReg, remaining, dataSize);
581            //Record the final results
582            Remainder = remainder;
583            Quotient = quotient;
584        '''
585        flag_code = '''
586            if (remaining == 0)
587                ccFlagBits = ccFlagBits | (ext & EZFBit);
588            else
589                ccFlagBits = ccFlagBits & ~(ext & EZFBit);
590        '''
591
592    class Divq(RdRegOp):
593        code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
594
595    class Divr(RdRegOp):
596        code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
597
598    class Mov(CondRegOp):
599        code = 'DestReg = merge(SrcReg1, op2, dataSize)'
600        else_code = 'DestReg = DestReg;'
601
602    # Shift instructions
603
604    class Sll(RegOp):
605        code = '''
606            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
607            DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
608            '''
609        flag_code = '''
610            // If the shift amount is zero, no flags should be modified.
611            if (shiftAmt) {
612                //Zero out any flags we might modify. This way we only have to
613                //worry about setting them.
614                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
615                int CFBits = 0;
616                //Figure out if we -would- set the CF bits if requested.
617                if (shiftAmt <= dataSize * 8 &&
618                        bits(SrcReg1, dataSize * 8 - shiftAmt)) {
619                    CFBits = 1;
620                }
621                //If some combination of the CF bits need to be set, set them.
622                if ((ext & (CFBit | ECFBit)) && CFBits)
623                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
624                //Figure out what the OF bit should be.
625                if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
626                    ccFlagBits = ccFlagBits | OFBit;
627                //Use the regular mechanisms to calculate the other flags.
628                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
629                        DestReg, psrc1, op2);
630            }
631        '''
632
633    class Srl(RegOp):
634        code = '''
635            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
636            // Because what happens to the bits shift -in- on a right shift
637            // is not defined in the C/C++ standard, we have to mask them out
638            // to be sure they're zero.
639            uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
640            DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
641            '''
642        flag_code = '''
643            // If the shift amount is zero, no flags should be modified.
644            if (shiftAmt) {
645                //Zero out any flags we might modify. This way we only have to
646                //worry about setting them.
647                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
648                //If some combination of the CF bits need to be set, set them.
649                if ((ext & (CFBit | ECFBit)) && 
650                        shiftAmt <= dataSize * 8 &&
651                        bits(SrcReg1, shiftAmt - 1)) {
652                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
653                }
654                //Figure out what the OF bit should be.
655                if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
656                    ccFlagBits = ccFlagBits | OFBit;
657                //Use the regular mechanisms to calculate the other flags.
658                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
659                        DestReg, psrc1, op2);
660            }
661        '''
662
663    class Sra(RegOp):
664        code = '''
665            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
666            // Because what happens to the bits shift -in- on a right shift
667            // is not defined in the C/C++ standard, we have to sign extend
668            // them manually to be sure.
669            uint64_t arithMask = (shiftAmt == 0) ? 0 :
670                -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
671            DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
672            '''
673        flag_code = '''
674            // If the shift amount is zero, no flags should be modified.
675            if (shiftAmt) {
676                //Zero out any flags we might modify. This way we only have to
677                //worry about setting them.
678                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
679                //If some combination of the CF bits need to be set, set them.
680                uint8_t effectiveShift =
681                    (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
682                if ((ext & (CFBit | ECFBit)) &&
683                        bits(SrcReg1, effectiveShift - 1)) {
684                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
685                }
686                //Use the regular mechanisms to calculate the other flags.
687                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
688                        DestReg, psrc1, op2);
689            }
690        '''
691
692    class Ror(RegOp):
693        code = '''
694            uint8_t shiftAmt =
695                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
696            uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
697            if(realShiftAmt)
698            {
699                uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
700                uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
701                DestReg = merge(DestReg, top | bottom, dataSize);
702            }
703            else
704                DestReg = merge(DestReg, DestReg, dataSize);
705            '''
706        flag_code = '''
707            // If the shift amount is zero, no flags should be modified.
708            if (shiftAmt) {
709                //Zero out any flags we might modify. This way we only have to
710                //worry about setting them.
711                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
712                //Find the most and second most significant bits of the result.
713                int msb = bits(DestReg, dataSize * 8 - 1);
714                int smsb = bits(DestReg, dataSize * 8 - 2);
715                //If some combination of the CF bits need to be set, set them.
716                if ((ext & (CFBit | ECFBit)) && msb)
717                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
718                //Figure out what the OF bit should be.
719                if ((ext & OFBit) && (msb ^ smsb))
720                    ccFlagBits = ccFlagBits | OFBit;
721                //Use the regular mechanisms to calculate the other flags.
722                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
723                        DestReg, psrc1, op2);
724            }
725        '''
726
727    class Rcr(RegOp):
728        code = '''
729            uint8_t shiftAmt =
730                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
731            uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
732            if(realShiftAmt)
733            {
734                CCFlagBits flags = ccFlagBits;
735                uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
736                if (realShiftAmt > 1)
737                    top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
738                uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
739                DestReg = merge(DestReg, top | bottom, dataSize);
740            }
741            else
742                DestReg = merge(DestReg, DestReg, dataSize);
743            '''
744        flag_code = '''
745            // If the shift amount is zero, no flags should be modified.
746            if (shiftAmt) {
747                int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
748                //Zero out any flags we might modify. This way we only have to
749                //worry about setting them.
750                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
751                //Figure out what the OF bit should be.
752                if ((ext & OFBit) && (origCFBit ^
753                                      bits(SrcReg1, dataSize * 8 - 1))) {
754                    ccFlagBits = ccFlagBits | OFBit;
755                }
756                //If some combination of the CF bits need to be set, set them.
757                if ((ext & (CFBit | ECFBit)) &&
758                        (realShiftAmt == 0) ? origCFBit :
759                        bits(SrcReg1, realShiftAmt - 1)) {
760                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
761                }
762                //Use the regular mechanisms to calculate the other flags.
763                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
764                        DestReg, psrc1, op2);
765            }
766        '''
767
768    class Rol(RegOp):
769        code = '''
770            uint8_t shiftAmt =
771                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
772            uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
773            if(realShiftAmt)
774            {
775                uint64_t top = psrc1 << realShiftAmt;
776                uint64_t bottom =
777                    bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
778                DestReg = merge(DestReg, top | bottom, dataSize);
779            }
780            else
781                DestReg = merge(DestReg, DestReg, dataSize);
782            '''
783        flag_code = '''
784            // If the shift amount is zero, no flags should be modified.
785            if (shiftAmt) {
786                //Zero out any flags we might modify. This way we only have to
787                //worry about setting them.
788                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
789                //The CF bits, if set, would be set to the lsb of the result.
790                int lsb = DestReg & 0x1;
791                int msb = bits(DestReg, dataSize * 8 - 1);
792                //If some combination of the CF bits need to be set, set them.
793                if ((ext & (CFBit | ECFBit)) && lsb)
794                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
795                //Figure out what the OF bit should be.
796                if ((ext & OFBit) && (msb ^ lsb))
797                    ccFlagBits = ccFlagBits | OFBit;
798                //Use the regular mechanisms to calculate the other flags.
799                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
800                        DestReg, psrc1, op2);
801            }
802        '''
803
804    class Rcl(RegOp):
805        code = '''
806            uint8_t shiftAmt =
807                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
808            uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
809            if(realShiftAmt)
810            {
811                CCFlagBits flags = ccFlagBits;
812                uint64_t top = psrc1 << realShiftAmt;
813                uint64_t bottom = flags.cf << (realShiftAmt - 1);
814                if(shiftAmt > 1)
815                    bottom |=
816                        bits(psrc1, dataSize * 8 - 1,
817                                   dataSize * 8 - realShiftAmt + 1);
818                DestReg = merge(DestReg, top | bottom, dataSize);
819            }
820            else
821                DestReg = merge(DestReg, DestReg, dataSize);
822            '''
823        flag_code = '''
824            // If the shift amount is zero, no flags should be modified.
825            if (shiftAmt) {
826                int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
827                //Zero out any flags we might modify. This way we only have to
828                //worry about setting them.
829                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
830                int msb = bits(DestReg, dataSize * 8 - 1);
831                int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
832                //If some combination of the CF bits need to be set, set them.
833                if ((ext & (CFBit | ECFBit)) && 
834                        (realShiftAmt == 0) ? origCFBit : CFBits)
835                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
836                //Figure out what the OF bit should be.
837                if ((ext & OFBit) && (msb ^ CFBits))
838                    ccFlagBits = ccFlagBits | OFBit;
839                //Use the regular mechanisms to calculate the other flags.
840                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
841                        DestReg, psrc1, op2);
842            }
843        '''
844
845    class Sld(RegOp):
846        code = '''
847            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
848            uint8_t dataBits = dataSize * 8;
849            uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
850            uint64_t result;
851            if (realShiftAmt == 0) {
852                result = psrc1;
853            } else if (realShiftAmt < dataBits) {
854                result = (psrc1 << realShiftAmt) |
855                         (DoubleBits >> (dataBits - realShiftAmt));
856            } else {
857                result = (DoubleBits << (realShiftAmt - dataBits)) |
858                         (psrc1 >> (2 * dataBits - realShiftAmt));
859            }
860            DestReg = merge(DestReg, result, dataSize);
861            '''
862        flag_code = '''
863            // If the shift amount is zero, no flags should be modified.
864            if (shiftAmt) {
865                //Zero out any flags we might modify. This way we only have to
866                //worry about setting them.
867                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
868                int CFBits = 0;
869                //Figure out if we -would- set the CF bits if requested.
870                if ((realShiftAmt == 0 &&
871                        bits(DoubleBits, 0)) ||
872                    (realShiftAmt <= dataBits &&
873                     bits(SrcReg1, dataBits - realShiftAmt)) ||
874                    (realShiftAmt > dataBits &&
875                     bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
876                    CFBits = 1;
877                }
878                //If some combination of the CF bits need to be set, set them.
879                if ((ext & (CFBit | ECFBit)) && CFBits)
880                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
881                //Figure out what the OF bit should be.
882                if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
883                                      bits(result, dataBits - 1)))
884                    ccFlagBits = ccFlagBits | OFBit;
885                //Use the regular mechanisms to calculate the other flags.
886                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
887                        DestReg, psrc1, op2);
888            }
889        '''
890
891    class Srd(RegOp):
892        code = '''
893            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
894            uint8_t dataBits = dataSize * 8;
895            uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
896            uint64_t result;
897            if (realShiftAmt == 0) {
898                result = psrc1;
899            } else if (realShiftAmt < dataBits) {
900                // Because what happens to the bits shift -in- on a right
901                // shift is not defined in the C/C++ standard, we have to
902                // mask them out to be sure they're zero.
903                uint64_t logicalMask = mask(dataBits - realShiftAmt);
904                result = ((psrc1 >> realShiftAmt) & logicalMask) |
905                         (DoubleBits << (dataBits - realShiftAmt));
906            } else {
907                uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
908                result = ((DoubleBits >> (realShiftAmt - dataBits)) &
909                          logicalMask) |
910                         (psrc1 << (2 * dataBits - realShiftAmt));
911            }
912            DestReg = merge(DestReg, result, dataSize);
913            '''
914        flag_code = '''
915            // If the shift amount is zero, no flags should be modified.
916            if (shiftAmt) {
917                //Zero out any flags we might modify. This way we only have to
918                //worry about setting them.
919                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
920                int CFBits = 0;
921                //If some combination of the CF bits need to be set, set them.
922                if ((realShiftAmt == 0 &&
923                            bits(DoubleBits, dataBits - 1)) ||
924                        (realShiftAmt <= dataBits &&
925                         bits(SrcReg1, realShiftAmt - 1)) ||
926                        (realShiftAmt > dataBits &&
927                         bits(DoubleBits, realShiftAmt - dataBits - 1))) {
928                    CFBits = 1;
929                }
930                //If some combination of the CF bits need to be set, set them.
931                if ((ext & (CFBit | ECFBit)) && CFBits)
932                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
933                //Figure out what the OF bit should be.
934                if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
935                                      bits(result, dataBits - 1)))
936                    ccFlagBits = ccFlagBits | OFBit;
937                //Use the regular mechanisms to calculate the other flags.
938                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
939                        DestReg, psrc1, op2);
940            }
941        '''
942
943    class Mdb(WrRegOp):
944        code = 'DoubleBits = psrc1 ^ op2;'
945
946    class Wrip(WrRegOp, CondRegOp):
947        code = 'RIP = psrc1 + sop2 + CSBase'
948        else_code="RIP = RIP;"
949
950    class Wruflags(WrRegOp):
951        code = 'ccFlagBits = psrc1 ^ op2'
952
953    class Wrflags(WrRegOp):
954        code = '''
955            MiscReg newFlags = psrc1 ^ op2;
956            MiscReg userFlagMask = 0xDD5;
957            // Get only the user flags
958            ccFlagBits = newFlags & userFlagMask;
959            // Get everything else
960            nccFlagBits = newFlags & ~userFlagMask;
961        '''
962
963    class Rdip(RdRegOp):
964        code = 'DestReg = RIP - CSBase'
965
966    class Ruflags(RdRegOp):
967        code = 'DestReg = ccFlagBits'
968
969    class Rflags(RdRegOp):
970        code = 'DestReg = ccFlagBits | nccFlagBits'
971
972    class Ruflag(RegOp):
973        code = '''
974            int flag = bits(ccFlagBits, imm8);
975            DestReg = merge(DestReg, flag, dataSize);
976            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
977                                       (ccFlagBits & ~EZFBit);
978            '''
979        def __init__(self, dest, imm, flags=None, \
980                dataSize="env.dataSize"):
981            super(Ruflag, self).__init__(dest, \
982                    "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
983
984    class Rflag(RegOp):
985        code = '''
986            MiscReg flagMask = 0x3F7FDD5;
987            MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
988            int flag = bits(flags, imm8);
989            DestReg = merge(DestReg, flag, dataSize);
990            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
991                                       (ccFlagBits & ~EZFBit);
992            '''
993        def __init__(self, dest, imm, flags=None, \
994                dataSize="env.dataSize"):
995            super(Rflag, self).__init__(dest, \
996                    "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
997
998    class Sext(RegOp):
999        code = '''
1000            IntReg val = psrc1;
1001            // Mask the bit position so that it wraps.
1002            int bitPos = op2 & (dataSize * 8 - 1);
1003            int sign_bit = bits(val, bitPos, bitPos);
1004            uint64_t maskVal = mask(bitPos+1);
1005            val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1006            DestReg = merge(DestReg, val, dataSize);
1007            '''
1008        flag_code = '''
1009            if (!sign_bit)
1010                ccFlagBits = ccFlagBits &
1011                    ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1012            else
1013                ccFlagBits = ccFlagBits |
1014                    (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1015            '''
1016
1017    class Zext(RegOp):
1018        code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1019
1020    class Rddr(RegOp):
1021        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1022            super(Rddr, self).__init__(dest, \
1023                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1024        code = '''
1025            CR4 cr4 = CR4Op;
1026            DR7 dr7 = DR7Op;
1027            if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1028                fault = new InvalidOpcode();
1029            } else if (dr7.gd) {
1030                fault = new DebugException();
1031            } else {
1032                DestReg = merge(DestReg, DebugSrc1, dataSize);
1033            }
1034        '''
1035
1036    class Wrdr(RegOp):
1037        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1038            super(Wrdr, self).__init__(dest, \
1039                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1040        code = '''
1041            CR4 cr4 = CR4Op;
1042            DR7 dr7 = DR7Op;
1043            if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
1044                fault = new InvalidOpcode();
1045            } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
1046                    machInst.mode.mode == LongMode) {
1047                fault = new GeneralProtection(0);
1048            } else if (dr7.gd) {
1049                fault = new DebugException();
1050            } else {
1051                DebugDest = psrc1;
1052            }
1053        '''
1054
1055    class Rdcr(RegOp):
1056        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1057            super(Rdcr, self).__init__(dest, \
1058                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1059        code = '''
1060            if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1061                fault = new InvalidOpcode();
1062            } else {
1063                DestReg = merge(DestReg, ControlSrc1, dataSize);
1064            }
1065        '''
1066
1067    class Wrcr(RegOp):
1068        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1069            super(Wrcr, self).__init__(dest, \
1070                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1071        code = '''
1072            if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1073                fault = new InvalidOpcode();
1074            } else {
1075                // There are *s in the line below so it doesn't confuse the
1076                // parser. They may be unnecessary.
1077                //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
1078                MiscReg newVal = psrc1;
1079
1080                // Check for any modifications that would cause a fault.
1081                switch(dest) {
1082                  case 0:
1083                    {
1084                        Efer efer = EferOp;
1085                        CR0 cr0 = newVal;
1086                        CR4 oldCr4 = CR4Op;
1087                        if (bits(newVal, 63, 32) ||
1088                                (!cr0.pe && cr0.pg) ||
1089                                (!cr0.cd && cr0.nw) ||
1090                                (cr0.pg && efer.lme && !oldCr4.pae))
1091                            fault = new GeneralProtection(0);
1092                    }
1093                    break;
1094                  case 2:
1095                    break;
1096                  case 3:
1097                    break;
1098                  case 4:
1099                    {
1100                        CR4 cr4 = newVal;
1101                        // PAE can't be disabled in long mode.
1102                        if (bits(newVal, 63, 11) ||
1103                                (machInst.mode.mode == LongMode && !cr4.pae))
1104                            fault = new GeneralProtection(0);
1105                    }
1106                    break;
1107                  case 8:
1108                    {
1109                        if (bits(newVal, 63, 4))
1110                            fault = new GeneralProtection(0);
1111                    }
1112                  default:
1113                    panic("Unrecognized control register %d.\\n", dest);
1114                }
1115                ControlDest = newVal;
1116            }
1117            '''
1118
1119    # Microops for manipulating segmentation registers
1120    class SegOp(CondRegOp):
1121        abstract = True
1122        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1123            super(SegOp, self).__init__(dest, \
1124                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1125
1126    class Wrbase(SegOp):
1127        code = '''
1128            SegBaseDest = psrc1;
1129        '''
1130
1131    class Wrlimit(SegOp):
1132        code = '''
1133            SegLimitDest = psrc1;
1134        '''
1135
1136    class Wrsel(SegOp):
1137        code = '''
1138            SegSelDest = psrc1;
1139        '''
1140
1141    class WrAttr(SegOp):
1142        code = '''
1143            SegAttrDest = psrc1;
1144        '''
1145
1146    class Rdbase(SegOp):
1147        code = '''
1148            DestReg = merge(DestReg, SegBaseSrc1, dataSize);
1149        '''
1150
1151    class Rdlimit(SegOp):
1152        code = '''
1153            DestReg = merge(DestReg, SegLimitSrc1, dataSize);
1154        '''
1155
1156    class RdAttr(SegOp):
1157        code = '''
1158            DestReg = merge(DestReg, SegAttrSrc1, dataSize);
1159        '''
1160
1161    class Rdsel(SegOp):
1162        code = '''
1163            DestReg = merge(DestReg, SegSelSrc1, dataSize);
1164        '''
1165
1166    class Rdval(RegOp):
1167        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1168            super(Rdval, self).__init__(dest, src1, \
1169                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1170        code = '''
1171            DestReg = MiscRegSrc1;
1172        '''
1173
1174    class Wrval(RegOp):
1175        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1176            super(Wrval, self).__init__(dest, src1, \
1177                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1178        code = '''
1179            MiscRegDest = SrcReg1;
1180        '''
1181
1182    class Chks(RegOp):
1183        def __init__(self, dest, src1, src2=0,
1184                flags=None, dataSize="env.dataSize"):
1185            super(Chks, self).__init__(dest,
1186                    src1, src2, flags, dataSize)
1187        code = '''
1188            // The selector is in source 1 and can be at most 16 bits.
1189            SegSelector selector = DestReg;
1190            SegDescriptor desc = SrcReg1;
1191            HandyM5Reg m5reg = M5Reg;
1192
1193            switch (imm8)
1194            {
1195              case SegNoCheck:
1196                break;
1197              case SegCSCheck:
1198                // Make sure it's the right type
1199                if (desc.s == 0 || desc.type.codeOrData != 1) {
1200                    fault = new GeneralProtection(0);
1201                } else if (m5reg.cpl != desc.dpl) {
1202                    fault = new GeneralProtection(0);
1203                }
1204                break;
1205              case SegCallGateCheck:
1206                panic("CS checks for far calls/jumps through call gates"
1207                        "not implemented.\\n");
1208                break;
1209              case SegSoftIntGateCheck:
1210                // Check permissions.
1211                if (desc.dpl < m5reg.cpl) {
1212                    fault = new GeneralProtection(selector);
1213                    break;
1214                }
1215                // Fall through on purpose
1216              case SegIntGateCheck:
1217                // Make sure the gate's the right type.
1218                if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
1219                        ((desc.type & 0x6) != 0x6)) {
1220                    fault = new GeneralProtection(0);
1221                }
1222                break;
1223              case SegSSCheck:
1224                if (selector.si || selector.ti) {
1225                    if (!desc.p) {
1226                        fault = new StackFault(selector);
1227                    }
1228                } else {
1229                    if ((m5reg.submode != SixtyFourBitMode ||
1230                                m5reg.cpl == 3) ||
1231                            !(desc.s == 1 &&
1232                            desc.type.codeOrData == 0 && desc.type.w) ||
1233                            (desc.dpl != m5reg.cpl) ||
1234                            (selector.rpl != m5reg.cpl)) {
1235                        fault = new GeneralProtection(selector);
1236                    }
1237                }
1238                break;
1239              case SegIretCheck:
1240                {
1241                    if ((!selector.si && !selector.ti) ||
1242                            (selector.rpl < m5reg.cpl) ||
1243                            !(desc.s == 1 && desc.type.codeOrData == 1) ||
1244                            (!desc.type.c && desc.dpl != selector.rpl) ||
1245                            (desc.type.c && desc.dpl > selector.rpl)) {
1246                        fault = new GeneralProtection(selector);
1247                    } else if (!desc.p) {
1248                        fault = new SegmentNotPresent(selector);
1249                    }
1250                    break;
1251                }
1252              case SegIntCSCheck:
1253                if (m5reg.mode == LongMode) {
1254                    if (desc.l != 1 || desc.d != 0) {
1255                        fault = new GeneralProtection(selector);
1256                    }
1257                } else {
1258                    panic("Interrupt CS checks not implemented "
1259                            "in legacy mode.\\n");
1260                }
1261                break;
1262              case SegTRCheck:
1263                if (!selector.si || selector.ti) {
1264                    fault = new GeneralProtection(selector);
1265                }
1266                break;
1267              case SegTSSCheck:
1268                if (!desc.p) {
1269                    fault = new SegmentNotPresent(selector);
1270                } else if (!(desc.type == 0x9 ||
1271                        (desc.type == 1 &&
1272                         m5reg.mode != LongMode))) {
1273                    fault = new GeneralProtection(selector);
1274                }
1275                break;
1276              case SegInGDTCheck:
1277                if (selector.ti) {
1278                    fault = new GeneralProtection(selector);
1279                }
1280                break;
1281              case SegLDTCheck:
1282                if (!desc.p) {
1283                    fault = new SegmentNotPresent(selector);
1284                } else if (desc.type != 0x2) {
1285                    fault = new GeneralProtection(selector);
1286                }
1287                break;
1288              default:
1289                panic("Undefined segment check type.\\n");
1290            }
1291        '''
1292        flag_code = '''
1293            // Check for a NULL selector and set ZF,EZF appropriately.
1294            ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1295            if (!selector.si && !selector.ti)
1296                ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1297        '''
1298
1299    class Wrdh(RegOp):
1300        code = '''
1301            SegDescriptor desc = SrcReg1;
1302
1303            uint64_t target = bits(SrcReg2, 31, 0) << 32;
1304            switch(desc.type) {
1305              case LDT64:
1306              case AvailableTSS64:
1307              case BusyTSS64:
1308                replaceBits(target, 23, 0, desc.baseLow);
1309                replaceBits(target, 31, 24, desc.baseHigh);
1310                break;
1311              case CallGate64:
1312              case IntGate64:
1313              case TrapGate64:
1314                replaceBits(target, 15, 0, bits(desc, 15, 0));
1315                replaceBits(target, 31, 16, bits(desc, 63, 48));
1316                break;
1317              default:
1318                panic("Wrdh used with wrong descriptor type!\\n");
1319            }
1320            DestReg = target;
1321        '''
1322
1323    class Wrtsc(WrRegOp):
1324        code = '''
1325            TscOp = psrc1;
1326        '''
1327
1328    class Rdtsc(RdRegOp):
1329        code = '''
1330            DestReg = TscOp;
1331        '''
1332
1333    class Rdm5reg(RdRegOp):
1334        code = '''
1335            DestReg = M5Reg;
1336        '''
1337
1338    class Wrdl(RegOp):
1339        code = '''
1340            SegDescriptor desc = SrcReg1;
1341            SegSelector selector = SrcReg2;
1342            if (selector.si || selector.ti) {
1343                if (!desc.p)
1344                    panic("Segment not present.\\n");
1345                SegAttr attr = 0;
1346                attr.dpl = desc.dpl;
1347                attr.unusable = 0;
1348                attr.defaultSize = desc.d;
1349                attr.longMode = desc.l;
1350                attr.avl = desc.avl;
1351                attr.granularity = desc.g;
1352                attr.present = desc.p;
1353                attr.system = desc.s;
1354                attr.type = desc.type;
1355                if (!desc.s) {
1356                    // The expand down bit happens to be set for gates.
1357                    if (desc.type.e) {
1358                        panic("Gate descriptor encountered.\\n");
1359                    }
1360                    attr.readable = 1;
1361                    attr.writable = 1;
1362                    attr.expandDown = 0;
1363                } else {
1364                    if (desc.type.codeOrData) {
1365                        attr.expandDown = 0;
1366                        attr.readable = desc.type.r;
1367                        attr.writable = 0;
1368                    } else {
1369                        attr.expandDown = desc.type.e;
1370                        attr.readable = 1;
1371                        attr.writable = desc.type.w;
1372                    }
1373                }
1374                Addr base = desc.baseLow | (desc.baseHigh << 24);
1375                Addr limit = desc.limitLow | (desc.limitHigh << 16);
1376                if (desc.g)
1377                    limit = (limit << 12) | mask(12);
1378                SegBaseDest = base;
1379                SegLimitDest = limit;
1380                SegAttrDest = attr;
1381            } else {
1382                SegBaseDest = SegBaseDest;
1383                SegLimitDest = SegLimitDest;
1384                SegAttrDest = SegAttrDest;
1385            }
1386        '''
1387}};
1388