regop.isa revision 6479
12623SN/A// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 22623SN/A// All rights reserved. 32623SN/A// 42623SN/A// Redistribution and use of this software in source and binary forms, 52623SN/A// with or without modification, are permitted provided that the 62623SN/A// following conditions are met: 72623SN/A// 82623SN/A// The software must be used only for Non-Commercial Use which means any 92623SN/A// use which is NOT directed to receiving any direct monetary 102623SN/A// compensation for, or commercial advantage from such use. Illustrative 112623SN/A// examples of non-commercial use are academic research, personal study, 122623SN/A// teaching, education and corporate research & development. 132623SN/A// Illustrative examples of commercial use are distributing products for 142623SN/A// commercial advantage and providing services using the software for 152623SN/A// commercial advantage. 162623SN/A// 172623SN/A// If you wish to use this software or functionality therein that may be 182623SN/A// covered by patents for commercial use, please contact: 192623SN/A// Director of Intellectual Property Licensing 202623SN/A// Office of Strategy and Technology 212623SN/A// Hewlett-Packard Company 222623SN/A// 1501 Page Mill Road 232623SN/A// Palo Alto, California 94304 242623SN/A// 252623SN/A// Redistributions of source code must retain the above copyright notice, 262623SN/A// this list of conditions and the following disclaimer. Redistributions 272665Ssaidi@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 282665Ssaidi@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 292623SN/A// other materials provided with the distribution. Neither the name of 302623SN/A// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 313170Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 323806Ssaidi@eecs.umich.edu// this software without specific prior written permission. No right of 332623SN/A// sublicense is granted herewith. Derivatives of the software and 344040Ssaidi@eecs.umich.edu// output created using the software may be prepared, but only for 352623SN/A// Non-Commercial Uses. Derivatives of the software may be shared with 362623SN/A// others provided: (i) the others agree to abide by the list of 373348Sbinkertn@umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 383348Sbinkertn@umich.edu// and (ii) such Derivatives of the software include the above copyright 392623SN/A// notice to acknowledge the contribution from this software where 402901Ssaidi@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 412623SN/A// 422623SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 432623SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 442623SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 452623SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 462623SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 472623SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 482623SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 492623SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 502623SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 512623SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 522623SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 532623SN/A// 542623SN/A// Authors: Gabe Black 552623SN/A 562623SN/A////////////////////////////////////////////////////////////////////////// 572623SN/A// 582623SN/A// RegOp Microop templates 592623SN/A// 602623SN/A////////////////////////////////////////////////////////////////////////// 612623SN/A 622623SN/Adef template MicroRegOpExecute {{ 632856Srdreslin@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 642856Srdreslin@umich.edu Trace::InstRecord *traceData) const 652856Srdreslin@umich.edu { 662856Srdreslin@umich.edu Fault fault = NoFault; 672856Srdreslin@umich.edu 682856Srdreslin@umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 692856Srdreslin@umich.edu %(op_decl)s; 702856Srdreslin@umich.edu %(op_rd)s; 712856Srdreslin@umich.edu 722856Srdreslin@umich.edu if(%(cond_check)s) 732623SN/A { 742623SN/A %(code)s; 752623SN/A %(flag_code)s; 762623SN/A } 772623SN/A else 782623SN/A { 792680Sktlim@umich.edu %(else_code)s; 802680Sktlim@umich.edu } 812623SN/A 822623SN/A //Write the resulting state to the execution context 832680Sktlim@umich.edu if(fault == NoFault) 842623SN/A { 852623SN/A %(op_wb)s; 862623SN/A } 872623SN/A return fault; 882623SN/A } 893349Sbinkertn@umich.edu}}; 902623SN/A 913184Srdreslin@umich.edudef template MicroRegOpImmExecute {{ 922623SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 932623SN/A Trace::InstRecord *traceData) const 942623SN/A { 952623SN/A Fault fault = NoFault; 963349Sbinkertn@umich.edu 972623SN/A %(op_decl)s; 983310Srdreslin@umich.edu %(op_rd)s; 993649Srdreslin@umich.edu 1002623SN/A if(%(cond_check)s) 1012623SN/A { 1022623SN/A %(code)s; 1033349Sbinkertn@umich.edu %(flag_code)s; 1042623SN/A } 1053184Srdreslin@umich.edu else 1063184Srdreslin@umich.edu { 1072623SN/A %(else_code)s; 1082623SN/A } 1092623SN/A 1102623SN/A //Write the resulting state to the execution context 1112623SN/A if(fault == NoFault) 1123647Srdreslin@umich.edu { 1133647Srdreslin@umich.edu %(op_wb)s; 1143647Srdreslin@umich.edu } 1153647Srdreslin@umich.edu return fault; 1163647Srdreslin@umich.edu } 1172626SN/A}}; 1183647Srdreslin@umich.edu 1192626SN/Adef template MicroRegOpDeclare {{ 1202623SN/A class %(class_name)s : public %(base_class)s 1212623SN/A { 1222623SN/A protected: 1232657Ssaidi@eecs.umich.edu void buildMe(); 1242623SN/A 1252623SN/A public: 1262623SN/A %(class_name)s(ExtMachInst _machInst, 1272623SN/A const char * instMnem, 1282623SN/A bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1294192Sktlim@umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1304192Sktlim@umich.edu uint8_t _dataSize, uint16_t _ext); 1314192Sktlim@umich.edu 1324192Sktlim@umich.edu %(class_name)s(ExtMachInst _machInst, 1334192Sktlim@umich.edu const char * instMnem, 1344192Sktlim@umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1354192Sktlim@umich.edu uint8_t _dataSize, uint16_t _ext); 1364192Sktlim@umich.edu 1374192Sktlim@umich.edu %(BasicExecDeclare)s 1384192Sktlim@umich.edu }; 1394192Sktlim@umich.edu}}; 1402623SN/A 1412623SN/Adef template MicroRegOpImmDeclare {{ 1422623SN/A 1432623SN/A class %(class_name)s : public %(base_class)s 1442640Sstever@eecs.umich.edu { 1452623SN/A protected: 1462623SN/A void buildMe(); 1472623SN/A 1483647Srdreslin@umich.edu public: 1493647Srdreslin@umich.edu %(class_name)s(ExtMachInst _machInst, 1503647Srdreslin@umich.edu const char * instMnem, 1512663Sstever@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1523170Sstever@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 1534022Sstever@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1542623SN/A 1552623SN/A %(class_name)s(ExtMachInst _machInst, 1562663Sstever@eecs.umich.edu const char * instMnem, 1573170Sstever@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 1584022Sstever@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1592641Sstever@eecs.umich.edu 1602623SN/A %(BasicExecDeclare)s 1612623SN/A }; 1622663Sstever@eecs.umich.edu}}; 1633170Sstever@eecs.umich.edu 1644022Sstever@eecs.umich.edudef template MicroRegOpConstructor {{ 1652641Sstever@eecs.umich.edu 1664040Ssaidi@eecs.umich.edu inline void %(class_name)s::buildMe() 1674040Ssaidi@eecs.umich.edu { 1682623SN/A %(constructor)s; 1692623SN/A } 1702623SN/A 1712623SN/A inline %(class_name)s::%(class_name)s( 1722623SN/A ExtMachInst machInst, const char * instMnem, 1732623SN/A InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1742623SN/A uint8_t _dataSize, uint16_t _ext) : 1752623SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1762623SN/A false, false, false, false, 1772623SN/A _src1, _src2, _dest, _dataSize, _ext, 1782915Sktlim@umich.edu %(op_class)s) 1792915Sktlim@umich.edu { 1803177Shsul@eecs.umich.edu buildMe(); 1813177Shsul@eecs.umich.edu } 1823145Shsul@eecs.umich.edu 1832623SN/A inline %(class_name)s::%(class_name)s( 1842623SN/A ExtMachInst machInst, const char * instMnem, 1852623SN/A bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1862623SN/A InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1872623SN/A uint8_t _dataSize, uint16_t _ext) : 1882623SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1892623SN/A isMicro, isDelayed, isFirst, isLast, 1902915Sktlim@umich.edu _src1, _src2, _dest, _dataSize, _ext, 1912915Sktlim@umich.edu %(op_class)s) 1923177Shsul@eecs.umich.edu { 1933145Shsul@eecs.umich.edu buildMe(); 1942915Sktlim@umich.edu } 1952915Sktlim@umich.edu}}; 1962915Sktlim@umich.edu 1972915Sktlim@umich.edudef template MicroRegOpImmConstructor {{ 1982915Sktlim@umich.edu 1992915Sktlim@umich.edu inline void %(class_name)s::buildMe() 2003324Shsul@eecs.umich.edu { 2013201Shsul@eecs.umich.edu %(constructor)s; 2023324Shsul@eecs.umich.edu } 2033324Shsul@eecs.umich.edu 2043324Shsul@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2053431Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2063495Sktlim@umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 2073431Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2083324Shsul@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2092915Sktlim@umich.edu false, false, false, false, 2102623SN/A _src1, _imm8, _dest, _dataSize, _ext, 2112623SN/A %(op_class)s) 2122623SN/A { 2132798Sktlim@umich.edu buildMe(); 2142623SN/A } 2152798Sktlim@umich.edu 2162798Sktlim@umich.edu inline %(class_name)s::%(class_name)s( 2172623SN/A ExtMachInst machInst, const char * instMnem, 2182798Sktlim@umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2192623SN/A InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 2202623SN/A uint8_t _dataSize, uint16_t _ext) : 2212623SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2222623SN/A isMicro, isDelayed, isFirst, isLast, 2232623SN/A _src1, _imm8, _dest, _dataSize, _ext, 2242623SN/A %(op_class)s) 2254192Sktlim@umich.edu { 2262623SN/A buildMe(); 2272623SN/A } 2282623SN/A}}; 2292680Sktlim@umich.edu 2302623SN/Aoutput header {{ 2312680Sktlim@umich.edu void 2322680Sktlim@umich.edu divide(uint64_t dividend, uint64_t divisor, 2332680Sktlim@umich.edu uint64_t "ient, uint64_t &remainder); 2342623SN/A 2353495Sktlim@umich.edu enum SegmentSelectorCheck { 2362623SN/A SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 2372623SN/A SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 2382623SN/A SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 2393512Sktlim@umich.edu }; 2403512Sktlim@umich.edu 2413512Sktlim@umich.edu enum LongModeDescriptorType { 2422623SN/A LDT64 = 2, 2432623SN/A AvailableTSS64 = 9, 2442623SN/A BusyTSS64 = 0xb, 2452623SN/A CallGate64 = 0xc, 2462623SN/A IntGate64 = 0xe, 2472623SN/A TrapGate64 = 0xf 2482623SN/A }; 2492683Sktlim@umich.edu}}; 2502623SN/A 2512623SN/Aoutput decoder {{ 2522623SN/A void 2532623SN/A divide(uint64_t dividend, uint64_t divisor, 2542623SN/A uint64_t "ient, uint64_t &remainder) 2553686Sktlim@umich.edu { 2563430Sgblack@eecs.umich.edu //Check for divide by zero. 2573495Sktlim@umich.edu if (divisor == 0) 2582623SN/A panic("Divide by zero!\\n"); 2592623SN/A //If the divisor is bigger than the dividend, don't do anything. 2602623SN/A if (divisor <= dividend) { 2612623SN/A //Shift the divisor so it's msb lines up with the dividend. 2622623SN/A int dividendMsb = findMsbSet(dividend); 2632623SN/A int divisorMsb = findMsbSet(divisor); 2642623SN/A int shift = dividendMsb - divisorMsb; 2652623SN/A divisor <<= shift; 2662683Sktlim@umich.edu //Compute what we'll add to the quotient if the divisor isn't 2672623SN/A //now larger than the dividend. 2682623SN/A uint64_t quotientBit = 1; 2692626SN/A quotientBit <<= shift; 2702626SN/A //If we need to step back a bit (no pun intended) because the 2712626SN/A //divisor got too to large, do that here. This is the "or two" 2722626SN/A //part of one or two bit division. 2732626SN/A if (divisor > dividend) { 2742623SN/A quotientBit >>= 1; 2752623SN/A divisor >>= 1; 2762623SN/A } 2772623SN/A //Decrement the remainder and increment the quotient. 2782623SN/A quotient += quotientBit; 2792623SN/A remainder -= divisor; 2802623SN/A } 2812623SN/A } 2822623SN/A}}; 2832623SN/A 2843169Sstever@eecs.umich.edulet {{ 2853169Sstever@eecs.umich.edu # Make these empty strings so that concatenating onto 2863349Sbinkertn@umich.edu # them will always work. 2873169Sstever@eecs.umich.edu header_output = "" 2883169Sstever@eecs.umich.edu decoder_output = "" 2892623SN/A exec_output = "" 2902623SN/A 2912623SN/A immTemplates = ( 2922623SN/A MicroRegOpImmDeclare, 2932623SN/A MicroRegOpImmConstructor, 2942623SN/A MicroRegOpImmExecute) 2953169Sstever@eecs.umich.edu 2962623SN/A regTemplates = ( 2972623SN/A MicroRegOpDeclare, 2982623SN/A MicroRegOpConstructor, 2993169Sstever@eecs.umich.edu MicroRegOpExecute) 3002623SN/A 3013806Ssaidi@eecs.umich.edu class RegOpMeta(type): 3023806Ssaidi@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 3033806Ssaidi@eecs.umich.edu code, flag_code, cond_check, else_code): 3043806Ssaidi@eecs.umich.edu 3052623SN/A # Globals to stick the output in 3063814Ssaidi@eecs.umich.edu global header_output 3073814Ssaidi@eecs.umich.edu global decoder_output 3083814Ssaidi@eecs.umich.edu global exec_output 3093814Ssaidi@eecs.umich.edu 3103814Ssaidi@eecs.umich.edu # Stick all the code together so it can be searched at once 3113169Sstever@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3123170Sstever@eecs.umich.edu 3133170Sstever@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3143170Sstever@eecs.umich.edu # of this code. 3153170Sstever@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 3162623SN/A match = matcher.search(allCode) 3172623SN/A if match: 3182623SN/A typeQual = "" 3193172Sstever@eecs.umich.edu if match.group("typeQual"): 3202623SN/A typeQual = match.group("typeQual") 3212623SN/A src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3222623SN/A self.buildCppClasses(name, Name, suffix, 3232623SN/A matcher.sub(src2_name, code), 3242623SN/A matcher.sub(src2_name, flag_code), 3252623SN/A matcher.sub(src2_name, cond_check), 3262623SN/A matcher.sub(src2_name, else_code)) 3272623SN/A self.buildCppClasses(name + "i", Name, suffix + "Imm", 3282623SN/A matcher.sub("imm8", code), 3294115Ssaidi@eecs.umich.edu matcher.sub("imm8", flag_code), 3304115Ssaidi@eecs.umich.edu matcher.sub("imm8", cond_check), 3314115Ssaidi@eecs.umich.edu matcher.sub("imm8", else_code)) 3324115Ssaidi@eecs.umich.edu return 3334040Ssaidi@eecs.umich.edu 3344040Ssaidi@eecs.umich.edu # If there's something optional to do with flags, generate 3354040Ssaidi@eecs.umich.edu # a version without it and fix up this version to use it. 3364040Ssaidi@eecs.umich.edu if flag_code != "" or cond_check != "true": 3372623SN/A self.buildCppClasses(name, Name, suffix, 3382623SN/A code, "", "true", else_code) 3392623SN/A suffix = "Flags" + suffix 3402623SN/A 3412623SN/A # If psrc1 or psrc2 is used, we need to actually insert code to 3422623SN/A # compute it. 3432623SN/A matcher = re.compile("(?<!\w)psrc1(?!\w)") 3442623SN/A if matcher.search(allCode): 3452623SN/A code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3462623SN/A matcher = re.compile("(?<!\w)psrc2(?!\w)") 3472623SN/A if matcher.search(allCode): 3482623SN/A code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3492623SN/A # Also make available versions which do sign extension 3502623SN/A matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3512623SN/A if matcher.search(allCode): 3522623SN/A code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3532623SN/A matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3542623SN/A if matcher.search(allCode): 3552623SN/A code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3562623SN/A 3572623SN/A base = "X86ISA::RegOp" 3582623SN/A 3592623SN/A # If imm8 shows up in the code, use the immediate templates, if 3602623SN/A # not, hopefully the register ones will be correct. 3612623SN/A templates = regTemplates 3622623SN/A matcher = re.compile("(?<!\w)imm8(?!\w)") 3632623SN/A if matcher.search(allCode): 3642623SN/A base += "Imm" 3652623SN/A templates = immTemplates 3662623SN/A 3672623SN/A # Get everything ready for the substitution 3682623SN/A iop = InstObjParams(name, Name + suffix, base, 3692623SN/A {"code" : code, 3702623SN/A "flag_code" : flag_code, 3712623SN/A "cond_check" : cond_check, 3722623SN/A "else_code" : else_code}) 3732623SN/A 3742623SN/A # Generate the actual code (finally!) 3752623SN/A header_output += templates[0].subst(iop) 3762623SN/A decoder_output += templates[1].subst(iop) 3772623SN/A exec_output += templates[2].subst(iop) 3782623SN/A 3792623SN/A 3803169Sstever@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3813169Sstever@eecs.umich.edu abstract = False 3824040Ssaidi@eecs.umich.edu name = Name.lower() 3833169Sstever@eecs.umich.edu if "abstract" in dict: 3843169Sstever@eecs.umich.edu abstract = dict['abstract'] 3852623SN/A del dict['abstract'] 3864040Ssaidi@eecs.umich.edu 3874040Ssaidi@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3884040Ssaidi@eecs.umich.edu if not abstract: 3894040Ssaidi@eecs.umich.edu cls.className = Name 3904040Ssaidi@eecs.umich.edu cls.base_mnemonic = name 3912623SN/A code = cls.code 3922623SN/A flag_code = cls.flag_code 3932623SN/A cond_check = cls.cond_check 3942623SN/A else_code = cls.else_code 3952623SN/A 3963169Sstever@eecs.umich.edu # Set up the C++ classes 3972623SN/A mcls.buildCppClasses(cls, name, Name, "", 3982623SN/A code, flag_code, cond_check, else_code) 3992623SN/A 4003170Sstever@eecs.umich.edu # Hook into the microassembler dict 4012623SN/A global microopClasses 4023170Sstever@eecs.umich.edu microopClasses[name] = cls 4033170Sstever@eecs.umich.edu 4043170Sstever@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 4054040Ssaidi@eecs.umich.edu 4064040Ssaidi@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 4074040Ssaidi@eecs.umich.edu # of this code. 4084040Ssaidi@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 4094040Ssaidi@eecs.umich.edu if matcher.search(allCode): 4102623SN/A microopClasses[name + 'i'] = cls 4113170Sstever@eecs.umich.edu return cls 4123170Sstever@eecs.umich.edu 4133170Sstever@eecs.umich.edu 4142631SN/A class RegOp(X86Microop): 4153806Ssaidi@eecs.umich.edu __metaclass__ = RegOpMeta 4163806Ssaidi@eecs.umich.edu # This class itself doesn't act as a microop 4173806Ssaidi@eecs.umich.edu abstract = True 4183806Ssaidi@eecs.umich.edu 4193806Ssaidi@eecs.umich.edu # Default template parameter values 4203806Ssaidi@eecs.umich.edu flag_code = "" 4213170Sstever@eecs.umich.edu cond_check = "true" 4223170Sstever@eecs.umich.edu else_code = ";" 4233814Ssaidi@eecs.umich.edu 4243814Ssaidi@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4253814Ssaidi@eecs.umich.edu self.dest = dest 4263814Ssaidi@eecs.umich.edu self.src1 = src1 4273814Ssaidi@eecs.umich.edu self.op2 = op2 4283170Sstever@eecs.umich.edu self.flags = flags 4293170Sstever@eecs.umich.edu self.dataSize = dataSize 4304040Ssaidi@eecs.umich.edu if flags is None: 4314040Ssaidi@eecs.umich.edu self.ext = 0 4324040Ssaidi@eecs.umich.edu else: 4334050Ssaidi@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4344052Ssaidi@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4352631SN/A self.ext = " | ".join(flags) 4362623SN/A self.className += "Flags" 4372623SN/A 4382623SN/A def getAllocator(self, *microFlags): 4393172Sstever@eecs.umich.edu className = self.className 4402623SN/A if self.mnemonic == self.base_mnemonic + 'i': 4412623SN/A className += "Imm" 4422623SN/A allocator = '''new %(class_name)s(machInst, macrocodeBlock 4432623SN/A %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4442623SN/A %(dataSize)s, %(ext)s)''' % { 4452623SN/A "class_name" : className, 4462623SN/A "flags" : self.microFlagsText(microFlags), 4472623SN/A "src1" : self.src1, "op2" : self.op2, 4482623SN/A "dest" : self.dest, 4494224Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4504224Sgblack@eecs.umich.edu "ext" : self.ext} 4514224Sgblack@eecs.umich.edu return allocator 4524224Sgblack@eecs.umich.edu 4534224Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4544224Sgblack@eecs.umich.edu abstract = True 4554224Sgblack@eecs.umich.edu flag_code = ''' 4564224Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4574224Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4584224Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4594224Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4602623SN/A ccFlagBits &= ~(CFBit & ext); 4612623SN/A ccFlagBits &= ~(ECFBit & ext); 4622623SN/A ccFlagBits &= ~(OFBit & ext); 4632623SN/A ''' 4642623SN/A 4652623SN/A class FlagRegOp(RegOp): 4662623SN/A abstract = True 4672623SN/A flag_code = \ 4682623SN/A "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4692623SN/A 4702623SN/A class SubRegOp(RegOp): 4712623SN/A abstract = True 4722623SN/A flag_code = \ 4732623SN/A "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4742623SN/A 4752623SN/A class CondRegOp(RegOp): 4762623SN/A abstract = True 4772623SN/A cond_check = "checkCondition(ccFlagBits, ext)" 4782623SN/A 4792623SN/A class RdRegOp(RegOp): 4802623SN/A abstract = True 4812623SN/A def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4822623SN/A if not src1: 4832623SN/A src1 = dest 4842623SN/A super(RdRegOp, self).__init__(dest, src1, \ 4852623SN/A "InstRegIndex(NUM_INTREGS)", None, dataSize) 4862623SN/A 4872623SN/A class WrRegOp(RegOp): 4882623SN/A abstract = True 4892623SN/A def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4902623SN/A super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4912623SN/A src1, src2, flags, dataSize) 4922623SN/A 4932623SN/A class Add(FlagRegOp): 4942623SN/A code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4952623SN/A 4962623SN/A class Or(LogicRegOp): 4972623SN/A code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4982623SN/A 4992623SN/A class Adc(FlagRegOp): 5002623SN/A code = ''' 5012623SN/A CCFlagBits flags = ccFlagBits; 5022623SN/A DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 5032623SN/A ''' 5042623SN/A 5052623SN/A class Sbb(SubRegOp): 5062623SN/A code = ''' 5072623SN/A CCFlagBits flags = ccFlagBits; 5082623SN/A DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 5092623SN/A ''' 5102623SN/A 5112623SN/A class And(LogicRegOp): 5122623SN/A code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 5133387Sgblack@eecs.umich.edu 5143387Sgblack@eecs.umich.edu class Sub(SubRegOp): 5152626SN/A code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 5162662Sstever@eecs.umich.edu 5172623SN/A class Xor(LogicRegOp): 5182623SN/A code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 5194182Sgblack@eecs.umich.edu 5204182Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5214182Sgblack@eecs.umich.edu code = ''' 5222662Sstever@eecs.umich.edu ProdLow = psrc1 * op2; 5234182Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5244182Sgblack@eecs.umich.edu uint64_t shifter = (1ULL << halfSize); 5254182Sgblack@eecs.umich.edu uint64_t hiResult; 5264182Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5274182Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5282623SN/A uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5294182Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5304182Sgblack@eecs.umich.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5314182Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 5324182Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5334182Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 5342623SN/A hiResult -= op2; 5353814Ssaidi@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 5364182Sgblack@eecs.umich.edu hiResult -= psrc1; 5374182Sgblack@eecs.umich.edu ProdHi = hiResult; 5384182Sgblack@eecs.umich.edu ''' 5394182Sgblack@eecs.umich.edu flag_code = ''' 5404182Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 5412623SN/A bits(ProdLow, dataSize * 8 - 1)) { 5423814Ssaidi@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5433814Ssaidi@eecs.umich.edu } else { 5443901Ssaidi@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5453814Ssaidi@eecs.umich.edu } 5463814Ssaidi@eecs.umich.edu ''' 5472623SN/A 5484182Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5494182Sgblack@eecs.umich.edu code = ''' 5502623SN/A ProdLow = psrc1 * op2; 5512662Sstever@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5522803Ssaidi@eecs.umich.edu uint64_t shifter = (1ULL << halfSize); 5532803Ssaidi@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5542803Ssaidi@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5552803Ssaidi@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5562803Ssaidi@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5572623SN/A ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5582623SN/A ((psrc1_l * psrc2_l) / shifter)) / shifter) + 5592623SN/A psrc1_h * psrc2_h; 5604377Sgblack@eecs.umich.edu ''' 5614182Sgblack@eecs.umich.edu flag_code = ''' 5622623SN/A if (ProdHi) { 5632623SN/A ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5642626SN/A } else { 5652626SN/A ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5662623SN/A } 5672623SN/A ''' 5682623SN/A 5692623SN/A class Mulel(RdRegOp): 5702623SN/A code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5712623SN/A 5722623SN/A class Muleh(RdRegOp): 5732623SN/A def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5742623SN/A if not src1: 5752623SN/A src1 = dest 5762623SN/A super(RdRegOp, self).__init__(dest, src1, \ 5772623SN/A "InstRegIndex(NUM_INTREGS)", flags, dataSize) 5782623SN/A code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5793119Sktlim@umich.edu 5802901Ssaidi@eecs.umich.edu # One or two bit divide 5813170Sstever@eecs.umich.edu class Div1(WrRegOp): 5822623SN/A code = ''' 5832623SN/A //These are temporaries so that modifying them later won't make 5843453Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5853453Sgblack@eecs.umich.edu uint64_t quotient = 0; 5862623SN/A uint64_t remainder = psrc1; 5873617Sbinkertn@umich.edu //Similarly, this is a temporary so changing it doesn't make it 5883617Sbinkertn@umich.edu //a source. 5893617Sbinkertn@umich.edu uint64_t divisor = op2; 5903617Sbinkertn@umich.edu //This is a temporary just for consistency and clarity. 5912623SN/A uint64_t dividend = remainder; 5922623SN/A //Do the division. 5932623SN/A divide(dividend, divisor, quotient, remainder); 5942623SN/A //Record the final results. 5952623SN/A Remainder = remainder; 5963661Srdreslin@umich.edu Quotient = quotient; 5972623SN/A Divisor = divisor; 5982623SN/A ''' 5992623SN/A 6002623SN/A # Step divide 6012623SN/A class Div2(RegOp): 6022623SN/A code = ''' 6032623SN/A uint64_t dividend = Remainder; 6042623SN/A uint64_t divisor = Divisor; 6052623SN/A uint64_t quotient = Quotient; 6062623SN/A uint64_t remainder = dividend; 6072623SN/A int remaining = op2; 6082623SN/A //If we overshot, do nothing. This lets us unrool division loops a 6092623SN/A //little. 6102623SN/A if (remaining) { 6112623SN/A //Shift in bits from the low order portion of the dividend 6122623SN/A while(dividend < divisor && remaining) { 6132623SN/A dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 6142623SN/A quotient <<= 1; 6152623SN/A remaining--; 6163119Sktlim@umich.edu } 6172901Ssaidi@eecs.umich.edu remainder = dividend; 6183170Sstever@eecs.umich.edu //Do the division. 6192623SN/A divide(dividend, divisor, quotient, remainder); 6202623SN/A } 6212623SN/A //Keep track of how many bits there are still to pull in. 6222623SN/A DestReg = merge(DestReg, remaining, dataSize); 6232623SN/A //Record the final results 6243617Sbinkertn@umich.edu Remainder = remainder; 6253617Sbinkertn@umich.edu Quotient = quotient; 6263617Sbinkertn@umich.edu ''' 6272623SN/A flag_code = ''' 6282623SN/A if (DestReg == 0) 6292623SN/A ccFlagBits = ccFlagBits | (ext & EZFBit); 6302623SN/A else 6312623SN/A ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6323661Srdreslin@umich.edu ''' 6332623SN/A 6342623SN/A class Divq(RdRegOp): 6352623SN/A code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6362623SN/A 6372623SN/A class Divr(RdRegOp): 6382623SN/A code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6392623SN/A 6402623SN/A class Mov(CondRegOp): 6412623SN/A code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6422623SN/A else_code = 'DestReg = merge(DestReg, DestReg, dataSize);' 6432623SN/A 6442623SN/A # Shift instructions 6452623SN/A 6462623SN/A class Sll(RegOp): 6472623SN/A code = ''' 6482623SN/A uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6492623SN/A DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6502623SN/A ''' 6513119Sktlim@umich.edu flag_code = ''' 6522623SN/A // If the shift amount is zero, no flags should be modified. 6533661Srdreslin@umich.edu if (shiftAmt) { 6542623SN/A //Zero out any flags we might modify. This way we only have to 6552623SN/A //worry about setting them. 6562623SN/A ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6572623SN/A int CFBits = 0; 6582623SN/A //Figure out if we -would- set the CF bits if requested. 6592901Ssaidi@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 6603170Sstever@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 6612623SN/A CFBits = 1; 6622623SN/A } 6632623SN/A //If some combination of the CF bits need to be set, set them. 6642623SN/A if ((ext & (CFBit | ECFBit)) && CFBits) 6652623SN/A ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6663617Sbinkertn@umich.edu //Figure out what the OF bit should be. 6673617Sbinkertn@umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 6683617Sbinkertn@umich.edu ccFlagBits = ccFlagBits | OFBit; 6692623SN/A //Use the regular mechanisms to calculate the other flags. 6702623SN/A ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6712623SN/A DestReg, psrc1, op2); 6722623SN/A } 6732623SN/A ''' 6742623SN/A 6752623SN/A class Srl(RegOp): 6762623SN/A code = ''' 6772623SN/A uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6782623SN/A // Because what happens to the bits shift -in- on a right shift 679 // is not defined in the C/C++ standard, we have to mask them out 680 // to be sure they're zero. 681 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 682 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 683 ''' 684 flag_code = ''' 685 // If the shift amount is zero, no flags should be modified. 686 if (shiftAmt) { 687 //Zero out any flags we might modify. This way we only have to 688 //worry about setting them. 689 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 690 //If some combination of the CF bits need to be set, set them. 691 if ((ext & (CFBit | ECFBit)) && 692 shiftAmt <= dataSize * 8 && 693 bits(SrcReg1, shiftAmt - 1)) { 694 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 695 } 696 //Figure out what the OF bit should be. 697 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 698 ccFlagBits = ccFlagBits | OFBit; 699 //Use the regular mechanisms to calculate the other flags. 700 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 701 DestReg, psrc1, op2); 702 } 703 ''' 704 705 class Sra(RegOp): 706 code = ''' 707 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 708 // Because what happens to the bits shift -in- on a right shift 709 // is not defined in the C/C++ standard, we have to sign extend 710 // them manually to be sure. 711 uint64_t arithMask = (shiftAmt == 0) ? 0 : 712 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 713 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 714 ''' 715 flag_code = ''' 716 // If the shift amount is zero, no flags should be modified. 717 if (shiftAmt) { 718 //Zero out any flags we might modify. This way we only have to 719 //worry about setting them. 720 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 721 //If some combination of the CF bits need to be set, set them. 722 uint8_t effectiveShift = 723 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 724 if ((ext & (CFBit | ECFBit)) && 725 bits(SrcReg1, effectiveShift - 1)) { 726 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 727 } 728 //Use the regular mechanisms to calculate the other flags. 729 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 730 DestReg, psrc1, op2); 731 } 732 ''' 733 734 class Ror(RegOp): 735 code = ''' 736 uint8_t shiftAmt = 737 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 738 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 739 if(realShiftAmt) 740 { 741 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 742 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 743 DestReg = merge(DestReg, top | bottom, dataSize); 744 } 745 else 746 DestReg = merge(DestReg, DestReg, dataSize); 747 ''' 748 flag_code = ''' 749 // If the shift amount is zero, no flags should be modified. 750 if (shiftAmt) { 751 //Zero out any flags we might modify. This way we only have to 752 //worry about setting them. 753 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 754 //Find the most and second most significant bits of the result. 755 int msb = bits(DestReg, dataSize * 8 - 1); 756 int smsb = bits(DestReg, dataSize * 8 - 2); 757 //If some combination of the CF bits need to be set, set them. 758 if ((ext & (CFBit | ECFBit)) && msb) 759 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 760 //Figure out what the OF bit should be. 761 if ((ext & OFBit) && (msb ^ smsb)) 762 ccFlagBits = ccFlagBits | OFBit; 763 //Use the regular mechanisms to calculate the other flags. 764 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 765 DestReg, psrc1, op2); 766 } 767 ''' 768 769 class Rcr(RegOp): 770 code = ''' 771 uint8_t shiftAmt = 772 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 773 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 774 if(realShiftAmt) 775 { 776 CCFlagBits flags = ccFlagBits; 777 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 778 if (realShiftAmt > 1) 779 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 780 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 781 DestReg = merge(DestReg, top | bottom, dataSize); 782 } 783 else 784 DestReg = merge(DestReg, DestReg, dataSize); 785 ''' 786 flag_code = ''' 787 // If the shift amount is zero, no flags should be modified. 788 if (shiftAmt) { 789 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 790 //Zero out any flags we might modify. This way we only have to 791 //worry about setting them. 792 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 793 //Figure out what the OF bit should be. 794 if ((ext & OFBit) && (origCFBit ^ 795 bits(SrcReg1, dataSize * 8 - 1))) { 796 ccFlagBits = ccFlagBits | OFBit; 797 } 798 //If some combination of the CF bits need to be set, set them. 799 if ((ext & (CFBit | ECFBit)) && 800 (realShiftAmt == 0) ? origCFBit : 801 bits(SrcReg1, realShiftAmt - 1)) { 802 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 803 } 804 //Use the regular mechanisms to calculate the other flags. 805 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 806 DestReg, psrc1, op2); 807 } 808 ''' 809 810 class Rol(RegOp): 811 code = ''' 812 uint8_t shiftAmt = 813 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 814 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 815 if(realShiftAmt) 816 { 817 uint64_t top = psrc1 << realShiftAmt; 818 uint64_t bottom = 819 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 820 DestReg = merge(DestReg, top | bottom, dataSize); 821 } 822 else 823 DestReg = merge(DestReg, DestReg, dataSize); 824 ''' 825 flag_code = ''' 826 // If the shift amount is zero, no flags should be modified. 827 if (shiftAmt) { 828 //Zero out any flags we might modify. This way we only have to 829 //worry about setting them. 830 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 831 //The CF bits, if set, would be set to the lsb of the result. 832 int lsb = DestReg & 0x1; 833 int msb = bits(DestReg, dataSize * 8 - 1); 834 //If some combination of the CF bits need to be set, set them. 835 if ((ext & (CFBit | ECFBit)) && lsb) 836 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 837 //Figure out what the OF bit should be. 838 if ((ext & OFBit) && (msb ^ lsb)) 839 ccFlagBits = ccFlagBits | OFBit; 840 //Use the regular mechanisms to calculate the other flags. 841 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 842 DestReg, psrc1, op2); 843 } 844 ''' 845 846 class Rcl(RegOp): 847 code = ''' 848 uint8_t shiftAmt = 849 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 850 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 851 if(realShiftAmt) 852 { 853 CCFlagBits flags = ccFlagBits; 854 uint64_t top = psrc1 << realShiftAmt; 855 uint64_t bottom = flags.cf << (realShiftAmt - 1); 856 if(shiftAmt > 1) 857 bottom |= 858 bits(psrc1, dataSize * 8 - 1, 859 dataSize * 8 - realShiftAmt + 1); 860 DestReg = merge(DestReg, top | bottom, dataSize); 861 } 862 else 863 DestReg = merge(DestReg, DestReg, dataSize); 864 ''' 865 flag_code = ''' 866 // If the shift amount is zero, no flags should be modified. 867 if (shiftAmt) { 868 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 869 //Zero out any flags we might modify. This way we only have to 870 //worry about setting them. 871 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 872 int msb = bits(DestReg, dataSize * 8 - 1); 873 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 874 //If some combination of the CF bits need to be set, set them. 875 if ((ext & (CFBit | ECFBit)) && 876 (realShiftAmt == 0) ? origCFBit : CFBits) 877 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 878 //Figure out what the OF bit should be. 879 if ((ext & OFBit) && (msb ^ CFBits)) 880 ccFlagBits = ccFlagBits | OFBit; 881 //Use the regular mechanisms to calculate the other flags. 882 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 883 DestReg, psrc1, op2); 884 } 885 ''' 886 887 class Sld(RegOp): 888 code = ''' 889 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 890 uint8_t dataBits = dataSize * 8; 891 uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 892 uint64_t result; 893 if (realShiftAmt == 0) { 894 result = psrc1; 895 } else if (realShiftAmt < dataBits) { 896 result = (psrc1 << realShiftAmt) | 897 (DoubleBits >> (dataBits - realShiftAmt)); 898 } else { 899 result = (DoubleBits << (realShiftAmt - dataBits)) | 900 (psrc1 >> (2 * dataBits - realShiftAmt)); 901 } 902 DestReg = merge(DestReg, result, dataSize); 903 ''' 904 flag_code = ''' 905 // If the shift amount is zero, no flags should be modified. 906 if (shiftAmt) { 907 //Zero out any flags we might modify. This way we only have to 908 //worry about setting them. 909 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 910 int CFBits = 0; 911 //Figure out if we -would- set the CF bits if requested. 912 if ((realShiftAmt == 0 && 913 bits(DoubleBits, 0)) || 914 (realShiftAmt <= dataBits && 915 bits(SrcReg1, dataBits - realShiftAmt)) || 916 (realShiftAmt > dataBits && 917 bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 918 CFBits = 1; 919 } 920 //If some combination of the CF bits need to be set, set them. 921 if ((ext & (CFBit | ECFBit)) && CFBits) 922 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 923 //Figure out what the OF bit should be. 924 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 925 bits(result, dataBits - 1))) 926 ccFlagBits = ccFlagBits | OFBit; 927 //Use the regular mechanisms to calculate the other flags. 928 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 929 DestReg, psrc1, op2); 930 } 931 ''' 932 933 class Srd(RegOp): 934 code = ''' 935 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 936 uint8_t dataBits = dataSize * 8; 937 uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 938 uint64_t result; 939 if (realShiftAmt == 0) { 940 result = psrc1; 941 } else if (realShiftAmt < dataBits) { 942 // Because what happens to the bits shift -in- on a right 943 // shift is not defined in the C/C++ standard, we have to 944 // mask them out to be sure they're zero. 945 uint64_t logicalMask = mask(dataBits - realShiftAmt); 946 result = ((psrc1 >> realShiftAmt) & logicalMask) | 947 (DoubleBits << (dataBits - realShiftAmt)); 948 } else { 949 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 950 result = ((DoubleBits >> (realShiftAmt - dataBits)) & 951 logicalMask) | 952 (psrc1 << (2 * dataBits - realShiftAmt)); 953 } 954 DestReg = merge(DestReg, result, dataSize); 955 ''' 956 flag_code = ''' 957 // If the shift amount is zero, no flags should be modified. 958 if (shiftAmt) { 959 //Zero out any flags we might modify. This way we only have to 960 //worry about setting them. 961 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 962 int CFBits = 0; 963 //If some combination of the CF bits need to be set, set them. 964 if ((realShiftAmt == 0 && 965 bits(DoubleBits, dataBits - 1)) || 966 (realShiftAmt <= dataBits && 967 bits(SrcReg1, realShiftAmt - 1)) || 968 (realShiftAmt > dataBits && 969 bits(DoubleBits, realShiftAmt - dataBits - 1))) { 970 CFBits = 1; 971 } 972 //If some combination of the CF bits need to be set, set them. 973 if ((ext & (CFBit | ECFBit)) && CFBits) 974 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 975 //Figure out what the OF bit should be. 976 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 977 bits(result, dataBits - 1))) 978 ccFlagBits = ccFlagBits | OFBit; 979 //Use the regular mechanisms to calculate the other flags. 980 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 981 DestReg, psrc1, op2); 982 } 983 ''' 984 985 class Mdb(WrRegOp): 986 code = 'DoubleBits = psrc1 ^ op2;' 987 988 class Wrip(WrRegOp, CondRegOp): 989 code = 'RIP = psrc1 + sop2 + CSBase' 990 else_code="RIP = RIP;" 991 992 class Wruflags(WrRegOp): 993 code = 'ccFlagBits = psrc1 ^ op2' 994 995 class Wrflags(WrRegOp): 996 code = ''' 997 MiscReg newFlags = psrc1 ^ op2; 998 MiscReg userFlagMask = 0xDD5; 999 // Get only the user flags 1000 ccFlagBits = newFlags & userFlagMask; 1001 // Get everything else 1002 nccFlagBits = newFlags & ~userFlagMask; 1003 ''' 1004 1005 class Rdip(RdRegOp): 1006 code = 'DestReg = RIP - CSBase' 1007 1008 class Ruflags(RdRegOp): 1009 code = 'DestReg = ccFlagBits' 1010 1011 class Rflags(RdRegOp): 1012 code = 'DestReg = ccFlagBits | nccFlagBits' 1013 1014 class Ruflag(RegOp): 1015 code = ''' 1016 int flag = bits(ccFlagBits, imm8); 1017 DestReg = merge(DestReg, flag, dataSize); 1018 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1019 (ccFlagBits & ~EZFBit); 1020 ''' 1021 def __init__(self, dest, imm, flags=None, \ 1022 dataSize="env.dataSize"): 1023 super(Ruflag, self).__init__(dest, \ 1024 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 1025 1026 class Rflag(RegOp): 1027 code = ''' 1028 MiscReg flagMask = 0x3F7FDD5; 1029 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 1030 int flag = bits(flags, imm8); 1031 DestReg = merge(DestReg, flag, dataSize); 1032 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1033 (ccFlagBits & ~EZFBit); 1034 ''' 1035 def __init__(self, dest, imm, flags=None, \ 1036 dataSize="env.dataSize"): 1037 super(Rflag, self).__init__(dest, \ 1038 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 1039 1040 class Sext(RegOp): 1041 code = ''' 1042 IntReg val = psrc1; 1043 // Mask the bit position so that it wraps. 1044 int bitPos = op2 & (dataSize * 8 - 1); 1045 int sign_bit = bits(val, bitPos, bitPos); 1046 uint64_t maskVal = mask(bitPos+1); 1047 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 1048 DestReg = merge(DestReg, val, dataSize); 1049 ''' 1050 flag_code = ''' 1051 if (!sign_bit) 1052 ccFlagBits = ccFlagBits & 1053 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1054 else 1055 ccFlagBits = ccFlagBits | 1056 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1057 ''' 1058 1059 class Zext(RegOp): 1060 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 1061 1062 class Rddr(RegOp): 1063 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1064 super(Rddr, self).__init__(dest, \ 1065 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1066 code = ''' 1067 CR4 cr4 = CR4Op; 1068 DR7 dr7 = DR7Op; 1069 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 1070 fault = new InvalidOpcode(); 1071 } else if (dr7.gd) { 1072 fault = new DebugException(); 1073 } else { 1074 DestReg = merge(DestReg, DebugSrc1, dataSize); 1075 } 1076 ''' 1077 1078 class Wrdr(RegOp): 1079 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1080 super(Wrdr, self).__init__(dest, \ 1081 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1082 code = ''' 1083 CR4 cr4 = CR4Op; 1084 DR7 dr7 = DR7Op; 1085 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 1086 fault = new InvalidOpcode(); 1087 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 1088 machInst.mode.mode == LongMode) { 1089 fault = new GeneralProtection(0); 1090 } else if (dr7.gd) { 1091 fault = new DebugException(); 1092 } else { 1093 DebugDest = psrc1; 1094 } 1095 ''' 1096 1097 class Rdcr(RegOp): 1098 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1099 super(Rdcr, self).__init__(dest, \ 1100 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1101 code = ''' 1102 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 1103 fault = new InvalidOpcode(); 1104 } else { 1105 DestReg = merge(DestReg, ControlSrc1, dataSize); 1106 } 1107 ''' 1108 1109 class Wrcr(RegOp): 1110 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1111 super(Wrcr, self).__init__(dest, \ 1112 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1113 code = ''' 1114 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 1115 fault = new InvalidOpcode(); 1116 } else { 1117 // There are *s in the line below so it doesn't confuse the 1118 // parser. They may be unnecessary. 1119 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 1120 MiscReg newVal = psrc1; 1121 1122 // Check for any modifications that would cause a fault. 1123 switch(dest) { 1124 case 0: 1125 { 1126 Efer efer = EferOp; 1127 CR0 cr0 = newVal; 1128 CR4 oldCr4 = CR4Op; 1129 if (bits(newVal, 63, 32) || 1130 (!cr0.pe && cr0.pg) || 1131 (!cr0.cd && cr0.nw) || 1132 (cr0.pg && efer.lme && !oldCr4.pae)) 1133 fault = new GeneralProtection(0); 1134 } 1135 break; 1136 case 2: 1137 break; 1138 case 3: 1139 break; 1140 case 4: 1141 { 1142 CR4 cr4 = newVal; 1143 // PAE can't be disabled in long mode. 1144 if (bits(newVal, 63, 11) || 1145 (machInst.mode.mode == LongMode && !cr4.pae)) 1146 fault = new GeneralProtection(0); 1147 } 1148 break; 1149 case 8: 1150 { 1151 if (bits(newVal, 63, 4)) 1152 fault = new GeneralProtection(0); 1153 } 1154 default: 1155 panic("Unrecognized control register %d.\\n", dest); 1156 } 1157 ControlDest = newVal; 1158 } 1159 ''' 1160 1161 # Microops for manipulating segmentation registers 1162 class SegOp(CondRegOp): 1163 abstract = True 1164 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1165 super(SegOp, self).__init__(dest, \ 1166 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1167 1168 class Wrbase(SegOp): 1169 code = ''' 1170 SegBaseDest = psrc1; 1171 ''' 1172 1173 class Wrlimit(SegOp): 1174 code = ''' 1175 SegLimitDest = psrc1; 1176 ''' 1177 1178 class Wrsel(SegOp): 1179 code = ''' 1180 SegSelDest = psrc1; 1181 ''' 1182 1183 class WrAttr(SegOp): 1184 code = ''' 1185 SegAttrDest = psrc1; 1186 ''' 1187 1188 class Rdbase(SegOp): 1189 code = ''' 1190 DestReg = merge(DestReg, SegBaseSrc1, dataSize); 1191 ''' 1192 1193 class Rdlimit(SegOp): 1194 code = ''' 1195 DestReg = merge(DestReg, SegLimitSrc1, dataSize); 1196 ''' 1197 1198 class RdAttr(SegOp): 1199 code = ''' 1200 DestReg = merge(DestReg, SegAttrSrc1, dataSize); 1201 ''' 1202 1203 class Rdsel(SegOp): 1204 code = ''' 1205 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1206 ''' 1207 1208 class Rdval(RegOp): 1209 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1210 super(Rdval, self).__init__(dest, src1, \ 1211 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1212 code = ''' 1213 DestReg = MiscRegSrc1; 1214 ''' 1215 1216 class Wrval(RegOp): 1217 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1218 super(Wrval, self).__init__(dest, src1, \ 1219 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1220 code = ''' 1221 MiscRegDest = SrcReg1; 1222 ''' 1223 1224 class Chks(RegOp): 1225 def __init__(self, dest, src1, src2=0, 1226 flags=None, dataSize="env.dataSize"): 1227 super(Chks, self).__init__(dest, 1228 src1, src2, flags, dataSize) 1229 code = ''' 1230 // The selector is in source 1 and can be at most 16 bits. 1231 SegSelector selector = DestReg; 1232 SegDescriptor desc = SrcReg1; 1233 HandyM5Reg m5reg = M5Reg; 1234 1235 switch (imm8) 1236 { 1237 case SegNoCheck: 1238 break; 1239 case SegCSCheck: 1240 // Make sure it's the right type 1241 if (desc.s == 0 || desc.type.codeOrData != 1) { 1242 fault = new GeneralProtection(0); 1243 } else if (m5reg.cpl != desc.dpl) { 1244 fault = new GeneralProtection(0); 1245 } 1246 break; 1247 case SegCallGateCheck: 1248 panic("CS checks for far calls/jumps through call gates" 1249 "not implemented.\\n"); 1250 break; 1251 case SegSoftIntGateCheck: 1252 // Check permissions. 1253 if (desc.dpl < m5reg.cpl) { 1254 fault = new GeneralProtection(selector); 1255 break; 1256 } 1257 // Fall through on purpose 1258 case SegIntGateCheck: 1259 // Make sure the gate's the right type. 1260 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 1261 ((desc.type & 0x6) != 0x6)) { 1262 fault = new GeneralProtection(0); 1263 } 1264 break; 1265 case SegSSCheck: 1266 if (selector.si || selector.ti) { 1267 if (!desc.p) { 1268 fault = new StackFault(selector); 1269 } 1270 } else { 1271 if ((m5reg.submode != SixtyFourBitMode || 1272 m5reg.cpl == 3) || 1273 !(desc.s == 1 && 1274 desc.type.codeOrData == 0 && desc.type.w) || 1275 (desc.dpl != m5reg.cpl) || 1276 (selector.rpl != m5reg.cpl)) { 1277 fault = new GeneralProtection(selector); 1278 } 1279 } 1280 break; 1281 case SegIretCheck: 1282 { 1283 if ((!selector.si && !selector.ti) || 1284 (selector.rpl < m5reg.cpl) || 1285 !(desc.s == 1 && desc.type.codeOrData == 1) || 1286 (!desc.type.c && desc.dpl != selector.rpl) || 1287 (desc.type.c && desc.dpl > selector.rpl)) { 1288 fault = new GeneralProtection(selector); 1289 } else if (!desc.p) { 1290 fault = new SegmentNotPresent(selector); 1291 } 1292 break; 1293 } 1294 case SegIntCSCheck: 1295 if (m5reg.mode == LongMode) { 1296 if (desc.l != 1 || desc.d != 0) { 1297 fault = new GeneralProtection(selector); 1298 } 1299 } else { 1300 panic("Interrupt CS checks not implemented " 1301 "in legacy mode.\\n"); 1302 } 1303 break; 1304 case SegTRCheck: 1305 if (!selector.si || selector.ti) { 1306 fault = new GeneralProtection(selector); 1307 } 1308 break; 1309 case SegTSSCheck: 1310 if (!desc.p) { 1311 fault = new SegmentNotPresent(selector); 1312 } else if (!(desc.type == 0x9 || 1313 (desc.type == 1 && 1314 m5reg.mode != LongMode))) { 1315 fault = new GeneralProtection(selector); 1316 } 1317 break; 1318 case SegInGDTCheck: 1319 if (selector.ti) { 1320 fault = new GeneralProtection(selector); 1321 } 1322 break; 1323 case SegLDTCheck: 1324 if (!desc.p) { 1325 fault = new SegmentNotPresent(selector); 1326 } else if (desc.type != 0x2) { 1327 fault = new GeneralProtection(selector); 1328 } 1329 break; 1330 default: 1331 panic("Undefined segment check type.\\n"); 1332 } 1333 ''' 1334 flag_code = ''' 1335 // Check for a NULL selector and set ZF,EZF appropriately. 1336 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 1337 if (!selector.si && !selector.ti) 1338 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 1339 ''' 1340 1341 class Wrdh(RegOp): 1342 code = ''' 1343 SegDescriptor desc = SrcReg1; 1344 1345 uint64_t target = bits(SrcReg2, 31, 0) << 32; 1346 switch(desc.type) { 1347 case LDT64: 1348 case AvailableTSS64: 1349 case BusyTSS64: 1350 replaceBits(target, 23, 0, desc.baseLow); 1351 replaceBits(target, 31, 24, desc.baseHigh); 1352 break; 1353 case CallGate64: 1354 case IntGate64: 1355 case TrapGate64: 1356 replaceBits(target, 15, 0, bits(desc, 15, 0)); 1357 replaceBits(target, 31, 16, bits(desc, 63, 48)); 1358 break; 1359 default: 1360 panic("Wrdh used with wrong descriptor type!\\n"); 1361 } 1362 DestReg = target; 1363 ''' 1364 1365 class Wrtsc(WrRegOp): 1366 code = ''' 1367 TscOp = psrc1; 1368 ''' 1369 1370 class Rdtsc(RdRegOp): 1371 code = ''' 1372 DestReg = TscOp; 1373 ''' 1374 1375 class Rdm5reg(RdRegOp): 1376 code = ''' 1377 DestReg = M5Reg; 1378 ''' 1379 1380 class Wrdl(RegOp): 1381 code = ''' 1382 SegDescriptor desc = SrcReg1; 1383 SegSelector selector = SrcReg2; 1384 if (selector.si || selector.ti) { 1385 if (!desc.p) 1386 panic("Segment not present.\\n"); 1387 SegAttr attr = 0; 1388 attr.dpl = desc.dpl; 1389 attr.unusable = 0; 1390 attr.defaultSize = desc.d; 1391 attr.longMode = desc.l; 1392 attr.avl = desc.avl; 1393 attr.granularity = desc.g; 1394 attr.present = desc.p; 1395 attr.system = desc.s; 1396 attr.type = desc.type; 1397 if (!desc.s) { 1398 // The expand down bit happens to be set for gates. 1399 if (desc.type.e) { 1400 panic("Gate descriptor encountered.\\n"); 1401 } 1402 attr.readable = 1; 1403 attr.writable = 1; 1404 attr.expandDown = 0; 1405 } else { 1406 if (desc.type.codeOrData) { 1407 attr.expandDown = 0; 1408 attr.readable = desc.type.r; 1409 attr.writable = 0; 1410 } else { 1411 attr.expandDown = desc.type.e; 1412 attr.readable = 1; 1413 attr.writable = desc.type.w; 1414 } 1415 } 1416 Addr base = desc.baseLow | (desc.baseHigh << 24); 1417 Addr limit = desc.limitLow | (desc.limitHigh << 16); 1418 if (desc.g) 1419 limit = (limit << 12) | mask(12); 1420 SegBaseDest = base; 1421 SegLimitDest = limit; 1422 SegAttrDest = attr; 1423 } else { 1424 SegBaseDest = SegBaseDest; 1425 SegLimitDest = SegLimitDest; 1426 SegAttrDest = SegAttrDest; 1427 } 1428 ''' 1429}}; 1430