regop.isa revision 6447
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42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53//
54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
62def template MicroRegOpExecute {{
63        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64                Trace::InstRecord *traceData) const
65        {
66            Fault fault = NoFault;
67
68            DPRINTF(X86, "The data size is %d\n", dataSize);
69            %(op_decl)s;
70            %(op_rd)s;
71
72            if(%(cond_check)s)
73            {
74                %(code)s;
75                %(flag_code)s;
76            }
77            else
78            {
79                %(else_code)s;
80            }
81
82            //Write the resulting state to the execution context
83            if(fault == NoFault)
84            {
85                %(op_wb)s;
86            }
87            return fault;
88        }
89}};
90
91def template MicroRegOpImmExecute {{
92        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
93                Trace::InstRecord *traceData) const
94        {
95            Fault fault = NoFault;
96
97            %(op_decl)s;
98            %(op_rd)s;
99
100            if(%(cond_check)s)
101            {
102                %(code)s;
103                %(flag_code)s;
104            }
105            else
106            {
107                %(else_code)s;
108            }
109
110            //Write the resulting state to the execution context
111            if(fault == NoFault)
112            {
113                %(op_wb)s;
114            }
115            return fault;
116        }
117}};
118
119def template MicroRegOpDeclare {{
120    class %(class_name)s : public %(base_class)s
121    {
122      protected:
123        void buildMe();
124
125      public:
126        %(class_name)s(ExtMachInst _machInst,
127                const char * instMnem,
128                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
129                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
130                uint8_t _dataSize, uint16_t _ext);
131
132        %(class_name)s(ExtMachInst _machInst,
133                const char * instMnem,
134                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
135                uint8_t _dataSize, uint16_t _ext);
136
137        %(BasicExecDeclare)s
138    };
139}};
140
141def template MicroRegOpImmDeclare {{
142
143    class %(class_name)s : public %(base_class)s
144    {
145      protected:
146        void buildMe();
147
148      public:
149        %(class_name)s(ExtMachInst _machInst,
150                const char * instMnem,
151                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
152                InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
153                uint8_t _dataSize, uint16_t _ext);
154
155        %(class_name)s(ExtMachInst _machInst,
156                const char * instMnem,
157                InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
158                uint8_t _dataSize, uint16_t _ext);
159
160        %(BasicExecDeclare)s
161    };
162}};
163
164def template MicroRegOpConstructor {{
165
166    inline void %(class_name)s::buildMe()
167    {
168        %(constructor)s;
169    }
170
171    inline %(class_name)s::%(class_name)s(
172            ExtMachInst machInst, const char * instMnem,
173            InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
174            uint8_t _dataSize, uint16_t _ext) :
175        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
176                false, false, false, false,
177                _src1, _src2, _dest, _dataSize, _ext,
178                %(op_class)s)
179    {
180        buildMe();
181    }
182
183    inline %(class_name)s::%(class_name)s(
184            ExtMachInst machInst, const char * instMnem,
185            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
186            InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
187            uint8_t _dataSize, uint16_t _ext) :
188        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
189                isMicro, isDelayed, isFirst, isLast,
190                _src1, _src2, _dest, _dataSize, _ext,
191                %(op_class)s)
192    {
193        buildMe();
194    }
195}};
196
197def template MicroRegOpImmConstructor {{
198
199    inline void %(class_name)s::buildMe()
200    {
201        %(constructor)s;
202    }
203
204    inline %(class_name)s::%(class_name)s(
205            ExtMachInst machInst, const char * instMnem,
206            InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
207            uint8_t _dataSize, uint16_t _ext) :
208        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
209                false, false, false, false,
210                _src1, _imm8, _dest, _dataSize, _ext,
211                %(op_class)s)
212    {
213        buildMe();
214    }
215
216    inline %(class_name)s::%(class_name)s(
217            ExtMachInst machInst, const char * instMnem,
218            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
219            InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
220            uint8_t _dataSize, uint16_t _ext) :
221        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
222                isMicro, isDelayed, isFirst, isLast,
223                _src1, _imm8, _dest, _dataSize, _ext,
224                %(op_class)s)
225    {
226        buildMe();
227    }
228}};
229
230output header {{
231    void
232    divide(uint64_t dividend, uint64_t divisor,
233            uint64_t &quotient, uint64_t &remainder);
234
235    enum SegmentSelectorCheck {
236      SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
237      SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
238      SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck
239    };
240
241    enum LongModeDescriptorType {
242        LDT64 = 2,
243        AvailableTSS64 = 9,
244        BusyTSS64 = 0xb,
245        CallGate64 = 0xc,
246        IntGate64 = 0xe,
247        TrapGate64 = 0xf
248    };
249}};
250
251output decoder {{
252    void
253    divide(uint64_t dividend, uint64_t divisor,
254            uint64_t &quotient, uint64_t &remainder)
255    {
256        //Check for divide by zero.
257        if (divisor == 0)
258            panic("Divide by zero!\\n");
259        //If the divisor is bigger than the dividend, don't do anything.
260        if (divisor <= dividend) {
261            //Shift the divisor so it's msb lines up with the dividend.
262            int dividendMsb = findMsbSet(dividend);
263            int divisorMsb = findMsbSet(divisor);
264            int shift = dividendMsb - divisorMsb;
265            divisor <<= shift;
266            //Compute what we'll add to the quotient if the divisor isn't
267            //now larger than the dividend.
268            uint64_t quotientBit = 1;
269            quotientBit <<= shift;
270            //If we need to step back a bit (no pun intended) because the
271            //divisor got too to large, do that here. This is the "or two"
272            //part of one or two bit division.
273            if (divisor > dividend) {
274                quotientBit >>= 1;
275                divisor >>= 1;
276            }
277            //Decrement the remainder and increment the quotient.
278            quotient += quotientBit;
279            remainder -= divisor;
280        }
281    }
282}};
283
284let {{
285    # Make these empty strings so that concatenating onto
286    # them will always work.
287    header_output = ""
288    decoder_output = ""
289    exec_output = ""
290
291    immTemplates = (
292            MicroRegOpImmDeclare,
293            MicroRegOpImmConstructor,
294            MicroRegOpImmExecute)
295
296    regTemplates = (
297            MicroRegOpDeclare,
298            MicroRegOpConstructor,
299            MicroRegOpExecute)
300
301    class RegOpMeta(type):
302        def buildCppClasses(self, name, Name, suffix, \
303                code, flag_code, cond_check, else_code):
304
305            # Globals to stick the output in
306            global header_output
307            global decoder_output
308            global exec_output
309
310            # Stick all the code together so it can be searched at once
311            allCode = "|".join((code, flag_code, cond_check, else_code))
312
313            # If op2 is used anywhere, make register and immediate versions
314            # of this code.
315            matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
316            match = matcher.search(allCode)
317            if match:
318                typeQual = ""
319                if match.group("typeQual"):
320                    typeQual = match.group("typeQual")
321                src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
322                self.buildCppClasses(name, Name, suffix,
323                        matcher.sub(src2_name, code),
324                        matcher.sub(src2_name, flag_code),
325                        matcher.sub(src2_name, cond_check),
326                        matcher.sub(src2_name, else_code))
327                self.buildCppClasses(name + "i", Name, suffix + "Imm",
328                        matcher.sub("imm8", code),
329                        matcher.sub("imm8", flag_code),
330                        matcher.sub("imm8", cond_check),
331                        matcher.sub("imm8", else_code))
332                return
333
334            # If there's something optional to do with flags, generate
335            # a version without it and fix up this version to use it.
336            if flag_code != "" or cond_check != "true":
337                self.buildCppClasses(name, Name, suffix,
338                        code, "", "true", else_code)
339                suffix = "Flags" + suffix
340
341            # If psrc1 or psrc2 is used, we need to actually insert code to
342            # compute it.
343            matcher = re.compile("(?<!\w)psrc1(?!\w)")
344            if matcher.search(allCode):
345                code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
346            matcher = re.compile("(?<!\w)psrc2(?!\w)")
347            if matcher.search(allCode):
348                code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
349            # Also make available versions which do sign extension
350            matcher = re.compile("(?<!\w)spsrc1(?!\w)")
351            if matcher.search(allCode):
352                code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
353            matcher = re.compile("(?<!\w)spsrc2(?!\w)")
354            if matcher.search(allCode):
355                code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
356
357            base = "X86ISA::RegOp"
358
359            # If imm8 shows up in the code, use the immediate templates, if
360            # not, hopefully the register ones will be correct.
361            templates = regTemplates
362            matcher = re.compile("(?<!\w)imm8(?!\w)")
363            if matcher.search(allCode):
364                base += "Imm"
365                templates = immTemplates
366
367            # Get everything ready for the substitution
368            iop = InstObjParams(name, Name + suffix, base,
369                    {"code" : code,
370                     "flag_code" : flag_code,
371                     "cond_check" : cond_check,
372                     "else_code" : else_code})
373
374            # Generate the actual code (finally!)
375            header_output += templates[0].subst(iop)
376            decoder_output += templates[1].subst(iop)
377            exec_output += templates[2].subst(iop)
378
379
380        def __new__(mcls, Name, bases, dict):
381            abstract = False
382            name = Name.lower()
383            if "abstract" in dict:
384                abstract = dict['abstract']
385                del dict['abstract']
386
387            cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
388            if not abstract:
389                cls.className = Name
390                cls.base_mnemonic = name
391                code = cls.code
392                flag_code = cls.flag_code
393                cond_check = cls.cond_check
394                else_code = cls.else_code
395
396                # Set up the C++ classes
397                mcls.buildCppClasses(cls, name, Name, "",
398                        code, flag_code, cond_check, else_code)
399
400                # Hook into the microassembler dict
401                global microopClasses
402                microopClasses[name] = cls
403
404                allCode = "|".join((code, flag_code, cond_check, else_code))
405
406                # If op2 is used anywhere, make register and immediate versions
407                # of this code.
408                matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
409                if matcher.search(allCode):
410                    microopClasses[name + 'i'] = cls
411            return cls
412
413
414    class RegOp(X86Microop):
415        __metaclass__ = RegOpMeta
416        # This class itself doesn't act as a microop
417        abstract = True
418
419        # Default template parameter values
420        flag_code = ""
421        cond_check = "true"
422        else_code = ";"
423
424        def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
425            self.dest = dest
426            self.src1 = src1
427            self.op2 = op2
428            self.flags = flags
429            self.dataSize = dataSize
430            if flags is None:
431                self.ext = 0
432            else:
433                if not isinstance(flags, (list, tuple)):
434                    raise Exception, "flags must be a list or tuple of flags"
435                self.ext = " | ".join(flags)
436                self.className += "Flags"
437
438        def getAllocator(self, *microFlags):
439            className = self.className
440            if self.mnemonic == self.base_mnemonic + 'i':
441                className += "Imm"
442            allocator = '''new %(class_name)s(machInst, macrocodeBlock
443                    %(flags)s, %(src1)s, %(op2)s, %(dest)s,
444                    %(dataSize)s, %(ext)s)''' % {
445                "class_name" : className,
446                "flags" : self.microFlagsText(microFlags),
447                "src1" : self.src1, "op2" : self.op2,
448                "dest" : self.dest,
449                "dataSize" : self.dataSize,
450                "ext" : self.ext}
451            return allocator
452
453    class LogicRegOp(RegOp):
454        abstract = True
455        flag_code = '''
456            //Don't have genFlags handle the OF or CF bits
457            uint64_t mask = CFBit | ECFBit | OFBit;
458            ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
459            //If a logic microop wants to set these, it wants to set them to 0.
460            ccFlagBits &= ~(CFBit & ext);
461            ccFlagBits &= ~(ECFBit & ext);
462            ccFlagBits &= ~(OFBit & ext);
463        '''
464
465    class FlagRegOp(RegOp):
466        abstract = True
467        flag_code = \
468            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
469
470    class SubRegOp(RegOp):
471        abstract = True
472        flag_code = \
473            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
474
475    class CondRegOp(RegOp):
476        abstract = True
477        cond_check = "checkCondition(ccFlagBits, ext)"
478
479    class RdRegOp(RegOp):
480        abstract = True
481        def __init__(self, dest, src1=None, dataSize="env.dataSize"):
482            if not src1:
483                src1 = dest
484            super(RdRegOp, self).__init__(dest, src1, \
485                    "InstRegIndex(NUM_INTREGS)", None, dataSize)
486
487    class WrRegOp(RegOp):
488        abstract = True
489        def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
490            super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
491                    src1, src2, flags, dataSize)
492
493    class Add(FlagRegOp):
494        code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
495
496    class Or(LogicRegOp):
497        code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
498
499    class Adc(FlagRegOp):
500        code = '''
501            CCFlagBits flags = ccFlagBits;
502            DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
503            '''
504
505    class Sbb(SubRegOp):
506        code = '''
507            CCFlagBits flags = ccFlagBits;
508            DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
509            '''
510
511    class And(LogicRegOp):
512        code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
513
514    class Sub(SubRegOp):
515        code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
516
517    class Xor(LogicRegOp):
518        code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
519
520    class Mul1s(WrRegOp):
521        code = '''
522            ProdLow = psrc1 * op2;
523            int halfSize = (dataSize * 8) / 2;
524            uint64_t shifter = (1ULL << halfSize);
525            uint64_t hiResult;
526            uint64_t psrc1_h = psrc1 / shifter;
527            uint64_t psrc1_l = psrc1 & mask(halfSize);
528            uint64_t psrc2_h = op2 / shifter;
529            uint64_t psrc2_l = op2 & mask(halfSize);
530            hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
531                        ((psrc1_l * psrc2_l) / shifter)) /shifter) +
532                       psrc1_h * psrc2_h;
533            if (spsrc1 < 0)
534                hiResult -= op2;
535            int64_t bigSop2 = sop2;
536            if (bigSop2 < 0)
537                hiResult -= psrc1;
538            ProdHi = hiResult;
539            '''
540
541    class Mul1u(WrRegOp):
542        code = '''
543            ProdLow = psrc1 * op2;
544            int halfSize = (dataSize * 8) / 2;
545            uint64_t shifter = (1ULL << halfSize);
546            uint64_t psrc1_h = psrc1 / shifter;
547            uint64_t psrc1_l = psrc1 & mask(halfSize);
548            uint64_t psrc2_h = op2 / shifter;
549            uint64_t psrc2_l = op2 & mask(halfSize);
550            ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
551                      ((psrc1_l * psrc2_l) / shifter)) / shifter) +
552                     psrc1_h * psrc2_h;
553            '''
554
555    class Mulel(RdRegOp):
556        code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
557
558    class Muleh(RdRegOp):
559        def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
560            if not src1:
561                src1 = dest
562            super(RdRegOp, self).__init__(dest, src1, \
563                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
564        code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
565        flag_code = '''
566            if (ProdHi)
567                ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
568            else
569                ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
570        '''
571
572    # One or two bit divide
573    class Div1(WrRegOp):
574        code = '''
575            //These are temporaries so that modifying them later won't make
576            //the ISA parser think they're also sources.
577            uint64_t quotient = 0;
578            uint64_t remainder = psrc1;
579            //Similarly, this is a temporary so changing it doesn't make it
580            //a source.
581            uint64_t divisor = op2;
582            //This is a temporary just for consistency and clarity.
583            uint64_t dividend = remainder;
584            //Do the division.
585            divide(dividend, divisor, quotient, remainder);
586            //Record the final results.
587            Remainder = remainder;
588            Quotient = quotient;
589            Divisor = divisor;
590            '''
591
592    # Step divide
593    class Div2(RegOp):
594        code = '''
595            uint64_t dividend = Remainder;
596            uint64_t divisor = Divisor;
597            uint64_t quotient = Quotient;
598            uint64_t remainder = dividend;
599            int remaining = op2;
600            //If we overshot, do nothing. This lets us unrool division loops a
601            //little.
602            if (remaining) {
603                //Shift in bits from the low order portion of the dividend
604                while(dividend < divisor && remaining) {
605                    dividend = (dividend << 1) | bits(SrcReg1, remaining - 1);
606                    quotient <<= 1;
607                    remaining--;
608                }
609                remainder = dividend;
610                //Do the division.
611                divide(dividend, divisor, quotient, remainder);
612            }
613            //Keep track of how many bits there are still to pull in.
614            DestReg = merge(DestReg, remaining, dataSize);
615            //Record the final results
616            Remainder = remainder;
617            Quotient = quotient;
618        '''
619        flag_code = '''
620            if (DestReg == 0)
621                ccFlagBits = ccFlagBits | (ext & EZFBit);
622            else
623                ccFlagBits = ccFlagBits & ~(ext & EZFBit);
624        '''
625
626    class Divq(RdRegOp):
627        code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
628
629    class Divr(RdRegOp):
630        code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
631
632    class Mov(CondRegOp):
633        code = 'DestReg = merge(SrcReg1, op2, dataSize)'
634        else_code = 'DestReg=DestReg;'
635
636    # Shift instructions
637
638    class Sll(RegOp):
639        code = '''
640            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
641            DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
642            '''
643        flag_code = '''
644            // If the shift amount is zero, no flags should be modified.
645            if (shiftAmt) {
646                //Zero out any flags we might modify. This way we only have to
647                //worry about setting them.
648                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
649                int CFBits = 0;
650                //Figure out if we -would- set the CF bits if requested.
651                if (shiftAmt <= dataSize * 8 &&
652                        bits(SrcReg1, dataSize * 8 - shiftAmt)) {
653                    CFBits = 1;
654                }
655                //If some combination of the CF bits need to be set, set them.
656                if ((ext & (CFBit | ECFBit)) && CFBits)
657                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
658                //Figure out what the OF bit should be.
659                if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
660                    ccFlagBits = ccFlagBits | OFBit;
661                //Use the regular mechanisms to calculate the other flags.
662                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
663                        DestReg, psrc1, op2);
664            }
665        '''
666
667    class Srl(RegOp):
668        code = '''
669            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
670            // Because what happens to the bits shift -in- on a right shift
671            // is not defined in the C/C++ standard, we have to mask them out
672            // to be sure they're zero.
673            uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
674            DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
675            '''
676        flag_code = '''
677            // If the shift amount is zero, no flags should be modified.
678            if (shiftAmt) {
679                //Zero out any flags we might modify. This way we only have to
680                //worry about setting them.
681                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
682                //If some combination of the CF bits need to be set, set them.
683                if ((ext & (CFBit | ECFBit)) && 
684                        shiftAmt <= dataSize * 8 &&
685                        bits(SrcReg1, shiftAmt - 1)) {
686                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
687                }
688                //Figure out what the OF bit should be.
689                if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
690                    ccFlagBits = ccFlagBits | OFBit;
691                //Use the regular mechanisms to calculate the other flags.
692                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
693                        DestReg, psrc1, op2);
694            }
695        '''
696
697    class Sra(RegOp):
698        code = '''
699            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
700            // Because what happens to the bits shift -in- on a right shift
701            // is not defined in the C/C++ standard, we have to sign extend
702            // them manually to be sure.
703            uint64_t arithMask = (shiftAmt == 0) ? 0 :
704                -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
705            DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
706            '''
707        flag_code = '''
708            // If the shift amount is zero, no flags should be modified.
709            if (shiftAmt) {
710                //Zero out any flags we might modify. This way we only have to
711                //worry about setting them.
712                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
713                //If some combination of the CF bits need to be set, set them.
714                uint8_t effectiveShift =
715                    (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
716                if ((ext & (CFBit | ECFBit)) &&
717                        bits(SrcReg1, effectiveShift - 1)) {
718                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
719                }
720                //Use the regular mechanisms to calculate the other flags.
721                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
722                        DestReg, psrc1, op2);
723            }
724        '''
725
726    class Ror(RegOp):
727        code = '''
728            uint8_t shiftAmt =
729                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
730            if(shiftAmt)
731            {
732                uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
733                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
734                DestReg = merge(DestReg, top | bottom, dataSize);
735            }
736            else
737                DestReg = merge(DestReg, DestReg, dataSize);
738            '''
739        flag_code = '''
740            // If the shift amount is zero, no flags should be modified.
741            if (shiftAmt) {
742                //Zero out any flags we might modify. This way we only have to
743                //worry about setting them.
744                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
745                //Find the most and second most significant bits of the result.
746                int msb = bits(DestReg, dataSize * 8 - 1);
747                int smsb = bits(DestReg, dataSize * 8 - 2);
748                //If some combination of the CF bits need to be set, set them.
749                if ((ext & (CFBit | ECFBit)) && msb)
750                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
751                //Figure out what the OF bit should be.
752                if ((ext & OFBit) && (msb ^ smsb))
753                    ccFlagBits = ccFlagBits | OFBit;
754                //Use the regular mechanisms to calculate the other flags.
755                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
756                        DestReg, psrc1, op2);
757            }
758        '''
759
760    class Rcr(RegOp):
761        code = '''
762            uint8_t shiftAmt =
763                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
764            if(shiftAmt)
765            {
766                CCFlagBits flags = ccFlagBits;
767                uint64_t top = flags.cf << (dataSize * 8 - shiftAmt);
768                if(shiftAmt > 1)
769                    top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
770                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
771                DestReg = merge(DestReg, top | bottom, dataSize);
772            }
773            else
774                DestReg = merge(DestReg, DestReg, dataSize);
775            '''
776        flag_code = '''
777            // If the shift amount is zero, no flags should be modified.
778            if (shiftAmt) {
779                //Zero out any flags we might modify. This way we only have to
780                //worry about setting them.
781                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
782                //Figure out what the OF bit should be.
783                if ((ext & OFBit) && ((ccFlagBits & CFBit) ^
784                                      bits(SrcReg1, dataSize * 8 - 1)))
785                    ccFlagBits = ccFlagBits | OFBit;
786                //If some combination of the CF bits need to be set, set them.
787                if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
788                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
789                //Use the regular mechanisms to calculate the other flags.
790                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
791                        DestReg, psrc1, op2);
792            }
793        '''
794
795    class Rol(RegOp):
796        code = '''
797            uint8_t shiftAmt =
798                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
799            uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
800            if(realShiftAmt)
801            {
802                uint64_t top = psrc1 << realShiftAmt;
803                uint64_t bottom =
804                    bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
805                DestReg = merge(DestReg, top | bottom, dataSize);
806            }
807            else
808                DestReg = merge(DestReg, DestReg, dataSize);
809            '''
810        flag_code = '''
811            // If the shift amount is zero, no flags should be modified.
812            if (shiftAmt) {
813                //Zero out any flags we might modify. This way we only have to
814                //worry about setting them.
815                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
816                //The CF bits, if set, would be set to the lsb of the result.
817                int lsb = DestReg & 0x1;
818                int msb = bits(DestReg, dataSize * 8 - 1);
819                //If some combination of the CF bits need to be set, set them.
820                if ((ext & (CFBit | ECFBit)) && lsb)
821                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
822                //Figure out what the OF bit should be.
823                if ((ext & OFBit) && (msb ^ lsb))
824                    ccFlagBits = ccFlagBits | OFBit;
825                //Use the regular mechanisms to calculate the other flags.
826                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
827                        DestReg, psrc1, op2);
828            }
829        '''
830
831    class Rcl(RegOp):
832        code = '''
833            uint8_t shiftAmt =
834                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
835            if(shiftAmt)
836            {
837                CCFlagBits flags = ccFlagBits;
838                uint64_t top = psrc1 << shiftAmt;
839                uint64_t bottom = flags.cf << (shiftAmt - 1);
840                if(shiftAmt > 1)
841                    bottom |=
842                        bits(psrc1, dataSize * 8 - 1,
843                                   dataSize * 8 - shiftAmt + 1);
844                DestReg = merge(DestReg, top | bottom, dataSize);
845            }
846            else
847                DestReg = merge(DestReg, DestReg, dataSize);
848            '''
849        flag_code = '''
850            // If the shift amount is zero, no flags should be modified.
851            if (shiftAmt) {
852                //Zero out any flags we might modify. This way we only have to
853                //worry about setting them.
854                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
855                int msb = bits(DestReg, dataSize * 8 - 1);
856                int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt);
857                //If some combination of the CF bits need to be set, set them.
858                if ((ext & (CFBit | ECFBit)) && CFBits)
859                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
860                //Figure out what the OF bit should be.
861                if ((ext & OFBit) && (msb ^ CFBits))
862                    ccFlagBits = ccFlagBits | OFBit;
863                //Use the regular mechanisms to calculate the other flags.
864                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
865                        DestReg, psrc1, op2);
866            }
867        '''
868
869    class Wrip(WrRegOp, CondRegOp):
870        code = 'RIP = psrc1 + sop2 + CSBase'
871        else_code="RIP = RIP;"
872
873    class Wruflags(WrRegOp):
874        code = 'ccFlagBits = psrc1 ^ op2'
875
876    class Wrflags(WrRegOp):
877        code = '''
878            MiscReg newFlags = psrc1 ^ op2;
879            MiscReg userFlagMask = 0xDD5;
880            // Get only the user flags
881            ccFlagBits = newFlags & userFlagMask;
882            // Get everything else
883            nccFlagBits = newFlags & ~userFlagMask;
884        '''
885
886    class Rdip(RdRegOp):
887        code = 'DestReg = RIP - CSBase'
888
889    class Ruflags(RdRegOp):
890        code = 'DestReg = ccFlagBits'
891
892    class Rflags(RdRegOp):
893        code = 'DestReg = ccFlagBits | nccFlagBits'
894
895    class Ruflag(RegOp):
896        code = '''
897            int flag = bits(ccFlagBits, imm8);
898            DestReg = merge(DestReg, flag, dataSize);
899            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
900                                       (ccFlagBits & ~EZFBit);
901            '''
902        def __init__(self, dest, imm, flags=None, \
903                dataSize="env.dataSize"):
904            super(Ruflag, self).__init__(dest, \
905                    "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
906
907    class Rflag(RegOp):
908        code = '''
909            MiscReg flagMask = 0x3F7FDD5;
910            MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
911            int flag = bits(flags, imm8);
912            DestReg = merge(DestReg, flag, dataSize);
913            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
914                                       (ccFlagBits & ~EZFBit);
915            '''
916        def __init__(self, dest, imm, flags=None, \
917                dataSize="env.dataSize"):
918            super(Rflag, self).__init__(dest, \
919                    "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
920
921    class Sext(RegOp):
922        code = '''
923            IntReg val = psrc1;
924            // Mask the bit position so that it wraps.
925            int bitPos = op2 & (dataSize * 8 - 1);
926            int sign_bit = bits(val, bitPos, bitPos);
927            uint64_t maskVal = mask(bitPos+1);
928            val = sign_bit ? (val | ~maskVal) : (val & maskVal);
929            DestReg = merge(DestReg, val, dataSize);
930            '''
931        flag_code = '''
932            if (!sign_bit)
933                ccFlagBits = ccFlagBits &
934                    ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
935            else
936                ccFlagBits = ccFlagBits |
937                    (ext & (CFBit | ECFBit | ZFBit | EZFBit));
938            '''
939
940    class Zext(RegOp):
941        code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
942
943    class Rddr(RegOp):
944        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
945            super(Rddr, self).__init__(dest, \
946                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
947        code = '''
948            CR4 cr4 = CR4Op;
949            DR7 dr7 = DR7Op;
950            if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
951                fault = new InvalidOpcode();
952            } else if (dr7.gd) {
953                fault = new DebugException();
954            } else {
955                DestReg = merge(DestReg, DebugSrc1, dataSize);
956            }
957        '''
958
959    class Wrdr(RegOp):
960        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
961            super(Wrdr, self).__init__(dest, \
962                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
963        code = '''
964            CR4 cr4 = CR4Op;
965            DR7 dr7 = DR7Op;
966            if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
967                fault = new InvalidOpcode();
968            } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
969                    machInst.mode.mode == LongMode) {
970                fault = new GeneralProtection(0);
971            } else if (dr7.gd) {
972                fault = new DebugException();
973            } else {
974                DebugDest = psrc1;
975            }
976        '''
977
978    class Rdcr(RegOp):
979        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
980            super(Rdcr, self).__init__(dest, \
981                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
982        code = '''
983            if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
984                fault = new InvalidOpcode();
985            } else {
986                DestReg = merge(DestReg, ControlSrc1, dataSize);
987            }
988        '''
989
990    class Wrcr(RegOp):
991        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
992            super(Wrcr, self).__init__(dest, \
993                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
994        code = '''
995            if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
996                fault = new InvalidOpcode();
997            } else {
998                // There are *s in the line below so it doesn't confuse the
999                // parser. They may be unnecessary.
1000                //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
1001                MiscReg newVal = psrc1;
1002
1003                // Check for any modifications that would cause a fault.
1004                switch(dest) {
1005                  case 0:
1006                    {
1007                        Efer efer = EferOp;
1008                        CR0 cr0 = newVal;
1009                        CR4 oldCr4 = CR4Op;
1010                        if (bits(newVal, 63, 32) ||
1011                                (!cr0.pe && cr0.pg) ||
1012                                (!cr0.cd && cr0.nw) ||
1013                                (cr0.pg && efer.lme && !oldCr4.pae))
1014                            fault = new GeneralProtection(0);
1015                    }
1016                    break;
1017                  case 2:
1018                    break;
1019                  case 3:
1020                    break;
1021                  case 4:
1022                    {
1023                        CR4 cr4 = newVal;
1024                        // PAE can't be disabled in long mode.
1025                        if (bits(newVal, 63, 11) ||
1026                                (machInst.mode.mode == LongMode && !cr4.pae))
1027                            fault = new GeneralProtection(0);
1028                    }
1029                    break;
1030                  case 8:
1031                    {
1032                        if (bits(newVal, 63, 4))
1033                            fault = new GeneralProtection(0);
1034                    }
1035                  default:
1036                    panic("Unrecognized control register %d.\\n", dest);
1037                }
1038                ControlDest = newVal;
1039            }
1040            '''
1041
1042    # Microops for manipulating segmentation registers
1043    class SegOp(CondRegOp):
1044        abstract = True
1045        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1046            super(SegOp, self).__init__(dest, \
1047                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1048
1049    class Wrbase(SegOp):
1050        code = '''
1051            SegBaseDest = psrc1;
1052        '''
1053
1054    class Wrlimit(SegOp):
1055        code = '''
1056            SegLimitDest = psrc1;
1057        '''
1058
1059    class Wrsel(SegOp):
1060        code = '''
1061            SegSelDest = psrc1;
1062        '''
1063
1064    class WrAttr(SegOp):
1065        code = '''
1066            SegAttrDest = psrc1;
1067        '''
1068
1069    class Rdbase(SegOp):
1070        code = '''
1071            DestReg = merge(DestReg, SegBaseSrc1, dataSize);
1072        '''
1073
1074    class Rdlimit(SegOp):
1075        code = '''
1076            DestReg = merge(DestReg, SegLimitSrc1, dataSize);
1077        '''
1078
1079    class RdAttr(SegOp):
1080        code = '''
1081            DestReg = merge(DestReg, SegAttrSrc1, dataSize);
1082        '''
1083
1084    class Rdsel(SegOp):
1085        code = '''
1086            DestReg = merge(DestReg, SegSelSrc1, dataSize);
1087        '''
1088
1089    class Rdval(RegOp):
1090        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1091            super(Rdval, self).__init__(dest, src1, \
1092                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1093        code = '''
1094            DestReg = MiscRegSrc1;
1095        '''
1096
1097    class Wrval(RegOp):
1098        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1099            super(Wrval, self).__init__(dest, src1, \
1100                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1101        code = '''
1102            MiscRegDest = SrcReg1;
1103        '''
1104
1105    class Chks(RegOp):
1106        def __init__(self, dest, src1, src2=0,
1107                flags=None, dataSize="env.dataSize"):
1108            super(Chks, self).__init__(dest,
1109                    src1, src2, flags, dataSize)
1110        code = '''
1111            // The selector is in source 1 and can be at most 16 bits.
1112            SegSelector selector = DestReg;
1113            SegDescriptor desc = SrcReg1;
1114            HandyM5Reg m5reg = M5Reg;
1115
1116            switch (imm8)
1117            {
1118              case SegNoCheck:
1119                break;
1120              case SegCSCheck:
1121                // Make sure it's the right type
1122                if (desc.s == 0 || desc.type.codeOrData != 1) {
1123                    fault = new GeneralProtection(0);
1124                } else if (m5reg.cpl != desc.dpl) {
1125                    fault = new GeneralProtection(0);
1126                }
1127                break;
1128              case SegCallGateCheck:
1129                panic("CS checks for far calls/jumps through call gates"
1130                        "not implemented.\\n");
1131                break;
1132              case SegSoftIntGateCheck:
1133                // Check permissions.
1134                if (desc.dpl < m5reg.cpl) {
1135                    fault = new GeneralProtection(selector);
1136                    break;
1137                }
1138                // Fall through on purpose
1139              case SegIntGateCheck:
1140                // Make sure the gate's the right type.
1141                if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
1142                        ((desc.type & 0x6) != 0x6)) {
1143                    fault = new GeneralProtection(0);
1144                }
1145                break;
1146              case SegSSCheck:
1147                if (selector.si || selector.ti) {
1148                    if (!desc.p) {
1149                        fault = new StackFault(selector);
1150                    }
1151                } else {
1152                    if ((m5reg.submode != SixtyFourBitMode ||
1153                                m5reg.cpl == 3) ||
1154                            !(desc.s == 1 &&
1155                            desc.type.codeOrData == 0 && desc.type.w) ||
1156                            (desc.dpl != m5reg.cpl) ||
1157                            (selector.rpl != m5reg.cpl)) {
1158                        fault = new GeneralProtection(selector);
1159                    }
1160                }
1161                break;
1162              case SegIretCheck:
1163                {
1164                    if ((!selector.si && !selector.ti) ||
1165                            (selector.rpl < m5reg.cpl) ||
1166                            !(desc.s == 1 && desc.type.codeOrData == 1) ||
1167                            (!desc.type.c && desc.dpl != selector.rpl) ||
1168                            (desc.type.c && desc.dpl > selector.rpl)) {
1169                        fault = new GeneralProtection(selector);
1170                    } else if (!desc.p) {
1171                        fault = new SegmentNotPresent(selector);
1172                    }
1173                    break;
1174                }
1175              case SegIntCSCheck:
1176                if (m5reg.mode == LongMode) {
1177                    if (desc.l != 1 || desc.d != 0) {
1178                        fault = new GeneralProtection(selector);
1179                    }
1180                } else {
1181                    panic("Interrupt CS checks not implemented "
1182                            "in legacy mode.\\n");
1183                }
1184                break;
1185              case SegTRCheck:
1186                if (!selector.si || selector.ti) {
1187                    fault = new GeneralProtection(selector);
1188                }
1189                break;
1190              case SegTSSCheck:
1191                if (!desc.p) {
1192                    fault = new SegmentNotPresent(selector);
1193                } else if (!(desc.type == 0x9 ||
1194                        (desc.type == 1 &&
1195                         m5reg.mode != LongMode))) {
1196                    fault = new GeneralProtection(selector);
1197                }
1198                break;
1199              case SegInGDTCheck:
1200                if (selector.ti) {
1201                    fault = new GeneralProtection(selector);
1202                }
1203                break;
1204              case SegLDTCheck:
1205                if (!desc.p) {
1206                    fault = new SegmentNotPresent(selector);
1207                } else if (desc.type != 0x2) {
1208                    fault = new GeneralProtection(selector);
1209                }
1210                break;
1211              default:
1212                panic("Undefined segment check type.\\n");
1213            }
1214        '''
1215        flag_code = '''
1216            // Check for a NULL selector and set ZF,EZF appropriately.
1217            ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1218            if (!selector.si && !selector.ti)
1219                ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1220        '''
1221
1222    class Wrdh(RegOp):
1223        code = '''
1224            SegDescriptor desc = SrcReg1;
1225
1226            uint64_t target = bits(SrcReg2, 31, 0) << 32;
1227            switch(desc.type) {
1228              case LDT64:
1229              case AvailableTSS64:
1230              case BusyTSS64:
1231                replaceBits(target, 23, 0, desc.baseLow);
1232                replaceBits(target, 31, 24, desc.baseHigh);
1233                break;
1234              case CallGate64:
1235              case IntGate64:
1236              case TrapGate64:
1237                replaceBits(target, 15, 0, bits(desc, 15, 0));
1238                replaceBits(target, 31, 16, bits(desc, 63, 48));
1239                break;
1240              default:
1241                panic("Wrdh used with wrong descriptor type!\\n");
1242            }
1243            DestReg = target;
1244        '''
1245
1246    class Wrtsc(WrRegOp):
1247        code = '''
1248            TscOp = psrc1;
1249        '''
1250
1251    class Rdtsc(RdRegOp):
1252        code = '''
1253            DestReg = TscOp;
1254        '''
1255
1256    class Rdm5reg(RdRegOp):
1257        code = '''
1258            DestReg = M5Reg;
1259        '''
1260
1261    class Wrdl(RegOp):
1262        code = '''
1263            SegDescriptor desc = SrcReg1;
1264            SegSelector selector = SrcReg2;
1265            if (selector.si || selector.ti) {
1266                if (!desc.p)
1267                    panic("Segment not present.\\n");
1268                SegAttr attr = 0;
1269                attr.dpl = desc.dpl;
1270                attr.unusable = 0;
1271                attr.defaultSize = desc.d;
1272                attr.longMode = desc.l;
1273                attr.avl = desc.avl;
1274                attr.granularity = desc.g;
1275                attr.present = desc.p;
1276                attr.system = desc.s;
1277                attr.type = desc.type;
1278                if (!desc.s) {
1279                    // The expand down bit happens to be set for gates.
1280                    if (desc.type.e) {
1281                        panic("Gate descriptor encountered.\\n");
1282                    }
1283                    attr.readable = 1;
1284                    attr.writable = 1;
1285                    attr.expandDown = 0;
1286                } else {
1287                    if (desc.type.codeOrData) {
1288                        attr.expandDown = 0;
1289                        attr.readable = desc.type.r;
1290                        attr.writable = 0;
1291                    } else {
1292                        attr.expandDown = desc.type.e;
1293                        attr.readable = 1;
1294                        attr.writable = desc.type.w;
1295                    }
1296                }
1297                Addr base = desc.baseLow | (desc.baseHigh << 24);
1298                Addr limit = desc.limitLow | (desc.limitHigh << 16);
1299                if (desc.g)
1300                    limit = (limit << 12) | mask(12);
1301                SegBaseDest = base;
1302                SegLimitDest = limit;
1303                SegAttrDest = attr;
1304            } else {
1305                SegBaseDest = SegBaseDest;
1306                SegLimitDest = SegLimitDest;
1307                SegAttrDest = SegAttrDest;
1308            }
1309        '''
1310}};
1311