regop.isa revision 5905
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41//
42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53//
54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
62def template MicroRegOpExecute {{
63        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64                Trace::InstRecord *traceData) const
65        {
66            Fault fault = NoFault;
67
68            DPRINTF(X86, "The data size is %d\n", dataSize);
69            %(op_decl)s;
70            %(op_rd)s;
71
72            if(%(cond_check)s)
73            {
74                %(code)s;
75                %(flag_code)s;
76            }
77            else
78            {
79                %(else_code)s;
80            }
81
82            //Write the resulting state to the execution context
83            if(fault == NoFault)
84            {
85                %(op_wb)s;
86            }
87            return fault;
88        }
89}};
90
91def template MicroRegOpImmExecute {{
92        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
93                Trace::InstRecord *traceData) const
94        {
95            Fault fault = NoFault;
96
97            %(op_decl)s;
98            %(op_rd)s;
99
100            if(%(cond_check)s)
101            {
102                %(code)s;
103                %(flag_code)s;
104            }
105            else
106            {
107                %(else_code)s;
108            }
109
110            //Write the resulting state to the execution context
111            if(fault == NoFault)
112            {
113                %(op_wb)s;
114            }
115            return fault;
116        }
117}};
118
119def template MicroRegOpDeclare {{
120    class %(class_name)s : public %(base_class)s
121    {
122      protected:
123        void buildMe();
124
125      public:
126        %(class_name)s(ExtMachInst _machInst,
127                const char * instMnem,
128                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
129                RegIndex _src1, RegIndex _src2, RegIndex _dest,
130                uint8_t _dataSize, uint16_t _ext);
131
132        %(class_name)s(ExtMachInst _machInst,
133                const char * instMnem,
134                RegIndex _src1, RegIndex _src2, RegIndex _dest,
135                uint8_t _dataSize, uint16_t _ext);
136
137        %(BasicExecDeclare)s
138    };
139}};
140
141def template MicroRegOpImmDeclare {{
142
143    class %(class_name)s : public %(base_class)s
144    {
145      protected:
146        void buildMe();
147
148      public:
149        %(class_name)s(ExtMachInst _machInst,
150                const char * instMnem,
151                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
152                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
153                uint8_t _dataSize, uint16_t _ext);
154
155        %(class_name)s(ExtMachInst _machInst,
156                const char * instMnem,
157                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
158                uint8_t _dataSize, uint16_t _ext);
159
160        %(BasicExecDeclare)s
161    };
162}};
163
164def template MicroRegOpConstructor {{
165
166    inline void %(class_name)s::buildMe()
167    {
168        %(constructor)s;
169    }
170
171    inline %(class_name)s::%(class_name)s(
172            ExtMachInst machInst, const char * instMnem,
173            RegIndex _src1, RegIndex _src2, RegIndex _dest,
174            uint8_t _dataSize, uint16_t _ext) :
175        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
176                false, false, false, false,
177                _src1, _src2, _dest, _dataSize, _ext,
178                %(op_class)s)
179    {
180        buildMe();
181    }
182
183    inline %(class_name)s::%(class_name)s(
184            ExtMachInst machInst, const char * instMnem,
185            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
186            RegIndex _src1, RegIndex _src2, RegIndex _dest,
187            uint8_t _dataSize, uint16_t _ext) :
188        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
189                isMicro, isDelayed, isFirst, isLast,
190                _src1, _src2, _dest, _dataSize, _ext,
191                %(op_class)s)
192    {
193        buildMe();
194    }
195}};
196
197def template MicroRegOpImmConstructor {{
198
199    inline void %(class_name)s::buildMe()
200    {
201        %(constructor)s;
202    }
203
204    inline %(class_name)s::%(class_name)s(
205            ExtMachInst machInst, const char * instMnem,
206            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
207            uint8_t _dataSize, uint16_t _ext) :
208        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
209                false, false, false, false,
210                _src1, _imm8, _dest, _dataSize, _ext,
211                %(op_class)s)
212    {
213        buildMe();
214    }
215
216    inline %(class_name)s::%(class_name)s(
217            ExtMachInst machInst, const char * instMnem,
218            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
219            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
220            uint8_t _dataSize, uint16_t _ext) :
221        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
222                isMicro, isDelayed, isFirst, isLast,
223                _src1, _imm8, _dest, _dataSize, _ext,
224                %(op_class)s)
225    {
226        buildMe();
227    }
228}};
229
230output header {{
231    void
232    divide(uint64_t dividend, uint64_t divisor,
233            uint64_t &quotient, uint64_t &remainder);
234
235    enum SegmentSelectorCheck {
236      SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
237      SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
238      SegTRCheck, SegTSSCheck
239    };
240
241    enum LongModeDescriptorType {
242        LDT64 = 2,
243        AvailableTSS64 = 9,
244        BusyTSS64 = 0xb,
245        CallGate64 = 0xc,
246        IntGate64 = 0xe,
247        TrapGate64 = 0xf
248    };
249}};
250
251output decoder {{
252    void
253    divide(uint64_t dividend, uint64_t divisor,
254            uint64_t &quotient, uint64_t &remainder)
255    {
256        //Check for divide by zero.
257        if (divisor == 0)
258            panic("Divide by zero!\\n");
259        //If the divisor is bigger than the dividend, don't do anything.
260        if (divisor <= dividend) {
261            //Shift the divisor so it's msb lines up with the dividend.
262            int dividendMsb = findMsbSet(dividend);
263            int divisorMsb = findMsbSet(divisor);
264            int shift = dividendMsb - divisorMsb;
265            divisor <<= shift;
266            //Compute what we'll add to the quotient if the divisor isn't
267            //now larger than the dividend.
268            uint64_t quotientBit = 1;
269            quotientBit <<= shift;
270            //If we need to step back a bit (no pun intended) because the
271            //divisor got too to large, do that here. This is the "or two"
272            //part of one or two bit division.
273            if (divisor > dividend) {
274                quotientBit >>= 1;
275                divisor >>= 1;
276            }
277            //Decrement the remainder and increment the quotient.
278            quotient += quotientBit;
279            remainder -= divisor;
280        }
281    }
282}};
283
284let {{
285    # Make these empty strings so that concatenating onto
286    # them will always work.
287    header_output = ""
288    decoder_output = ""
289    exec_output = ""
290
291    immTemplates = (
292            MicroRegOpImmDeclare,
293            MicroRegOpImmConstructor,
294            MicroRegOpImmExecute)
295
296    regTemplates = (
297            MicroRegOpDeclare,
298            MicroRegOpConstructor,
299            MicroRegOpExecute)
300
301    class RegOpMeta(type):
302        def buildCppClasses(self, name, Name, suffix, \
303                code, flag_code, cond_check, else_code):
304
305            # Globals to stick the output in
306            global header_output
307            global decoder_output
308            global exec_output
309
310            # Stick all the code together so it can be searched at once
311            allCode = "|".join((code, flag_code, cond_check, else_code))
312
313            # If op2 is used anywhere, make register and immediate versions
314            # of this code.
315            matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
316            match = matcher.search(allCode)
317            if match:
318                typeQual = ""
319                if match.group("typeQual"):
320                    typeQual = match.group("typeQual")
321                src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
322                self.buildCppClasses(name, Name, suffix,
323                        matcher.sub(src2_name, code),
324                        matcher.sub(src2_name, flag_code),
325                        matcher.sub(src2_name, cond_check),
326                        matcher.sub(src2_name, else_code))
327                self.buildCppClasses(name + "i", Name, suffix + "Imm",
328                        matcher.sub("imm8", code),
329                        matcher.sub("imm8", flag_code),
330                        matcher.sub("imm8", cond_check),
331                        matcher.sub("imm8", else_code))
332                return
333
334            # If there's something optional to do with flags, generate
335            # a version without it and fix up this version to use it.
336            if flag_code != "" or cond_check != "true":
337                self.buildCppClasses(name, Name, suffix,
338                        code, "", "true", else_code)
339                suffix = "Flags" + suffix
340
341            # If psrc1 or psrc2 is used, we need to actually insert code to
342            # compute it.
343            matcher = re.compile("(?<!\w)psrc1(?!\w)")
344            if matcher.search(allCode):
345                code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
346            matcher = re.compile("(?<!\w)psrc2(?!\w)")
347            if matcher.search(allCode):
348                code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
349            # Also make available versions which do sign extension
350            matcher = re.compile("(?<!\w)spsrc1(?!\w)")
351            if matcher.search(allCode):
352                code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
353            matcher = re.compile("(?<!\w)spsrc2(?!\w)")
354            if matcher.search(allCode):
355                code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
356
357            base = "X86ISA::RegOp"
358
359            # If imm8 shows up in the code, use the immediate templates, if
360            # not, hopefully the register ones will be correct.
361            templates = regTemplates
362            matcher = re.compile("(?<!\w)imm8(?!\w)")
363            if matcher.search(allCode):
364                base += "Imm"
365                templates = immTemplates
366
367            # Get everything ready for the substitution
368            iop = InstObjParams(name, Name + suffix, base,
369                    {"code" : code,
370                     "flag_code" : flag_code,
371                     "cond_check" : cond_check,
372                     "else_code" : else_code})
373
374            # Generate the actual code (finally!)
375            header_output += templates[0].subst(iop)
376            decoder_output += templates[1].subst(iop)
377            exec_output += templates[2].subst(iop)
378
379
380        def __new__(mcls, Name, bases, dict):
381            abstract = False
382            name = Name.lower()
383            if "abstract" in dict:
384                abstract = dict['abstract']
385                del dict['abstract']
386
387            cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
388            if not abstract:
389                cls.className = Name
390                cls.base_mnemonic = name
391                code = cls.code
392                flag_code = cls.flag_code
393                cond_check = cls.cond_check
394                else_code = cls.else_code
395
396                # Set up the C++ classes
397                mcls.buildCppClasses(cls, name, Name, "",
398                        code, flag_code, cond_check, else_code)
399
400                # Hook into the microassembler dict
401                global microopClasses
402                microopClasses[name] = cls
403
404                allCode = "|".join((code, flag_code, cond_check, else_code))
405
406                # If op2 is used anywhere, make register and immediate versions
407                # of this code.
408                matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
409                if matcher.search(allCode):
410                    microopClasses[name + 'i'] = cls
411            return cls
412
413
414    class RegOp(X86Microop):
415        __metaclass__ = RegOpMeta
416        # This class itself doesn't act as a microop
417        abstract = True
418
419        # Default template parameter values
420        flag_code = ""
421        cond_check = "true"
422        else_code = ";"
423
424        def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
425            self.dest = dest
426            self.src1 = src1
427            self.op2 = op2
428            self.flags = flags
429            self.dataSize = dataSize
430            if flags is None:
431                self.ext = 0
432            else:
433                if not isinstance(flags, (list, tuple)):
434                    raise Exception, "flags must be a list or tuple of flags"
435                self.ext = " | ".join(flags)
436                self.className += "Flags"
437
438        def getAllocator(self, *microFlags):
439            className = self.className
440            if self.mnemonic == self.base_mnemonic + 'i':
441                className += "Imm"
442            allocator = '''new %(class_name)s(machInst, macrocodeBlock
443                    %(flags)s, %(src1)s, %(op2)s, %(dest)s,
444                    %(dataSize)s, %(ext)s)''' % {
445                "class_name" : className,
446                "flags" : self.microFlagsText(microFlags),
447                "src1" : self.src1, "op2" : self.op2,
448                "dest" : self.dest,
449                "dataSize" : self.dataSize,
450                "ext" : self.ext}
451            return allocator
452
453    class LogicRegOp(RegOp):
454        abstract = True
455        flag_code = '''
456            //Don't have genFlags handle the OF or CF bits
457            uint64_t mask = CFBit | ECFBit | OFBit;
458            ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
459            //If a logic microop wants to set these, it wants to set them to 0.
460            ccFlagBits &= ~(CFBit & ext);
461            ccFlagBits &= ~(ECFBit & ext);
462            ccFlagBits &= ~(OFBit & ext);
463        '''
464
465    class FlagRegOp(RegOp):
466        abstract = True
467        flag_code = \
468            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
469
470    class SubRegOp(RegOp):
471        abstract = True
472        flag_code = \
473            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
474
475    class CondRegOp(RegOp):
476        abstract = True
477        cond_check = "checkCondition(ccFlagBits, ext)"
478
479    class RdRegOp(RegOp):
480        abstract = True
481        def __init__(self, dest, src1=None, dataSize="env.dataSize"):
482            if not src1:
483                src1 = dest
484            super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
485
486    class WrRegOp(RegOp):
487        abstract = True
488        def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
489            super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
490
491    class Add(FlagRegOp):
492        code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
493
494    class Or(LogicRegOp):
495        code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
496
497    class Adc(FlagRegOp):
498        code = '''
499            CCFlagBits flags = ccFlagBits;
500            DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
501            '''
502
503    class Sbb(SubRegOp):
504        code = '''
505            CCFlagBits flags = ccFlagBits;
506            DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
507            '''
508
509    class And(LogicRegOp):
510        code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
511
512    class Sub(SubRegOp):
513        code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
514
515    class Xor(LogicRegOp):
516        code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
517
518    # Neither of these is quite correct because it assumes that right shifting
519    # a signed or unsigned value does sign or zero extension respectively.
520    # The C standard says that what happens on a right shift with a 1 in the
521    # MSB position is undefined. On x86 and under likely most compilers the
522    # "right thing" happens, but this isn't a guarantee.
523    class Mul1s(WrRegOp):
524        code = '''
525            ProdLow = psrc1 * op2;
526            int halfSize = (dataSize * 8) / 2;
527            int64_t spsrc1_h = spsrc1 >> halfSize;
528            int64_t spsrc1_l = spsrc1 & mask(halfSize);
529            int64_t spsrc2_h = sop2 >> halfSize;
530            int64_t spsrc2_l = sop2 & mask(halfSize);
531            ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l +
532                      ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) +
533                     spsrc1_h * spsrc2_h;
534            '''
535
536    class Mul1u(WrRegOp):
537        code = '''
538            ProdLow = psrc1 * op2;
539            int halfSize = (dataSize * 8) / 2;
540            uint64_t psrc1_h = psrc1 >> halfSize;
541            uint64_t psrc1_l = psrc1 & mask(halfSize);
542            uint64_t psrc2_h = op2 >> halfSize;
543            uint64_t psrc2_l = op2 & mask(halfSize);
544            ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
545                      ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
546                     psrc1_h * psrc2_h;
547            '''
548
549    class Mulel(RdRegOp):
550        code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
551
552    class Muleh(RdRegOp):
553        def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
554            if not src1:
555                src1 = dest
556            super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize)
557        code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
558        flag_code = '''
559            if (ProdHi)
560                ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
561            else
562                ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
563        '''
564
565    # One or two bit divide
566    class Div1(WrRegOp):
567        code = '''
568            //These are temporaries so that modifying them later won't make
569            //the ISA parser think they're also sources.
570            uint64_t quotient = 0;
571            uint64_t remainder = psrc1;
572            //Similarly, this is a temporary so changing it doesn't make it
573            //a source.
574            uint64_t divisor = op2;
575            //This is a temporary just for consistency and clarity.
576            uint64_t dividend = remainder;
577            //Do the division.
578            divide(dividend, divisor, quotient, remainder);
579            //Record the final results.
580            Remainder = remainder;
581            Quotient = quotient;
582            Divisor = divisor;
583            '''
584
585    # Step divide
586    class Div2(RegOp):
587        code = '''
588            uint64_t dividend = Remainder;
589            uint64_t divisor = Divisor;
590            uint64_t quotient = Quotient;
591            uint64_t remainder = dividend;
592            int remaining = op2;
593            //If we overshot, do nothing. This lets us unrool division loops a
594            //little.
595            if (remaining) {
596                //Shift in bits from the low order portion of the dividend
597                while(dividend < divisor && remaining) {
598                    dividend = (dividend << 1) | bits(SrcReg1, remaining - 1);
599                    quotient <<= 1;
600                    remaining--;
601                }
602                remainder = dividend;
603                //Do the division.
604                divide(dividend, divisor, quotient, remainder);
605            }
606            //Keep track of how many bits there are still to pull in.
607            DestReg = merge(DestReg, remaining, dataSize);
608            //Record the final results
609            Remainder = remainder;
610            Quotient = quotient;
611        '''
612        flag_code = '''
613            if (DestReg == 0)
614                ccFlagBits = ccFlagBits | (ext & EZFBit);
615            else
616                ccFlagBits = ccFlagBits & ~(ext & EZFBit);
617        '''
618
619    class Divq(RdRegOp):
620        code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
621
622    class Divr(RdRegOp):
623        code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
624
625    class Mov(CondRegOp):
626        code = 'DestReg = merge(SrcReg1, op2, dataSize)'
627        else_code = 'DestReg=DestReg;'
628
629    # Shift instructions
630
631    class Sll(RegOp):
632        code = '''
633            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
634            DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
635            '''
636        flag_code = '''
637            // If the shift amount is zero, no flags should be modified.
638            if (shiftAmt) {
639                //Zero out any flags we might modify. This way we only have to
640                //worry about setting them.
641                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
642                int CFBits = 0;
643                //Figure out if we -would- set the CF bits if requested.
644                if (bits(SrcReg1, dataSize * 8 - shiftAmt))
645                    CFBits = 1;
646                //If some combination of the CF bits need to be set, set them.
647                if ((ext & (CFBit | ECFBit)) && CFBits)
648                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
649                //Figure out what the OF bit should be.
650                if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
651                    ccFlagBits = ccFlagBits | OFBit;
652                //Use the regular mechanisms to calculate the other flags.
653                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
654                        DestReg, psrc1, op2);
655            }
656        '''
657
658    class Srl(RegOp):
659        code = '''
660            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
661            // Because what happens to the bits shift -in- on a right shift
662            // is not defined in the C/C++ standard, we have to mask them out
663            // to be sure they're zero.
664            uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
665            DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
666            '''
667        flag_code = '''
668            // If the shift amount is zero, no flags should be modified.
669            if (shiftAmt) {
670                //Zero out any flags we might modify. This way we only have to
671                //worry about setting them.
672                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
673                //If some combination of the CF bits need to be set, set them.
674                if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
675                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
676                //Figure out what the OF bit should be.
677                if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
678                    ccFlagBits = ccFlagBits | OFBit;
679                //Use the regular mechanisms to calculate the other flags.
680                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
681                        DestReg, psrc1, op2);
682            }
683        '''
684
685    class Sra(RegOp):
686        code = '''
687            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
688            // Because what happens to the bits shift -in- on a right shift
689            // is not defined in the C/C++ standard, we have to sign extend
690            // them manually to be sure.
691            uint64_t arithMask =
692                -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
693            DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
694            '''
695        flag_code = '''
696            // If the shift amount is zero, no flags should be modified.
697            if (shiftAmt) {
698                //Zero out any flags we might modify. This way we only have to
699                //worry about setting them.
700                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
701                //If some combination of the CF bits need to be set, set them.
702                if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
703                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
704                //Use the regular mechanisms to calculate the other flags.
705                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
706                        DestReg, psrc1, op2);
707            }
708        '''
709
710    class Ror(RegOp):
711        code = '''
712            uint8_t shiftAmt =
713                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
714            if(shiftAmt)
715            {
716                uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
717                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
718                DestReg = merge(DestReg, top | bottom, dataSize);
719            }
720            else
721                DestReg = DestReg;
722            '''
723        flag_code = '''
724            // If the shift amount is zero, no flags should be modified.
725            if (shiftAmt) {
726                //Zero out any flags we might modify. This way we only have to
727                //worry about setting them.
728                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
729                //Find the most and second most significant bits of the result.
730                int msb = bits(DestReg, dataSize * 8 - 1);
731                int smsb = bits(DestReg, dataSize * 8 - 2);
732                //If some combination of the CF bits need to be set, set them.
733                if ((ext & (CFBit | ECFBit)) && msb)
734                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
735                //Figure out what the OF bit should be.
736                if ((ext & OFBit) && (msb ^ smsb))
737                    ccFlagBits = ccFlagBits | OFBit;
738                //Use the regular mechanisms to calculate the other flags.
739                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
740                        DestReg, psrc1, op2);
741            }
742        '''
743
744    class Rcr(RegOp):
745        code = '''
746            uint8_t shiftAmt =
747                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
748            if(shiftAmt)
749            {
750                CCFlagBits flags = ccFlagBits;
751                uint64_t top = flags.cf << (dataSize * 8 - shiftAmt);
752                if(shiftAmt > 1)
753                    top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
754                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
755                DestReg = merge(DestReg, top | bottom, dataSize);
756            }
757            else
758                DestReg = DestReg;
759            '''
760        flag_code = '''
761            // If the shift amount is zero, no flags should be modified.
762            if (shiftAmt) {
763                //Zero out any flags we might modify. This way we only have to
764                //worry about setting them.
765                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
766                //Figure out what the OF bit should be.
767                if ((ext & OFBit) && ((ccFlagBits & CFBit) ^
768                                      bits(SrcReg1, dataSize * 8 - 1)))
769                    ccFlagBits = ccFlagBits | OFBit;
770                //If some combination of the CF bits need to be set, set them.
771                if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
772                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
773                //Use the regular mechanisms to calculate the other flags.
774                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
775                        DestReg, psrc1, op2);
776            }
777        '''
778
779    class Rol(RegOp):
780        code = '''
781            uint8_t shiftAmt =
782                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
783            if(shiftAmt)
784            {
785                uint64_t top = psrc1 << shiftAmt;
786                uint64_t bottom =
787                    bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
788                DestReg = merge(DestReg, top | bottom, dataSize);
789            }
790            else
791                DestReg = DestReg;
792            '''
793        flag_code = '''
794            // If the shift amount is zero, no flags should be modified.
795            if (shiftAmt) {
796                //Zero out any flags we might modify. This way we only have to
797                //worry about setting them.
798                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
799                //The CF bits, if set, would be set to the lsb of the result.
800                int lsb = DestReg & 0x1;
801                int msb = bits(DestReg, dataSize * 8 - 1);
802                //If some combination of the CF bits need to be set, set them.
803                if ((ext & (CFBit | ECFBit)) && lsb)
804                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
805                //Figure out what the OF bit should be.
806                if ((ext & OFBit) && (msb ^ lsb))
807                    ccFlagBits = ccFlagBits | OFBit;
808                //Use the regular mechanisms to calculate the other flags.
809                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
810                        DestReg, psrc1, op2);
811            }
812        '''
813
814    class Rcl(RegOp):
815        code = '''
816            uint8_t shiftAmt =
817                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
818            if(shiftAmt)
819            {
820                CCFlagBits flags = ccFlagBits;
821                uint64_t top = psrc1 << shiftAmt;
822                uint64_t bottom = flags.cf << (shiftAmt - 1);
823                if(shiftAmt > 1)
824                    bottom |=
825                        bits(psrc1, dataSize * 8 - 1,
826                                   dataSize * 8 - shiftAmt + 1);
827                DestReg = merge(DestReg, top | bottom, dataSize);
828            }
829            else
830                DestReg = DestReg;
831            '''
832        flag_code = '''
833            // If the shift amount is zero, no flags should be modified.
834            if (shiftAmt) {
835                //Zero out any flags we might modify. This way we only have to
836                //worry about setting them.
837                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
838                int msb = bits(DestReg, dataSize * 8 - 1);
839                int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt);
840                //If some combination of the CF bits need to be set, set them.
841                if ((ext & (CFBit | ECFBit)) && CFBits)
842                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
843                //Figure out what the OF bit should be.
844                if ((ext & OFBit) && (msb ^ CFBits))
845                    ccFlagBits = ccFlagBits | OFBit;
846                //Use the regular mechanisms to calculate the other flags.
847                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
848                        DestReg, psrc1, op2);
849            }
850        '''
851
852    class Wrip(WrRegOp, CondRegOp):
853        code = 'RIP = psrc1 + sop2 + CSBase'
854        else_code="RIP = RIP;"
855
856    class Wruflags(WrRegOp):
857        code = 'ccFlagBits = psrc1 ^ op2'
858
859    class Wrflags(WrRegOp):
860        code = '''
861            MiscReg newFlags = psrc1 ^ op2;
862            MiscReg userFlagMask = 0xDD5;
863            // Get only the user flags
864            ccFlagBits = newFlags & userFlagMask;
865            // Get everything else
866            nccFlagBits = newFlags & ~userFlagMask;
867        '''
868
869    class Rdip(RdRegOp):
870        code = 'DestReg = RIP - CSBase'
871
872    class Ruflags(RdRegOp):
873        code = 'DestReg = ccFlagBits'
874
875    class Rflags(RdRegOp):
876        code = 'DestReg = ccFlagBits | nccFlagBits'
877
878    class Ruflag(RegOp):
879        code = '''
880            int flag = bits(ccFlagBits, imm8);
881            DestReg = merge(DestReg, flag, dataSize);
882            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
883                                       (ccFlagBits & ~EZFBit);
884            '''
885        def __init__(self, dest, imm, flags=None, \
886                dataSize="env.dataSize"):
887            super(Ruflag, self).__init__(dest, \
888                    "NUM_INTREGS", imm, flags, dataSize)
889
890    class Rflag(RegOp):
891        code = '''
892            MiscReg flagMask = 0x3F7FDD5;
893            MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
894            int flag = bits(flags, imm8);
895            DestReg = merge(DestReg, flag, dataSize);
896            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
897                                       (ccFlagBits & ~EZFBit);
898            '''
899        def __init__(self, dest, imm, flags=None, \
900                dataSize="env.dataSize"):
901            super(Rflag, self).__init__(dest, \
902                    "NUM_INTREGS", imm, flags, dataSize)
903
904    class Sext(RegOp):
905        code = '''
906            IntReg val = psrc1;
907            // Mask the bit position so that it wraps.
908            int bitPos = op2 & (dataSize * 8 - 1);
909            int sign_bit = bits(val, bitPos, bitPos);
910            uint64_t maskVal = mask(bitPos+1);
911            val = sign_bit ? (val | ~maskVal) : (val & maskVal);
912            DestReg = merge(DestReg, val, dataSize);
913            '''
914        flag_code = '''
915            if (!sign_bit)
916                ccFlagBits = ccFlagBits &
917                    ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
918            else
919                ccFlagBits = ccFlagBits |
920                    (ext & (CFBit | ECFBit | ZFBit | EZFBit));
921            '''
922
923    class Zext(RegOp):
924        code = 'DestReg = bits(psrc1, op2, 0);'
925
926    class Rdcr(RegOp):
927        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
928            super(Rdcr, self).__init__(dest, \
929                    src1, "NUM_INTREGS", flags, dataSize)
930        code = '''
931            if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
932                fault = new InvalidOpcode();
933            } else {
934                DestReg = ControlSrc1;
935            }
936        '''
937
938    class Wrcr(RegOp):
939        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
940            super(Wrcr, self).__init__(dest, \
941                    src1, "NUM_INTREGS", flags, dataSize)
942        code = '''
943            if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
944                fault = new InvalidOpcode();
945            } else {
946                // There are *s in the line below so it doesn't confuse the
947                // parser. They may be unnecessary.
948                //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
949                MiscReg newVal = psrc1;
950
951                // Check for any modifications that would cause a fault.
952                switch(dest) {
953                  case 0:
954                    {
955                        Efer efer = EferOp;
956                        CR0 cr0 = newVal;
957                        CR4 oldCr4 = CR4Op;
958                        if (bits(newVal, 63, 32) ||
959                                (!cr0.pe && cr0.pg) ||
960                                (!cr0.cd && cr0.nw) ||
961                                (cr0.pg && efer.lme && !oldCr4.pae))
962                            fault = new GeneralProtection(0);
963                    }
964                    break;
965                  case 2:
966                    break;
967                  case 3:
968                    break;
969                  case 4:
970                    {
971                        CR4 cr4 = newVal;
972                        // PAE can't be disabled in long mode.
973                        if (bits(newVal, 63, 11) ||
974                                (machInst.mode.mode == LongMode && !cr4.pae))
975                            fault = new GeneralProtection(0);
976                    }
977                    break;
978                  case 8:
979                    {
980                        if (bits(newVal, 63, 4))
981                            fault = new GeneralProtection(0);
982                    }
983                  default:
984                    panic("Unrecognized control register %d.\\n", dest);
985                }
986                ControlDest = newVal;
987            }
988            '''
989
990    # Microops for manipulating segmentation registers
991    class SegOp(CondRegOp):
992        abstract = True
993        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
994            super(SegOp, self).__init__(dest, \
995                    src1, "NUM_INTREGS", flags, dataSize)
996
997    class Wrbase(SegOp):
998        code = '''
999            SegBaseDest = psrc1;
1000        '''
1001
1002    class Wrlimit(SegOp):
1003        code = '''
1004            SegLimitDest = psrc1;
1005        '''
1006
1007    class Wrsel(SegOp):
1008        code = '''
1009            SegSelDest = psrc1;
1010        '''
1011
1012    class WrAttr(SegOp):
1013        code = '''
1014            SegAttrDest = psrc1;
1015        '''
1016
1017    class Rdbase(SegOp):
1018        code = '''
1019            DestReg = SegBaseSrc1;
1020        '''
1021
1022    class Rdlimit(SegOp):
1023        code = '''
1024            DestReg = SegLimitSrc1;
1025        '''
1026
1027    class RdAttr(SegOp):
1028        code = '''
1029            DestReg = SegAttrSrc1;
1030        '''
1031
1032    class Rdsel(SegOp):
1033        code = '''
1034            DestReg = SegSelSrc1;
1035        '''
1036
1037    class Rdval(RegOp):
1038        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1039            super(Rdval, self).__init__(dest, \
1040                    src1, "NUM_INTREGS", flags, dataSize)
1041        code = '''
1042            DestReg = MiscRegSrc1;
1043        '''
1044
1045    class Wrval(RegOp):
1046        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1047            super(Wrval, self).__init__(dest, \
1048                    src1, "NUM_INTREGS", flags, dataSize)
1049        code = '''
1050            MiscRegDest = SrcReg1;
1051        '''
1052
1053    class Chks(RegOp):
1054        def __init__(self, dest, src1, src2=0,
1055                flags=None, dataSize="env.dataSize"):
1056            super(Chks, self).__init__(dest,
1057                    src1, src2, flags, dataSize)
1058        code = '''
1059            // The selector is in source 1 and can be at most 16 bits.
1060            SegSelector selector = DestReg;
1061            SegDescriptor desc = SrcReg1;
1062            HandyM5Reg m5reg = M5Reg;
1063
1064            switch (imm8)
1065            {
1066              case SegNoCheck:
1067                break;
1068              case SegCSCheck:
1069                panic("CS checks for far calls/jumps not implemented.\\n");
1070                break;
1071              case SegCallGateCheck:
1072                panic("CS checks for far calls/jumps through call gates"
1073                        "not implemented.\\n");
1074                break;
1075              case SegSoftIntGateCheck:
1076                // Check permissions.
1077                if (desc.dpl < m5reg.cpl) {
1078                    fault = new GeneralProtection(selector);
1079                }
1080                // Fall through on purpose
1081              case SegIntGateCheck:
1082                // Make sure the gate's the right type.
1083                if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
1084                        ((desc.type & 0x6) != 0x6)) {
1085                    fault = new GeneralProtection(0);
1086                }
1087                break;
1088              case SegSSCheck:
1089                if (selector.si || selector.ti) {
1090                    if (!desc.p) {
1091                        fault = new StackFault(selector);
1092                    }
1093                } else {
1094                    if ((m5reg.submode != SixtyFourBitMode ||
1095                                m5reg.cpl == 3) ||
1096                            !(desc.s == 1 &&
1097                            desc.type.codeOrData == 0 && desc.type.w) ||
1098                            (desc.dpl != m5reg.cpl) ||
1099                            (selector.rpl != m5reg.cpl)) {
1100                        fault = new GeneralProtection(selector);
1101                    }
1102                }
1103                break;
1104              case SegIretCheck:
1105                {
1106                    if ((!selector.si && !selector.ti) ||
1107                            (selector.rpl < m5reg.cpl) ||
1108                            !(desc.s == 1 && desc.type.codeOrData == 1) ||
1109                            (!desc.type.c && desc.dpl != selector.rpl) ||
1110                            (desc.type.c && desc.dpl > selector.rpl)) {
1111                        fault = new GeneralProtection(selector);
1112                    } else if (!desc.p) {
1113                        fault = new SegmentNotPresent(selector);
1114                    }
1115                    break;
1116                }
1117              case SegIntCSCheck:
1118                if (m5reg.mode == LongMode) {
1119                    if (desc.l != 1 || desc.d != 0) {
1120                        fault = new GeneralProtection(selector);
1121                    }
1122                } else {
1123                    panic("Interrupt CS checks not implemented "
1124                            "in legacy mode.\\n");
1125                }
1126                break;
1127              case SegTRCheck:
1128                if (!selector.si || selector.ti) {
1129                    fault = new GeneralProtection(selector);
1130                }
1131                break;
1132              case SegTSSCheck:
1133                if (!desc.p) {
1134                    fault = new SegmentNotPresent(selector);
1135                } else if (!(desc.type == 0x9 ||
1136                        (desc.type == 1 &&
1137                         m5reg.mode != LongMode))) {
1138
1139                }
1140                break;
1141              default:
1142                panic("Undefined segment check type.\\n");
1143            }
1144        '''
1145        flag_code = '''
1146            // Check for a NULL selector and set ZF,EZF appropriately.
1147            ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1148            if (!selector.si && !selector.ti)
1149                ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1150        '''
1151
1152    class Wrdh(RegOp):
1153        code = '''
1154            SegDescriptor desc = SrcReg1;
1155
1156            uint64_t target = bits(SrcReg2, 31, 0) << 32;
1157            switch(desc.type) {
1158              case LDT64:
1159              case AvailableTSS64:
1160              case BusyTSS64:
1161                replaceBits(target, 23, 0, desc.baseLow);
1162                replaceBits(target, 31, 24, desc.baseHigh);
1163                break;
1164              case CallGate64:
1165              case IntGate64:
1166              case TrapGate64:
1167                replaceBits(target, 15, 0, bits(desc, 15, 0));
1168                replaceBits(target, 31, 16, bits(desc, 63, 48));
1169                break;
1170              default:
1171                panic("Wrdh used with wrong descriptor type!\\n");
1172            }
1173            DestReg = target;
1174        '''
1175
1176    class Wrtsc(WrRegOp):
1177        code = '''
1178            TscOp = psrc1;
1179        '''
1180
1181    class Rdtsc(RdRegOp):
1182        code = '''
1183            DestReg = TscOp;
1184        '''
1185
1186    class Rdm5reg(RdRegOp):
1187        code = '''
1188            DestReg = M5Reg;
1189        '''
1190
1191    class Wrdl(RegOp):
1192        code = '''
1193            SegDescriptor desc = SrcReg1;
1194            SegSelector selector = SrcReg2;
1195            if (selector.si || selector.ti) {
1196                SegAttr attr = 0;
1197                attr.dpl = desc.dpl;
1198                attr.defaultSize = desc.d;
1199                if (!desc.s) {
1200                    // The expand down bit happens to be set for gates.
1201                    if (desc.type.e) {
1202                        panic("Gate descriptor encountered.\\n");
1203                    }
1204                    attr.readable = 1;
1205                    attr.writable = 1;
1206                } else {
1207                    if (!desc.p)
1208                        panic("Segment not present.\\n");
1209                    if (desc.type.codeOrData) {
1210                        attr.readable = desc.type.r;
1211                        attr.longMode = desc.l;
1212                    } else {
1213                        attr.expandDown = desc.type.e;
1214                        attr.readable = 1;
1215                        attr.writable = desc.type.w;
1216                    }
1217                }
1218                Addr base = desc.baseLow | (desc.baseHigh << 24);
1219                Addr limit = desc.limitLow | (desc.limitHigh << 16);
1220                if (desc.g)
1221                    limit = (limit << 12) | mask(12);
1222                SegBaseDest = base;
1223                SegLimitDest = limit;
1224                SegAttrDest = attr;
1225            } else {
1226                SegBaseDest = SegBaseDest;
1227                SegLimitDest = SegLimitDest;
1228                SegAttrDest = SegAttrDest;
1229            }
1230        '''
1231}};
1232