regop.isa revision 5058
1// Copyright (c) 2007 The Hewlett-Packard Development Company
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3//
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41//
42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53//
54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
62def template MicroRegOpExecute {{
63        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64                Trace::InstRecord *traceData) const
65        {
66            Fault fault = NoFault;
67
68            DPRINTF(X86, "The data size is %d\n", dataSize);
69            %(op_decl)s;
70            %(op_rd)s;
71
72            if(%(cond_check)s)
73            {
74                %(code)s;
75                %(flag_code)s;
76            }
77            else
78            {
79                %(else_code)s;
80            }
81
82            //Write the resulting state to the execution context
83            if(fault == NoFault)
84            {
85                %(op_wb)s;
86            }
87            return fault;
88        }
89}};
90
91def template MicroRegOpImmExecute {{
92        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
93                Trace::InstRecord *traceData) const
94        {
95            Fault fault = NoFault;
96
97            %(op_decl)s;
98            %(op_rd)s;
99
100            if(%(cond_check)s)
101            {
102                %(code)s;
103                %(flag_code)s;
104            }
105            else
106            {
107                %(else_code)s;
108            }
109
110            //Write the resulting state to the execution context
111            if(fault == NoFault)
112            {
113                %(op_wb)s;
114            }
115            return fault;
116        }
117}};
118
119def template MicroRegOpDeclare {{
120    class %(class_name)s : public %(base_class)s
121    {
122      protected:
123        void buildMe();
124
125      public:
126        %(class_name)s(ExtMachInst _machInst,
127                const char * instMnem,
128                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
129                RegIndex _src1, RegIndex _src2, RegIndex _dest,
130                uint8_t _dataSize, uint16_t _ext);
131
132        %(class_name)s(ExtMachInst _machInst,
133                const char * instMnem,
134                RegIndex _src1, RegIndex _src2, RegIndex _dest,
135                uint8_t _dataSize, uint16_t _ext);
136
137        %(BasicExecDeclare)s
138    };
139}};
140
141def template MicroRegOpImmDeclare {{
142
143    class %(class_name)s : public %(base_class)s
144    {
145      protected:
146        void buildMe();
147
148      public:
149        %(class_name)s(ExtMachInst _machInst,
150                const char * instMnem,
151                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
152                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
153                uint8_t _dataSize, uint16_t _ext);
154
155        %(class_name)s(ExtMachInst _machInst,
156                const char * instMnem,
157                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
158                uint8_t _dataSize, uint16_t _ext);
159
160        %(BasicExecDeclare)s
161    };
162}};
163
164def template MicroRegOpConstructor {{
165
166    inline void %(class_name)s::buildMe()
167    {
168        %(constructor)s;
169    }
170
171    inline %(class_name)s::%(class_name)s(
172            ExtMachInst machInst, const char * instMnem,
173            RegIndex _src1, RegIndex _src2, RegIndex _dest,
174            uint8_t _dataSize, uint16_t _ext) :
175        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
176                false, false, false, false,
177                _src1, _src2, _dest, _dataSize, _ext,
178                %(op_class)s)
179    {
180        buildMe();
181    }
182
183    inline %(class_name)s::%(class_name)s(
184            ExtMachInst machInst, const char * instMnem,
185            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
186            RegIndex _src1, RegIndex _src2, RegIndex _dest,
187            uint8_t _dataSize, uint16_t _ext) :
188        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
189                isMicro, isDelayed, isFirst, isLast,
190                _src1, _src2, _dest, _dataSize, _ext,
191                %(op_class)s)
192    {
193        buildMe();
194    }
195}};
196
197def template MicroRegOpImmConstructor {{
198
199    inline void %(class_name)s::buildMe()
200    {
201        %(constructor)s;
202    }
203
204    inline %(class_name)s::%(class_name)s(
205            ExtMachInst machInst, const char * instMnem,
206            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
207            uint8_t _dataSize, uint16_t _ext) :
208        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
209                false, false, false, false,
210                _src1, _imm8, _dest, _dataSize, _ext,
211                %(op_class)s)
212    {
213        buildMe();
214    }
215
216    inline %(class_name)s::%(class_name)s(
217            ExtMachInst machInst, const char * instMnem,
218            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
219            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
220            uint8_t _dataSize, uint16_t _ext) :
221        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
222                isMicro, isDelayed, isFirst, isLast,
223                _src1, _imm8, _dest, _dataSize, _ext,
224                %(op_class)s)
225    {
226        buildMe();
227    }
228}};
229
230let {{
231    # Make these empty strings so that concatenating onto
232    # them will always work.
233    header_output = ""
234    decoder_output = ""
235    exec_output = ""
236
237    immTemplates = (
238            MicroRegOpImmDeclare,
239            MicroRegOpImmConstructor,
240            MicroRegOpImmExecute)
241
242    regTemplates = (
243            MicroRegOpDeclare,
244            MicroRegOpConstructor,
245            MicroRegOpExecute)
246
247    class RegOpMeta(type):
248        def buildCppClasses(self, name, Name, suffix, \
249                code, flag_code, cond_check, else_code):
250
251            # Globals to stick the output in
252            global header_output
253            global decoder_output
254            global exec_output
255
256            # Stick all the code together so it can be searched at once
257            allCode = "|".join((code, flag_code, cond_check, else_code))
258
259            # If op2 is used anywhere, make register and immediate versions
260            # of this code.
261            matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
262            if matcher.search(allCode):
263                self.buildCppClasses(name, Name, suffix,
264                        matcher.sub("psrc2", code),
265                        matcher.sub("psrc2", flag_code),
266                        matcher.sub("psrc2", cond_check),
267                        matcher.sub("psrc2", else_code))
268                self.buildCppClasses(name + "i", Name, suffix + "Imm",
269                        matcher.sub("imm8", code),
270                        matcher.sub("imm8", flag_code),
271                        matcher.sub("imm8", cond_check),
272                        matcher.sub("imm8", else_code))
273                return
274
275            # If there's something optional to do with flags, generate
276            # a version without it and fix up this version to use it.
277            if flag_code is not "" or cond_check is not "true":
278                self.buildCppClasses(name, Name, suffix,
279                        code, "", "true", else_code)
280                suffix = "Flags" + suffix
281
282            # If psrc1 or psrc2 is used, we need to actually insert code to
283            # compute it.
284            matcher = re.compile("(?<!\w)psrc1(?!\w)")
285            if matcher.search(allCode):
286                code = "IntReg psrc1 = pick(SrcReg1, 0, dataSize);" + code
287            matcher = re.compile("(?<!\w)psrc2(?!\w)")
288            if matcher.search(allCode):
289                code = "IntReg psrc2 = pick(SrcReg2, 1, dataSize);" + code
290
291            base = "X86ISA::RegOp"
292
293            # If imm8 shows up in the code, use the immediate templates, if
294            # not, hopefully the register ones will be correct.
295            templates = regTemplates
296            matcher = re.compile("(?<!\w)imm8(?!\w)")
297            if matcher.search(allCode):
298                base += "Imm"
299                templates = immTemplates
300
301            # Get everything ready for the substitution
302            iop = InstObjParams(name, Name + suffix, base,
303                    {"code" : code,
304                     "flag_code" : flag_code,
305                     "cond_check" : cond_check,
306                     "else_code" : else_code})
307
308            # Generate the actual code (finally!)
309            header_output += templates[0].subst(iop)
310            decoder_output += templates[1].subst(iop)
311            exec_output += templates[2].subst(iop)
312
313
314        def __new__(mcls, Name, bases, dict):
315            abstract = False
316            name = Name.lower()
317            if "abstract" in dict:
318                abstract = dict['abstract']
319                del dict['abstract']
320
321            cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
322            if not abstract:
323                cls.className = Name
324                cls.base_mnemonic = name
325                code = cls.code
326                flag_code = cls.flag_code
327                cond_check = cls.cond_check
328                else_code = cls.else_code
329
330                # Set up the C++ classes
331                mcls.buildCppClasses(cls, name, Name, "",
332                        code, flag_code, cond_check, else_code)
333
334                # Hook into the microassembler dict
335                global microopClasses
336                microopClasses[name] = cls
337
338                allCode = "|".join((code, flag_code, cond_check, else_code))
339
340                # If op2 is used anywhere, make register and immediate versions
341                # of this code.
342                matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
343                if matcher.search(allCode):
344                    microopClasses[name + 'i'] = cls
345            return cls
346
347
348    class RegOp(X86Microop):
349        __metaclass__ = RegOpMeta
350        # This class itself doesn't act as a microop
351        abstract = True
352
353        # Default template parameter values
354        flag_code = ""
355        cond_check = "true"
356        else_code = ";"
357
358        def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
359            self.dest = dest
360            self.src1 = src1
361            self.op2 = op2
362            self.flags = flags
363            self.dataSize = dataSize
364            if flags is None:
365                self.ext = 0
366            else:
367                if not isinstance(flags, (list, tuple)):
368                    raise Exception, "flags must be a list or tuple of flags"
369                self.ext = " | ".join(flags)
370                self.className += "Flags"
371
372        def getAllocator(self, *microFlags):
373            className = self.className
374            if self.mnemonic == self.base_mnemonic + 'i':
375                className += "Imm"
376            allocator = '''new %(class_name)s(machInst, mnemonic
377                    %(flags)s, %(src1)s, %(op2)s, %(dest)s,
378                    %(dataSize)s, %(ext)s)''' % {
379                "class_name" : className,
380                "flags" : self.microFlagsText(microFlags),
381                "src1" : self.src1, "op2" : self.op2,
382                "dest" : self.dest,
383                "dataSize" : self.dataSize,
384                "ext" : self.ext}
385            return allocator
386
387    class LogicRegOp(RegOp):
388        abstract = True
389        flag_code = '''
390            //Don't have genFlags handle the OF or CF bits
391            uint64_t mask = CFBit | OFBit;
392            ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
393            //If a logic microop wants to set these, it wants to set them to 0.
394            ccFlagBits &= ~(CFBit & ext);
395            ccFlagBits &= ~(OFBit & ext);
396        '''
397
398    class FlagRegOp(RegOp):
399        abstract = True
400        flag_code = \
401            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
402
403    class SubRegOp(RegOp):
404        abstract = True
405        flag_code = \
406            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
407
408    class CondRegOp(RegOp):
409        abstract = True
410        cond_check = "checkCondition(ccFlagBits)"
411
412    class Add(FlagRegOp):
413        code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
414
415    class Or(LogicRegOp):
416        code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
417
418    class Adc(FlagRegOp):
419        code = '''
420            CCFlagBits flags = ccFlagBits;
421            DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize);
422            '''
423
424    class Sbb(SubRegOp):
425        code = '''
426            CCFlagBits flags = ccFlagBits;
427            DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize);
428            '''
429
430    class And(LogicRegOp):
431        code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
432
433    class Sub(SubRegOp):
434        code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
435
436    class Xor(LogicRegOp):
437        code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
438
439    class Mul1s(FlagRegOp):
440        code = '''
441            int signPos = (dataSize * 8) / 2 - 1;
442            IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos);
443            IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos);
444            DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
445            '''
446
447    class Mul1u(FlagRegOp):
448        code = '''
449            int halfSize = (dataSize * 8) / 2;
450            IntReg srcVal1 = psrc1 & mask(halfSize);
451            IntReg srcVal2 = op2 & mask(halfSize);
452            DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
453            '''
454
455    class Mulel(FlagRegOp):
456        code = 'DestReg = merge(DestReg, psrc1 * op2, dataSize);'
457
458    class Muleh(FlagRegOp):
459        code = '''
460            int halfSize = (dataSize * 8) / 2;
461            uint64_t psrc1_h = psrc1 >> halfSize;
462            uint64_t psrc1_l = psrc1 & mask(halfSize);
463            uint64_t psrc2_h = op2 >> halfSize;
464            uint64_t psrc2_l = op2 & mask(halfSize);
465            uint64_t result =
466                ((psrc1_l * psrc2_h) >> halfSize) +
467                ((psrc1_h * psrc2_l) >> halfSize) +
468                psrc1_h * psrc2_h;
469            DestReg = merge(DestReg, result, dataSize);
470            '''
471
472    class Div1(FlagRegOp):
473        code = '''
474            int halfSize = (dataSize * 8) / 2;
475            IntReg quotient = (psrc1 / op2) & mask(halfSize);
476            IntReg remainder = (psrc1 % op2) & mask(halfSize);
477            IntReg result = quotient | (remainder << halfSize);
478            DestReg = merge(DestReg, result, dataSize);
479            '''
480
481    class Divq(FlagRegOp):
482        code = 'DestReg = merge(DestReg, psrc1 / op2, dataSize);'
483
484    class Divr(FlagRegOp):
485        code = 'DestReg = merge(DestReg, psrc1 % op2, dataSize);'
486
487    class Mov(CondRegOp):
488        code = 'DestReg = merge(SrcReg1, op2, dataSize)'
489        else_code = 'DestReg=DestReg;'
490
491    # Shift instructions
492
493    class Sll(FlagRegOp):
494        code = '''
495            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
496            DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
497            '''
498
499    class Srl(FlagRegOp):
500        code = '''
501            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
502            // Because what happens to the bits shift -in- on a right shift
503            // is not defined in the C/C++ standard, we have to mask them out
504            // to be sure they're zero.
505            uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
506            DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
507            '''
508
509    class Sra(FlagRegOp):
510        code = '''
511            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
512            // Because what happens to the bits shift -in- on a right shift
513            // is not defined in the C/C++ standard, we have to sign extend
514            // them manually to be sure.
515            uint64_t arithMask =
516                -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
517            DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
518            '''
519
520    class Ror(FlagRegOp):
521        code = '''
522            uint8_t shiftAmt =
523                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
524            if(shiftAmt)
525            {
526                uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
527                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
528                DestReg = merge(DestReg, top | bottom, dataSize);
529            }
530            else
531                DestReg = DestReg;
532            '''
533
534    class Rcr(FlagRegOp):
535        code = '''
536            uint8_t shiftAmt =
537                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
538            if(shiftAmt)
539            {
540                CCFlagBits flags = ccFlagBits;
541                uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
542                if(shiftAmt > 1)
543                    top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
544                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
545                DestReg = merge(DestReg, top | bottom, dataSize);
546            }
547            else
548                DestReg = DestReg;
549            '''
550
551    class Rol(FlagRegOp):
552        code = '''
553            uint8_t shiftAmt =
554                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
555            if(shiftAmt)
556            {
557                uint64_t top = psrc1 << shiftAmt;
558                uint64_t bottom =
559                    bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
560                DestReg = merge(DestReg, top | bottom, dataSize);
561            }
562            else
563                DestReg = DestReg;
564            '''
565
566    class Rcl(FlagRegOp):
567        code = '''
568            uint8_t shiftAmt =
569                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
570            if(shiftAmt)
571            {
572                CCFlagBits flags = ccFlagBits;
573                uint64_t top = psrc1 << shiftAmt;
574                uint64_t bottom = flags.CF << (shiftAmt - 1);
575                if(shiftAmt > 1)
576                    bottom |=
577                        bits(psrc1, dataSize * 8 - 1,
578                                   dataSize * 8 - shiftAmt + 1);
579                DestReg = merge(DestReg, top | bottom, dataSize);
580            }
581            else
582                DestReg = DestReg;
583            '''
584
585    class WrRegOp(RegOp):
586        abstract = True
587        def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
588            super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
589
590    class Wrip(WrRegOp, CondRegOp):
591        code = 'RIP = psrc1 + op2'
592        else_code="RIP = RIP;"
593
594    class Br(WrRegOp, CondRegOp):
595        code = 'nuIP = psrc1 + op2;'
596        else_code='nuIP = nuIP;'
597
598    class Wruflags(WrRegOp):
599        code = 'ccFlagBits = psrc1 ^ op2'
600
601    class RdRegOp(RegOp):
602        abstract = True
603        def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
604            super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
605
606    class Rdip(RdRegOp):
607        code = 'DestReg = RIP'
608
609    class Ruflags(RdRegOp):
610        code = 'DestReg = ccFlagBits'
611
612    class Ruflag(RegOp):
613        code = '''
614            int flag = bits(ccFlagBits, imm8 + 0*psrc1);
615            DestReg = merge(DestReg, flag, dataSize);
616            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
617                                       (ccFlagBits & ~EZFBit);
618            '''
619        def __init__(self, dest, imm, flags=None, \
620                dataSize="env.dataSize"):
621            super(Ruflag, self).__init__(dest, \
622                    "NUM_INTREGS", imm, flags, dataSize)
623
624    class Sext(RegOp):
625        code = '''
626            IntReg val = psrc1;
627            int sign_bit = bits(val, imm8-1, imm8-1);
628            uint64_t maskVal = mask(imm8);
629            val = sign_bit ? (val | ~maskVal) : (val & maskVal);
630            DestReg = merge(DestReg, val, dataSize);
631            '''
632
633    class Zext(RegOp):
634        code = 'DestReg = bits(psrc1, imm8-1, 0);'
635
636    class Compfp(WrRegOp):
637        # This class sets the condition codes in rflags according to the
638        # rules for comparing floating point.
639        code = '''
640            //               ZF PF CF
641            // Unordered      1  1  1
642            // Greater than   0  0  0
643            // Less than      0  0  1
644            // Equal          1  0  0
645            //           OF = SF = AF = 0
646            ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit |
647                                        ZFBit | PFBit | CFBit);
648            if (isnan(FpSrcReg1) || isnan(FpSrcReg2))
649                ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit);
650            else if(FpSrcReg1 < FpSrcReg2)
651                ccFlagBits = ccFlagBits | CFBit;
652            else if(FpSrcReg1 == FpSrcReg2)
653                ccFlagBits = ccFlagBits | ZFBit;
654        '''
655
656    class Xorfp(RegOp):
657        code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;'
658
659    class Movfp(CondRegOp):
660        code = 'FpDestReg.uqw = FpSrcReg2.uqw;'
661        else_code = 'FpDestReg.uqw = FpDestReg.uqw;'
662
663    # Conversion microops
664    class ConvOp(RegOp):
665        abstract = True
666        def __init__(self, dest, src1):
667            super(ConvOp, self).__init__(dest, src1, "NUM_INTREGS")
668
669    #FIXME This needs to always use 32 bits unless REX.W is present
670    class cvtf_i2d(ConvOp):
671        code = 'FpDestReg = psrc1;'
672
673    class cvtf_i2d_hi(ConvOp):
674        code = 'FpDestReg = bits(SrcReg1, 63, 32);'
675
676    class cvtf_d2i(ConvOp):
677        code = '''
678        int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1);
679        DestReg = merge(DestReg, intSrcReg1, dataSize);
680        '''
681
682    # These need to consider size at some point. They'll always use doubles
683    # for the moment.
684    class addfp(RegOp):
685        code = 'FpDestReg = FpSrcReg1 + FpSrcReg2;'
686
687    class mulfp(RegOp):
688        code = 'FpDestReg = FpSrcReg1 * FpSrcReg2;'
689
690    class divfp(RegOp):
691        code = 'FpDestReg = FpSrcReg1 / FpSrcReg2;'
692
693    class subfp(RegOp):
694        code = 'FpDestReg = FpSrcReg1 - FpSrcReg2;'
695}};
696