regop.isa revision 5028:b9d42ad1f94e
1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any 9// use which is NOT directed to receiving any direct monetary 10// compensation for, or commercial advantage from such use. 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Neither the name of 30// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 31// contributors may be used to endorse or promote products derived from 32// this software without specific prior written permission. No right of 33// sublicense is granted herewith. Derivatives of the software and 34// output created using the software may be prepared, but only for 35// Non-Commercial Uses. Derivatives of the software may be shared with 36// others provided: (i) the others agree to abide by the list of 37// conditions herein which includes the Non-Commercial Use restrictions; 38// and (ii) such Derivatives of the software include the above copyright 39// notice to acknowledge the contribution from this software where 40// applicable, this list of conditions and the disclaimer below. 41// 42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53// 54// Authors: Gabe Black 55 56////////////////////////////////////////////////////////////////////////// 57// 58// RegOp Microop templates 59// 60////////////////////////////////////////////////////////////////////////// 61 62def template MicroRegOpExecute {{ 63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 64 Trace::InstRecord *traceData) const 65 { 66 Fault fault = NoFault; 67 68 DPRINTF(X86, "The data size is %d\n", dataSize); 69 %(op_decl)s; 70 %(op_rd)s; 71 72 if(%(cond_check)s) 73 { 74 %(code)s; 75 %(flag_code)s; 76 } 77 else 78 { 79 %(else_code)s; 80 } 81 82 //Write the resulting state to the execution context 83 if(fault == NoFault) 84 { 85 %(op_wb)s; 86 } 87 return fault; 88 } 89}}; 90 91def template MicroRegOpImmExecute {{ 92 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 93 Trace::InstRecord *traceData) const 94 { 95 Fault fault = NoFault; 96 97 %(op_decl)s; 98 %(op_rd)s; 99 100 if(%(cond_check)s) 101 { 102 %(code)s; 103 %(flag_code)s; 104 } 105 else 106 { 107 %(else_code)s; 108 } 109 110 //Write the resulting state to the execution context 111 if(fault == NoFault) 112 { 113 %(op_wb)s; 114 } 115 return fault; 116 } 117}}; 118 119def template MicroRegOpDeclare {{ 120 class %(class_name)s : public %(base_class)s 121 { 122 protected: 123 void buildMe(); 124 125 public: 126 %(class_name)s(ExtMachInst _machInst, 127 const char * instMnem, 128 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 129 RegIndex _src1, RegIndex _src2, RegIndex _dest, 130 uint8_t _dataSize, uint16_t _ext); 131 132 %(class_name)s(ExtMachInst _machInst, 133 const char * instMnem, 134 RegIndex _src1, RegIndex _src2, RegIndex _dest, 135 uint8_t _dataSize, uint16_t _ext); 136 137 %(BasicExecDeclare)s 138 }; 139}}; 140 141def template MicroRegOpImmDeclare {{ 142 143 class %(class_name)s : public %(base_class)s 144 { 145 protected: 146 void buildMe(); 147 148 public: 149 %(class_name)s(ExtMachInst _machInst, 150 const char * instMnem, 151 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 152 RegIndex _src1, uint16_t _imm8, RegIndex _dest, 153 uint8_t _dataSize, uint16_t _ext); 154 155 %(class_name)s(ExtMachInst _machInst, 156 const char * instMnem, 157 RegIndex _src1, uint16_t _imm8, RegIndex _dest, 158 uint8_t _dataSize, uint16_t _ext); 159 160 %(BasicExecDeclare)s 161 }; 162}}; 163 164def template MicroRegOpConstructor {{ 165 166 inline void %(class_name)s::buildMe() 167 { 168 %(constructor)s; 169 } 170 171 inline %(class_name)s::%(class_name)s( 172 ExtMachInst machInst, const char * instMnem, 173 RegIndex _src1, RegIndex _src2, RegIndex _dest, 174 uint8_t _dataSize, uint16_t _ext) : 175 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 176 false, false, false, false, 177 _src1, _src2, _dest, _dataSize, _ext, 178 %(op_class)s) 179 { 180 buildMe(); 181 } 182 183 inline %(class_name)s::%(class_name)s( 184 ExtMachInst machInst, const char * instMnem, 185 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 186 RegIndex _src1, RegIndex _src2, RegIndex _dest, 187 uint8_t _dataSize, uint16_t _ext) : 188 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 189 isMicro, isDelayed, isFirst, isLast, 190 _src1, _src2, _dest, _dataSize, _ext, 191 %(op_class)s) 192 { 193 buildMe(); 194 } 195}}; 196 197def template MicroRegOpImmConstructor {{ 198 199 inline void %(class_name)s::buildMe() 200 { 201 %(constructor)s; 202 } 203 204 inline %(class_name)s::%(class_name)s( 205 ExtMachInst machInst, const char * instMnem, 206 RegIndex _src1, uint16_t _imm8, RegIndex _dest, 207 uint8_t _dataSize, uint16_t _ext) : 208 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 209 false, false, false, false, 210 _src1, _imm8, _dest, _dataSize, _ext, 211 %(op_class)s) 212 { 213 buildMe(); 214 } 215 216 inline %(class_name)s::%(class_name)s( 217 ExtMachInst machInst, const char * instMnem, 218 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 219 RegIndex _src1, uint16_t _imm8, RegIndex _dest, 220 uint8_t _dataSize, uint16_t _ext) : 221 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 222 isMicro, isDelayed, isFirst, isLast, 223 _src1, _imm8, _dest, _dataSize, _ext, 224 %(op_class)s) 225 { 226 buildMe(); 227 } 228}}; 229 230let {{ 231 class X86MicroMeta(type): 232 def __new__(mcls, name, bases, dict): 233 abstract = False 234 if "abstract" in dict: 235 abstract = dict['abstract'] 236 del dict['abstract'] 237 238 cls = type.__new__(mcls, name, bases, dict) 239 if not abstract: 240 allClasses[name] = cls 241 return cls 242 243 class XXX86Microop(object): 244 __metaclass__ = X86MicroMeta 245 abstract = True 246 247 class RegOp(X86Microop): 248 abstract = True 249 def __init__(self, dest, src1, src2, flags, dataSize): 250 self.dest = dest 251 self.src1 = src1 252 self.src2 = src2 253 self.flags = flags 254 self.dataSize = dataSize 255 if flags is None: 256 self.ext = 0 257 else: 258 if not isinstance(flags, (list, tuple)): 259 raise Exception, "flags must be a list or tuple of flags" 260 self.ext = " | ".join(flags) 261 self.className += "Flags" 262 263 def getAllocator(self, *microFlags): 264 allocator = '''new %(class_name)s(machInst, mnemonic 265 %(flags)s, %(src1)s, %(src2)s, %(dest)s, 266 %(dataSize)s, %(ext)s)''' % { 267 "class_name" : self.className, 268 "flags" : self.microFlagsText(microFlags), 269 "src1" : self.src1, "src2" : self.src2, 270 "dest" : self.dest, 271 "dataSize" : self.dataSize, 272 "ext" : self.ext} 273 return allocator 274 275 class RegOpImm(X86Microop): 276 abstract = True 277 def __init__(self, dest, src1, imm8, flags, dataSize): 278 self.dest = dest 279 self.src1 = src1 280 self.imm8 = imm8 281 self.flags = flags 282 self.dataSize = dataSize 283 if flags is None: 284 self.ext = 0 285 else: 286 if not isinstance(flags, (list, tuple)): 287 raise Exception, "flags must be a list or tuple of flags" 288 self.ext = " | ".join(flags) 289 self.className += "Flags" 290 291 def getAllocator(self, *microFlags): 292 allocator = '''new %(class_name)s(machInst, mnemonic 293 %(flags)s, %(src1)s, %(imm8)s, %(dest)s, 294 %(dataSize)s, %(ext)s)''' % { 295 "class_name" : self.className, 296 "flags" : self.microFlagsText(microFlags), 297 "src1" : self.src1, "imm8" : self.imm8, 298 "dest" : self.dest, 299 "dataSize" : self.dataSize, 300 "ext" : self.ext} 301 return allocator 302}}; 303 304let {{ 305 306 # Make these empty strings so that concatenating onto 307 # them will always work. 308 header_output = "" 309 decoder_output = "" 310 exec_output = "" 311 312 # A function which builds the C++ classes that implement the microops 313 def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";", imm=False): 314 global header_output 315 global decoder_output 316 global exec_output 317 global microopClasses 318 319 iop = InstObjParams(name, Name, base, 320 {"code" : code, 321 "flag_code" : flagCode, 322 "cond_check" : condCheck, 323 "else_code" : elseCode}) 324 if imm: 325 header_output += MicroRegOpImmDeclare.subst(iop) 326 decoder_output += MicroRegOpImmConstructor.subst(iop) 327 exec_output += MicroRegOpImmExecute.subst(iop) 328 else: 329 header_output += MicroRegOpDeclare.subst(iop) 330 decoder_output += MicroRegOpConstructor.subst(iop) 331 exec_output += MicroRegOpExecute.subst(iop) 332 333 334 checkCCFlagBits = "checkCondition(ccFlagBits)" 335 genCCFlagBits = \ 336 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 337 genCCFlagBitsSub = \ 338 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 339 genCCFlagBitsLogic = ''' 340 //Don't have genFlags handle the OF or CF bits 341 uint64_t mask = CFBit | OFBit; 342 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 343 //If a logic microop wants to set these, it wants to set them to 0. 344 ccFlagBits &= ~(CFBit & ext); 345 ccFlagBits &= ~(OFBit & ext); 346 ''' 347 348 regPick = ''' 349 IntReg psrc1 = pick(SrcReg1, 0, dataSize); 350 IntReg psrc2 = pick(SrcReg2, 1, dataSize); 351 ''' 352 immPick = ''' 353 IntReg psrc1 = pick(SrcReg1, 0, dataSize); 354 ''' 355 356 357 # This creates a python representations of a microop which are a cross 358 # product of reg/immediate and flag/no flag versions. 359 def defineMicroRegOp(mnemonic, code, flagCode=genCCFlagBits, \ 360 cc=False, doImm=True, elseCode=";"): 361 Name = mnemonic 362 name = mnemonic.lower() 363 364 # Find op2 in each of the instruction definitions. Create two versions 365 # of the code, one with an integer operand, and one with an immediate 366 # operand. 367 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 368 regCode = regPick + matcher.sub("psrc2", code) 369 immCode = immPick + matcher.sub("imm8", code) 370 371 if not cc: 372 condCode = "true" 373 else: 374 flagCode = "" 375 condCode = checkCCFlagBits 376 377 regFlagCode = matcher.sub("psrc2", flagCode) 378 immFlagCode = matcher.sub("imm8", flagCode) 379 380 class RegOpChild(RegOp): 381 mnemonic = name 382 className = Name 383 def __init__(self, dest, src1, src2, \ 384 flags=None, dataSize="env.dataSize"): 385 super(RegOpChild, self).__init__(dest, src1, src2, \ 386 flags, dataSize) 387 388 microopClasses[name] = RegOpChild 389 390 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode); 391 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", 392 regCode, flagCode=regFlagCode, 393 condCheck=condCode, elseCode=elseCode); 394 395 if doImm: 396 class RegOpChildImm(RegOpImm): 397 mnemonic = name + 'i' 398 className = Name + 'Imm' 399 def __init__(self, dest, src1, src2, \ 400 flags=None, dataSize="env.dataSize"): 401 super(RegOpChildImm, self).__init__(dest, src1, src2, \ 402 flags, dataSize) 403 404 microopClasses[name + 'i'] = RegOpChildImm 405 406 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \ 407 immCode, imm=True); 408 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", 409 immCode, flagCode=immFlagCode, 410 condCheck=condCode, elseCode=elseCode, imm=True); 411 412 # This has it's own function because Wr ops have implicit destinations 413 def defineMicroRegOpWr(mnemonic, code, elseCode=";"): 414 Name = mnemonic 415 name = mnemonic.lower() 416 417 # Find op2 in each of the instruction definitions. Create two versions 418 # of the code, one with an integer operand, and one with an immediate 419 # operand. 420 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 421 regCode = regPick + matcher.sub("psrc2", code) 422 immCode = immPick + matcher.sub("imm8", code) 423 424 class RegOpChild(RegOp): 425 mnemonic = name 426 className = Name 427 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 428 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 429 430 microopClasses[name] = RegOpChild 431 432 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode); 433 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, 434 condCheck = checkCCFlagBits, elseCode = elseCode); 435 436 class RegOpChildImm(RegOpImm): 437 mnemonic = name + 'i' 438 className = Name + 'Imm' 439 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 440 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 441 442 microopClasses[name + 'i'] = RegOpChildImm 443 444 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", \ 445 immCode, imm=True); 446 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", \ 447 immCode, condCheck = checkCCFlagBits, elseCode = elseCode, \ 448 imm=True); 449 450 # This has it's own function because Rd ops don't always have two parameters 451 def defineMicroRegOpRd(mnemonic, code): 452 Name = mnemonic 453 name = mnemonic.lower() 454 455 class RegOpChild(RegOp): 456 className = Name 457 mnemonic = name 458 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"): 459 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 460 461 microopClasses[name] = RegOpChild 462 463 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code); 464 465 def defineMicroRegOpImm(mnemonic, code, flagCode=""): 466 Name = mnemonic 467 name = mnemonic.lower() 468 code = immPick + code 469 470 class RegOpChild(RegOpImm): 471 className = Name 472 mnemonic = name 473 def __init__(self, dest, src1, src2, \ 474 flags=None, dataSize="env.dataSize"): 475 super(RegOpChild, self).__init__(dest, \ 476 src1, src2, flags, dataSize) 477 478 microopClasses[name] = RegOpChild 479 480 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True); 481 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \ 482 code, flagCode=flagCode, imm=True); 483 484 def defineMicroRegOpRdImm(mnemonic, code, flagCode=""): 485 Name = mnemonic 486 name = mnemonic.lower() 487 code = immPick + code 488 489 class RegOpChildRdImm(RegOpImm): 490 className = Name 491 mnemonic = name 492 def __init__(self, dest, imm, flags=None, \ 493 dataSize="env.dataSize"): 494 super(RegOpChildRdImm, self).__init__(dest, \ 495 "NUM_INTREGS", imm, flags, dataSize) 496 497 microopClasses[name] = RegOpChildRdImm 498 499 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True); 500 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \ 501 code, flagCode=flagCode, imm=True); 502 503 defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)') 504 defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);', 505 flagCode = genCCFlagBitsLogic) 506 defineMicroRegOp('Adc', ''' 507 CCFlagBits flags = ccFlagBits; 508 DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize); 509 ''') 510 defineMicroRegOp('Sbb', ''' 511 CCFlagBits flags = ccFlagBits; 512 DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize); 513 ''', flagCode = genCCFlagBitsSub) 514 defineMicroRegOp('And', \ 515 'DestReg = merge(DestReg, psrc1 & op2, dataSize)', \ 516 flagCode = genCCFlagBitsLogic) 517 defineMicroRegOp('Sub', \ 518 'DestReg = merge(DestReg, psrc1 - op2, dataSize)', \ 519 flagCode = genCCFlagBitsSub) 520 defineMicroRegOp('Xor', \ 521 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)', \ 522 flagCode = genCCFlagBitsLogic) 523 defineMicroRegOp('Mul1s', ''' 524 int signPos = (dataSize * 8) / 2 - 1; 525 IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos); 526 IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos); 527 DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize) 528 ''') 529 defineMicroRegOp('Mul1u', ''' 530 int halfSize = (dataSize * 8) / 2; 531 IntReg srcVal1 = psrc1 & mask(halfSize); 532 IntReg srcVal2 = op2 & mask(halfSize); 533 DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize) 534 ''') 535 defineMicroRegOp('Mulel', \ 536 'DestReg = merge(DestReg, psrc1 * op2, dataSize)') 537 defineMicroRegOp('Muleh', ''' 538 int halfSize = (dataSize * 8) / 2; 539 uint64_t psrc1_h = psrc1 >> halfSize; 540 uint64_t psrc1_l = psrc1 & mask(halfSize); 541 uint64_t psrc2_h = op2 >> halfSize; 542 uint64_t psrc2_l = op2 & mask(halfSize); 543 uint64_t result = 544 ((psrc1_l * psrc2_h) >> halfSize) + 545 ((psrc1_h * psrc2_l) >> halfSize) + 546 psrc1_h * psrc2_h; 547 DestReg = merge(DestReg, result, dataSize); 548 ''') 549 defineMicroRegOp('Div1', ''' 550 int halfSize = (dataSize * 8) / 2; 551 IntReg quotient = (psrc1 / op2) & mask(halfSize); 552 IntReg remainder = (psrc1 % op2) & mask(halfSize); 553 IntReg result = quotient | (remainder << halfSize); 554 DestReg = merge(DestReg, result, dataSize); 555 ''') 556 defineMicroRegOp('Divq', ''' 557 DestReg = merge(DestReg, psrc1 / op2, dataSize); 558 ''') 559 defineMicroRegOp('Divr', ''' 560 DestReg = merge(DestReg, psrc1 % op2, dataSize); 561 ''') 562 563 # 564 # HACK HACK HACK HACK - Put psrc1 in here but make it inert to shut up gcc. 565 # 566 defineMicroRegOp('Mov', 567 'DestReg = merge(SrcReg1, psrc1 * 0 + op2, dataSize)', 568 elseCode='DestReg=DestReg;', cc=True) 569 570 defineMicroRegOp('Movfp', 571 'FpDestReg = FpSrcReg2 + psrc1 * 0 + psrc2 * 0', 572 elseCode='FpDestReg=FpDestReg;', cc=True, doImm=False) 573 574 # Shift instructions 575 defineMicroRegOp('Sll', ''' 576 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 577 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 578 ''') 579 defineMicroRegOp('Srl', ''' 580 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 581 // Because what happens to the bits shift -in- on a right shift 582 // is not defined in the C/C++ standard, we have to mask them out 583 // to be sure they're zero. 584 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 585 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 586 ''') 587 defineMicroRegOp('Sra', ''' 588 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 589 // Because what happens to the bits shift -in- on a right shift 590 // is not defined in the C/C++ standard, we have to sign extend 591 // them manually to be sure. 592 uint64_t arithMask = 593 -bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 594 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 595 ''') 596 defineMicroRegOp('Ror', ''' 597 uint8_t shiftAmt = 598 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 599 if(shiftAmt) 600 { 601 uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 602 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 603 DestReg = merge(DestReg, top | bottom, dataSize); 604 } 605 else 606 DestReg = DestReg; 607 ''') 608 defineMicroRegOp('Rcr', ''' 609 uint8_t shiftAmt = 610 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 611 if(shiftAmt) 612 { 613 CCFlagBits flags = ccFlagBits; 614 uint64_t top = flags.CF << (dataSize * 8 - shiftAmt); 615 if(shiftAmt > 1) 616 top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 617 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 618 DestReg = merge(DestReg, top | bottom, dataSize); 619 } 620 else 621 DestReg = DestReg; 622 ''') 623 defineMicroRegOp('Rol', ''' 624 uint8_t shiftAmt = 625 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 626 if(shiftAmt) 627 { 628 uint64_t top = psrc1 << shiftAmt; 629 uint64_t bottom = 630 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 631 DestReg = merge(DestReg, top | bottom, dataSize); 632 } 633 else 634 DestReg = DestReg; 635 ''') 636 defineMicroRegOp('Rcl', ''' 637 uint8_t shiftAmt = 638 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 639 if(shiftAmt) 640 { 641 CCFlagBits flags = ccFlagBits; 642 uint64_t top = psrc1 << shiftAmt; 643 uint64_t bottom = flags.CF << (shiftAmt - 1); 644 if(shiftAmt > 1) 645 bottom |= 646 bits(psrc1, dataSize * 8 - 1, 647 dataSize * 8 - shiftAmt + 1); 648 DestReg = merge(DestReg, top | bottom, dataSize); 649 } 650 else 651 DestReg = DestReg; 652 ''') 653 654 defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;") 655 defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;') 656 defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2') 657 658 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 659 defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits') 660 defineMicroRegOpRdImm('Ruflag', ''' 661 int flag = bits(ccFlagBits, imm8 + 0*psrc1); 662 DestReg = merge(DestReg, flag, dataSize); 663 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 664 (ccFlagBits & ~EZFBit); 665 ''') 666 667 defineMicroRegOpImm('Sext', ''' 668 IntReg val = psrc1; 669 int sign_bit = bits(val, imm8-1, imm8-1); 670 uint64_t maskVal = mask(imm8); 671 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 672 DestReg = merge(DestReg, val, dataSize); 673 ''') 674 675 defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);') 676}}; 677