regop.isa revision 9212
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 124519Sgblack@eecs.umich.edu// 137087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 147087Snate@binkert.org// modification, are permitted provided that the following conditions are 157087Snate@binkert.org// met: redistributions of source code must retain the above copyright 167087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org// documentation and/or other materials provided with the distribution; 207087Snate@binkert.org// neither the name of the copyright holders nor the names of its 214519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227087Snate@binkert.org// this software without specific prior written permission. 234519Sgblack@eecs.umich.edu// 244519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354519Sgblack@eecs.umich.edu// 364519Sgblack@eecs.umich.edu// Authors: Gabe Black 374519Sgblack@eecs.umich.edu 384519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 394519Sgblack@eecs.umich.edu// 404519Sgblack@eecs.umich.edu// RegOp Microop templates 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 434519Sgblack@eecs.umich.edu 444519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 454519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 464519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474519Sgblack@eecs.umich.edu { 484519Sgblack@eecs.umich.edu Fault fault = NoFault; 494519Sgblack@eecs.umich.edu 504809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 514519Sgblack@eecs.umich.edu %(op_decl)s; 524519Sgblack@eecs.umich.edu %(op_rd)s; 534688Sgblack@eecs.umich.edu 547969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 557969Sgblack@eecs.umich.edu 564688Sgblack@eecs.umich.edu if(%(cond_check)s) 574688Sgblack@eecs.umich.edu { 584688Sgblack@eecs.umich.edu %(code)s; 594688Sgblack@eecs.umich.edu %(flag_code)s; 604688Sgblack@eecs.umich.edu } 614708Sgblack@eecs.umich.edu else 624708Sgblack@eecs.umich.edu { 634708Sgblack@eecs.umich.edu %(else_code)s; 644708Sgblack@eecs.umich.edu } 654519Sgblack@eecs.umich.edu 664519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 674519Sgblack@eecs.umich.edu if(fault == NoFault) 684519Sgblack@eecs.umich.edu { 694519Sgblack@eecs.umich.edu %(op_wb)s; 704519Sgblack@eecs.umich.edu } 714519Sgblack@eecs.umich.edu return fault; 724519Sgblack@eecs.umich.edu } 734519Sgblack@eecs.umich.edu}}; 744519Sgblack@eecs.umich.edu 754519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 764951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 774519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 784519Sgblack@eecs.umich.edu { 794519Sgblack@eecs.umich.edu Fault fault = NoFault; 804519Sgblack@eecs.umich.edu 814519Sgblack@eecs.umich.edu %(op_decl)s; 824519Sgblack@eecs.umich.edu %(op_rd)s; 834688Sgblack@eecs.umich.edu 847969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 857969Sgblack@eecs.umich.edu 864688Sgblack@eecs.umich.edu if(%(cond_check)s) 874688Sgblack@eecs.umich.edu { 884688Sgblack@eecs.umich.edu %(code)s; 894688Sgblack@eecs.umich.edu %(flag_code)s; 904688Sgblack@eecs.umich.edu } 914708Sgblack@eecs.umich.edu else 924708Sgblack@eecs.umich.edu { 934708Sgblack@eecs.umich.edu %(else_code)s; 944708Sgblack@eecs.umich.edu } 954519Sgblack@eecs.umich.edu 964519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 974519Sgblack@eecs.umich.edu if(fault == NoFault) 984519Sgblack@eecs.umich.edu { 994519Sgblack@eecs.umich.edu %(op_wb)s; 1004519Sgblack@eecs.umich.edu } 1014519Sgblack@eecs.umich.edu return fault; 1024519Sgblack@eecs.umich.edu } 1034519Sgblack@eecs.umich.edu}}; 1044519Sgblack@eecs.umich.edu 1054519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1064519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1074519Sgblack@eecs.umich.edu { 1084519Sgblack@eecs.umich.edu public: 1094519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1107620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1116345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1124712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1134519Sgblack@eecs.umich.edu 1144519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1154519Sgblack@eecs.umich.edu }; 1164519Sgblack@eecs.umich.edu}}; 1174519Sgblack@eecs.umich.edu 1184519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1194519Sgblack@eecs.umich.edu 1204951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu public: 1234951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1247620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1256646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1264712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1274519Sgblack@eecs.umich.edu 1284519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1294519Sgblack@eecs.umich.edu }; 1304519Sgblack@eecs.umich.edu}}; 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1334519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1347620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1356345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1364712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1377620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1384688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1394581Sgblack@eecs.umich.edu %(op_class)s) 1404519Sgblack@eecs.umich.edu { 1417626Sgblack@eecs.umich.edu %(constructor)s; 1427894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1434519Sgblack@eecs.umich.edu } 1444519Sgblack@eecs.umich.edu}}; 1454519Sgblack@eecs.umich.edu 1464519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1474951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1487620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1496646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1504712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1517620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1524688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 1534581Sgblack@eecs.umich.edu %(op_class)s) 1544519Sgblack@eecs.umich.edu { 1557626Sgblack@eecs.umich.edu %(constructor)s; 1567894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1574519Sgblack@eecs.umich.edu } 1584519Sgblack@eecs.umich.edu}}; 1594519Sgblack@eecs.umich.edu 1605075Sgblack@eecs.umich.eduoutput header {{ 1615075Sgblack@eecs.umich.edu void 1625075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1635075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 1645428Sgblack@eecs.umich.edu 1655428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 1665674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 1675899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 1685936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 1695428Sgblack@eecs.umich.edu }; 1705678Sgblack@eecs.umich.edu 1715678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 1725678Sgblack@eecs.umich.edu LDT64 = 2, 1735678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 1745678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 1755678Sgblack@eecs.umich.edu CallGate64 = 0xc, 1765678Sgblack@eecs.umich.edu IntGate64 = 0xe, 1775678Sgblack@eecs.umich.edu TrapGate64 = 0xf 1785678Sgblack@eecs.umich.edu }; 1795075Sgblack@eecs.umich.edu}}; 1805075Sgblack@eecs.umich.edu 1815075Sgblack@eecs.umich.eduoutput decoder {{ 1825075Sgblack@eecs.umich.edu void 1835075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1845075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 1855075Sgblack@eecs.umich.edu { 1865075Sgblack@eecs.umich.edu //Check for divide by zero. 1877719Sgblack@eecs.umich.edu assert(divisor != 0); 1885075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 1895075Sgblack@eecs.umich.edu if (divisor <= dividend) { 1905075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 1915075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 1925075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 1935075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 1945075Sgblack@eecs.umich.edu divisor <<= shift; 1955075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 1965075Sgblack@eecs.umich.edu //now larger than the dividend. 1975075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 1985075Sgblack@eecs.umich.edu quotientBit <<= shift; 1995075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2005075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2015075Sgblack@eecs.umich.edu //part of one or two bit division. 2025075Sgblack@eecs.umich.edu if (divisor > dividend) { 2035075Sgblack@eecs.umich.edu quotientBit >>= 1; 2045075Sgblack@eecs.umich.edu divisor >>= 1; 2055075Sgblack@eecs.umich.edu } 2065075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2075075Sgblack@eecs.umich.edu quotient += quotientBit; 2085075Sgblack@eecs.umich.edu remainder -= divisor; 2095075Sgblack@eecs.umich.edu } 2105075Sgblack@eecs.umich.edu } 2115075Sgblack@eecs.umich.edu}}; 2125075Sgblack@eecs.umich.edu 2134519Sgblack@eecs.umich.edulet {{ 2145040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2155040Sgblack@eecs.umich.edu # them will always work. 2165040Sgblack@eecs.umich.edu header_output = "" 2175040Sgblack@eecs.umich.edu decoder_output = "" 2185040Sgblack@eecs.umich.edu exec_output = "" 2195040Sgblack@eecs.umich.edu 2205040Sgblack@eecs.umich.edu immTemplates = ( 2215040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2225040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2235040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2245040Sgblack@eecs.umich.edu 2255040Sgblack@eecs.umich.edu regTemplates = ( 2265040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2275040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2285040Sgblack@eecs.umich.edu MicroRegOpExecute) 2295040Sgblack@eecs.umich.edu 2305040Sgblack@eecs.umich.edu class RegOpMeta(type): 2317967Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, code, big_code, \ 2327967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, cond_control_flag_init): 2335040Sgblack@eecs.umich.edu 2345040Sgblack@eecs.umich.edu # Globals to stick the output in 2355040Sgblack@eecs.umich.edu global header_output 2365040Sgblack@eecs.umich.edu global decoder_output 2375040Sgblack@eecs.umich.edu global exec_output 2385040Sgblack@eecs.umich.edu 2395040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2407894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 2417894SBrad.Beckmann@amd.com cond_control_flag_init)) 2427967Sgblack@eecs.umich.edu allBigCode = "|".join((big_code, flag_code, cond_check, else_code, 2437967Sgblack@eecs.umich.edu cond_control_flag_init)) 2445040Sgblack@eecs.umich.edu 2455040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2465040Sgblack@eecs.umich.edu # of this code. 2478588Sgblack@eecs.umich.edu matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?") 2487967Sgblack@eecs.umich.edu match = matcher.search(allCode + allBigCode) 2495062Sgblack@eecs.umich.edu if match: 2505062Sgblack@eecs.umich.edu typeQual = "" 2515062Sgblack@eecs.umich.edu if match.group("typeQual"): 2525062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 2535062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 2545040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2555062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 2567967Sgblack@eecs.umich.edu matcher.sub(src2_name, big_code), 2575062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 2585062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 2597894SBrad.Beckmann@amd.com matcher.sub(src2_name, else_code), 2607894SBrad.Beckmann@amd.com matcher.sub(src2_name, cond_control_flag_init)) 2616647Sgblack@eecs.umich.edu imm_name = "%simm8" % match.group("prefix") 2625040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 2636647Sgblack@eecs.umich.edu matcher.sub(imm_name, code), 2647967Sgblack@eecs.umich.edu matcher.sub(imm_name, big_code), 2656647Sgblack@eecs.umich.edu matcher.sub(imm_name, flag_code), 2666647Sgblack@eecs.umich.edu matcher.sub(imm_name, cond_check), 2677894SBrad.Beckmann@amd.com matcher.sub(imm_name, else_code), 2687894SBrad.Beckmann@amd.com matcher.sub(imm_name, cond_control_flag_init)) 2695040Sgblack@eecs.umich.edu return 2705040Sgblack@eecs.umich.edu 2715040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 2725040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 2735239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 2745040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2757967Sgblack@eecs.umich.edu code, big_code, "", "true", else_code, "") 2765040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 2775040Sgblack@eecs.umich.edu 2785040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 2795040Sgblack@eecs.umich.edu # compute it. 2807967Sgblack@eecs.umich.edu for (big, all) in ((False, allCode), (True, allBigCode)): 2817967Sgblack@eecs.umich.edu prefix = "" 2827967Sgblack@eecs.umich.edu for (rex, decl) in ( 2837967Sgblack@eecs.umich.edu ("(?<!\w)psrc1(?!\w)", 2847967Sgblack@eecs.umich.edu "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"), 2857967Sgblack@eecs.umich.edu ("(?<!\w)psrc2(?!\w)", 2867967Sgblack@eecs.umich.edu "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"), 2877967Sgblack@eecs.umich.edu ("(?<!\w)spsrc1(?!\w)", 2887967Sgblack@eecs.umich.edu "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"), 2897967Sgblack@eecs.umich.edu ("(?<!\w)spsrc2(?!\w)", 2907967Sgblack@eecs.umich.edu "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"), 2917967Sgblack@eecs.umich.edu ("(?<!\w)simm8(?!\w)", 2927967Sgblack@eecs.umich.edu "int8_t simm8 = imm8;")): 2937967Sgblack@eecs.umich.edu matcher = re.compile(rex) 2947967Sgblack@eecs.umich.edu if matcher.search(all): 2957967Sgblack@eecs.umich.edu prefix += decl + "\n" 2967967Sgblack@eecs.umich.edu if big: 2977967Sgblack@eecs.umich.edu if big_code != "": 2987967Sgblack@eecs.umich.edu big_code = prefix + big_code 2997967Sgblack@eecs.umich.edu else: 3007967Sgblack@eecs.umich.edu code = prefix + code 3015040Sgblack@eecs.umich.edu 3025040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3035040Sgblack@eecs.umich.edu 3045040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3055040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3065040Sgblack@eecs.umich.edu templates = regTemplates 3076647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3085040Sgblack@eecs.umich.edu if matcher.search(allCode): 3095040Sgblack@eecs.umich.edu base += "Imm" 3105040Sgblack@eecs.umich.edu templates = immTemplates 3115040Sgblack@eecs.umich.edu 3125040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3137967Sgblack@eecs.umich.edu iops = [InstObjParams(name, Name + suffix, base, 3145040Sgblack@eecs.umich.edu {"code" : code, 3155040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3165040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3177894SBrad.Beckmann@amd.com "else_code" : else_code, 3187967Sgblack@eecs.umich.edu "cond_control_flag_init" : cond_control_flag_init})] 3197967Sgblack@eecs.umich.edu if big_code != "": 3207967Sgblack@eecs.umich.edu iops += [InstObjParams(name, Name + suffix + "Big", base, 3217967Sgblack@eecs.umich.edu {"code" : big_code, 3227967Sgblack@eecs.umich.edu "flag_code" : flag_code, 3237967Sgblack@eecs.umich.edu "cond_check" : cond_check, 3247967Sgblack@eecs.umich.edu "else_code" : else_code, 3257967Sgblack@eecs.umich.edu "cond_control_flag_init" : 3267967Sgblack@eecs.umich.edu cond_control_flag_init})] 3275040Sgblack@eecs.umich.edu 3285040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3297967Sgblack@eecs.umich.edu for iop in iops: 3307967Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3317967Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3327967Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3335040Sgblack@eecs.umich.edu 3345040Sgblack@eecs.umich.edu 3355040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3364688Sgblack@eecs.umich.edu abstract = False 3375040Sgblack@eecs.umich.edu name = Name.lower() 3384688Sgblack@eecs.umich.edu if "abstract" in dict: 3394688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3404688Sgblack@eecs.umich.edu del dict['abstract'] 3414688Sgblack@eecs.umich.edu 3425040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3434688Sgblack@eecs.umich.edu if not abstract: 3445040Sgblack@eecs.umich.edu cls.className = Name 3455040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3465040Sgblack@eecs.umich.edu code = cls.code 3477967Sgblack@eecs.umich.edu big_code = cls.big_code 3485040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3495040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3505040Sgblack@eecs.umich.edu else_code = cls.else_code 3517894SBrad.Beckmann@amd.com cond_control_flag_init = cls.cond_control_flag_init 3525040Sgblack@eecs.umich.edu 3535040Sgblack@eecs.umich.edu # Set up the C++ classes 3547967Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", code, big_code, 3557967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, 3567967Sgblack@eecs.umich.edu cond_control_flag_init) 3575040Sgblack@eecs.umich.edu 3585040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3595040Sgblack@eecs.umich.edu global microopClasses 3605040Sgblack@eecs.umich.edu microopClasses[name] = cls 3615040Sgblack@eecs.umich.edu 3627894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 3637894SBrad.Beckmann@amd.com cond_control_flag_init)) 3645040Sgblack@eecs.umich.edu 3655040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3665040Sgblack@eecs.umich.edu # of this code. 3678588Sgblack@eecs.umich.edu matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?") 3685040Sgblack@eecs.umich.edu if matcher.search(allCode): 3695040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3704688Sgblack@eecs.umich.edu return cls 3714688Sgblack@eecs.umich.edu 3725040Sgblack@eecs.umich.edu 3735040Sgblack@eecs.umich.edu class RegOp(X86Microop): 3745040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 3755040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 3764688Sgblack@eecs.umich.edu abstract = True 3774688Sgblack@eecs.umich.edu 3785040Sgblack@eecs.umich.edu # Default template parameter values 3797967Sgblack@eecs.umich.edu big_code = "" 3805040Sgblack@eecs.umich.edu flag_code = "" 3815040Sgblack@eecs.umich.edu cond_check = "true" 3825040Sgblack@eecs.umich.edu else_code = ";" 3837894SBrad.Beckmann@amd.com cond_control_flag_init = "" 3845040Sgblack@eecs.umich.edu 3855040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 3864519Sgblack@eecs.umich.edu self.dest = dest 3874519Sgblack@eecs.umich.edu self.src1 = src1 3885040Sgblack@eecs.umich.edu self.op2 = op2 3894688Sgblack@eecs.umich.edu self.flags = flags 3904701Sgblack@eecs.umich.edu self.dataSize = dataSize 3914688Sgblack@eecs.umich.edu if flags is None: 3924688Sgblack@eecs.umich.edu self.ext = 0 3934688Sgblack@eecs.umich.edu else: 3944688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 3954688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 3964688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 3974688Sgblack@eecs.umich.edu self.className += "Flags" 3984519Sgblack@eecs.umich.edu 3997620Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 4007967Sgblack@eecs.umich.edu if self.big_code != "": 4017967Sgblack@eecs.umich.edu className = self.className 4027967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4037967Sgblack@eecs.umich.edu className += "Imm" 4047967Sgblack@eecs.umich.edu allocString = ''' 4057967Sgblack@eecs.umich.edu (%(dataSize)s >= 4) ? 4067967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)sBig(machInst, 4077967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4087967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) : 4097967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)s(machInst, 4107967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4117967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) 4127967Sgblack@eecs.umich.edu ''' 4137967Sgblack@eecs.umich.edu allocator = allocString % { 4147967Sgblack@eecs.umich.edu "class_name" : className, 4157967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4167967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4177967Sgblack@eecs.umich.edu "dest" : self.dest, 4187967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4197967Sgblack@eecs.umich.edu "ext" : self.ext} 4207967Sgblack@eecs.umich.edu return allocator 4217967Sgblack@eecs.umich.edu else: 4227967Sgblack@eecs.umich.edu className = self.className 4237967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4247967Sgblack@eecs.umich.edu className += "Imm" 4257967Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 4267967Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4277967Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4287967Sgblack@eecs.umich.edu "class_name" : className, 4297967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4307967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4317967Sgblack@eecs.umich.edu "dest" : self.dest, 4327967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4337967Sgblack@eecs.umich.edu "ext" : self.ext} 4347967Sgblack@eecs.umich.edu return allocator 4354519Sgblack@eecs.umich.edu 4365040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4374688Sgblack@eecs.umich.edu abstract = True 4385040Sgblack@eecs.umich.edu flag_code = ''' 4395040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4405115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4419212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 4429212Snilay@cs.wisc.edu PredezfBit, ext & ~mask, result, psrc1, op2); 4439212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 4449212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 4459212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 4469010Snilay@cs.wisc.edu 4475040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4489212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~((CFBit | OFBit) & ext); 4499212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ECFBit & ext); 4505040Sgblack@eecs.umich.edu ''' 4514519Sgblack@eecs.umich.edu 4525040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4535040Sgblack@eecs.umich.edu abstract = True 4549010Snilay@cs.wisc.edu flag_code = ''' 4559212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PredcfofBits | 4569212Snilay@cs.wisc.edu PreddfBit | PredecfBit | PredezfBit, 4579212Snilay@cs.wisc.edu ext, result, psrc1, op2); 4589212Snilay@cs.wisc.edu 4599212Snilay@cs.wisc.edu PredcfofBits = newFlags & cfofMask; 4609212Snilay@cs.wisc.edu PredecfBit = newFlags & ECFBit; 4619212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 4629212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 4639212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 4649010Snilay@cs.wisc.edu ''' 4654519Sgblack@eecs.umich.edu 4665040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4675040Sgblack@eecs.umich.edu abstract = True 4689010Snilay@cs.wisc.edu flag_code = ''' 4699212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PredcfofBits | 4709212Snilay@cs.wisc.edu PreddfBit | PredecfBit | PredezfBit, 4719212Snilay@cs.wisc.edu ext, result, psrc1, ~op2, true); 4729212Snilay@cs.wisc.edu 4739212Snilay@cs.wisc.edu PredcfofBits = newFlags & cfofMask; 4749212Snilay@cs.wisc.edu PredecfBit = newFlags & ECFBit; 4759212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 4769212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 4779212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 4789010Snilay@cs.wisc.edu ''' 4794519Sgblack@eecs.umich.edu 4805040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4815040Sgblack@eecs.umich.edu abstract = True 4829211Snilay@cs.wisc.edu cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | ecfBit | \ 4839211Snilay@cs.wisc.edu ezfBit, ext)" 4847894SBrad.Beckmann@amd.com cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];" 4854519Sgblack@eecs.umich.edu 4865063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4875063Sgblack@eecs.umich.edu abstract = True 4885063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4895063Sgblack@eecs.umich.edu if not src1: 4905063Sgblack@eecs.umich.edu src1 = dest 4916345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4926345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4935063Sgblack@eecs.umich.edu 4945063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4955063Sgblack@eecs.umich.edu abstract = True 4965063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4976345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4986345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 4995063Sgblack@eecs.umich.edu 5005040Sgblack@eecs.umich.edu class Add(FlagRegOp): 5017969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' 5027969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' 5034595Sgblack@eecs.umich.edu 5045040Sgblack@eecs.umich.edu class Or(LogicRegOp): 5057969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' 5067969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' 5074595Sgblack@eecs.umich.edu 5085040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 5095040Sgblack@eecs.umich.edu code = ''' 5109010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5117969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); 5125040Sgblack@eecs.umich.edu ''' 5137967Sgblack@eecs.umich.edu big_code = ''' 5149010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5157969Sgblack@eecs.umich.edu DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); 5167967Sgblack@eecs.umich.edu ''' 5175040Sgblack@eecs.umich.edu 5185040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 5195040Sgblack@eecs.umich.edu code = ''' 5209010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5217969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); 5225040Sgblack@eecs.umich.edu ''' 5237967Sgblack@eecs.umich.edu big_code = ''' 5249010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5257969Sgblack@eecs.umich.edu DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); 5267967Sgblack@eecs.umich.edu ''' 5275040Sgblack@eecs.umich.edu 5285040Sgblack@eecs.umich.edu class And(LogicRegOp): 5297969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' 5307969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' 5315040Sgblack@eecs.umich.edu 5325040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5337969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' 5347969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' 5355040Sgblack@eecs.umich.edu 5365040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5377969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' 5387969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)' 5395040Sgblack@eecs.umich.edu 5405063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5415040Sgblack@eecs.umich.edu code = ''' 5425063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5435063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5446742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5456430Sgblack@eecs.umich.edu uint64_t hiResult; 5466430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5476430Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5486461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5496430Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5506430Sgblack@eecs.umich.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5516430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 5526430Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5536462Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 5546430Sgblack@eecs.umich.edu hiResult -= op2; 5556462Sgblack@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 5566430Sgblack@eecs.umich.edu hiResult -= psrc1; 5576430Sgblack@eecs.umich.edu ProdHi = hiResult; 5585040Sgblack@eecs.umich.edu ''' 5596463Sgblack@eecs.umich.edu flag_code = ''' 5606463Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 5616463Sgblack@eecs.umich.edu bits(ProdLow, dataSize * 8 - 1)) { 5629212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & (CFBit | OFBit)); 5639212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 5646463Sgblack@eecs.umich.edu } else { 5659212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 5669212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 5676463Sgblack@eecs.umich.edu } 5686463Sgblack@eecs.umich.edu ''' 5695040Sgblack@eecs.umich.edu 5705063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5715040Sgblack@eecs.umich.edu code = ''' 5725063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5734809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5746742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5756430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5765063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5776461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5785063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5795063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5806430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) / shifter) + 5815063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5825040Sgblack@eecs.umich.edu ''' 5836463Sgblack@eecs.umich.edu flag_code = ''' 5846463Sgblack@eecs.umich.edu if (ProdHi) { 5859212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & (CFBit | OFBit)); 5869212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 5876463Sgblack@eecs.umich.edu } else { 5889212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 5899212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 5906463Sgblack@eecs.umich.edu } 5916463Sgblack@eecs.umich.edu ''' 5925040Sgblack@eecs.umich.edu 5935063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5945063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5957967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdLow & mask(dataSize * 8);' 5965040Sgblack@eecs.umich.edu 5975063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5985063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5995063Sgblack@eecs.umich.edu if not src1: 6005063Sgblack@eecs.umich.edu src1 = dest 6016345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 6026345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 6035063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 6047967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdHi & mask(dataSize * 8);' 6055062Sgblack@eecs.umich.edu 6065075Sgblack@eecs.umich.edu # One or two bit divide 6075075Sgblack@eecs.umich.edu class Div1(WrRegOp): 6085040Sgblack@eecs.umich.edu code = ''' 6095075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 6105075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 6115075Sgblack@eecs.umich.edu uint64_t quotient = 0; 6125075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 6135075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 6145075Sgblack@eecs.umich.edu //a source. 6155075Sgblack@eecs.umich.edu uint64_t divisor = op2; 6165075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 6175075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 6185075Sgblack@eecs.umich.edu //Do the division. 6197719Sgblack@eecs.umich.edu if (divisor == 0) { 6207719Sgblack@eecs.umich.edu fault = new DivideByZero; 6217719Sgblack@eecs.umich.edu } else { 6227719Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6237719Sgblack@eecs.umich.edu //Record the final results. 6247719Sgblack@eecs.umich.edu Remainder = remainder; 6257719Sgblack@eecs.umich.edu Quotient = quotient; 6267719Sgblack@eecs.umich.edu Divisor = divisor; 6277719Sgblack@eecs.umich.edu } 6285040Sgblack@eecs.umich.edu ''' 6294823Sgblack@eecs.umich.edu 6305075Sgblack@eecs.umich.edu # Step divide 6315075Sgblack@eecs.umich.edu class Div2(RegOp): 6327967Sgblack@eecs.umich.edu divCode = ''' 6335075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 6345075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 6355075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 6365075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 6375075Sgblack@eecs.umich.edu int remaining = op2; 6385075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 6395075Sgblack@eecs.umich.edu //little. 6407719Sgblack@eecs.umich.edu if (divisor == 0) { 6417719Sgblack@eecs.umich.edu fault = new DivideByZero; 6427719Sgblack@eecs.umich.edu } else if (remaining) { 6437070Sgblack@eecs.umich.edu if (divisor & (ULL(1) << 63)) { 6447070Sgblack@eecs.umich.edu while (remaining && !(dividend & (ULL(1) << 63))) { 6457070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6467070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6477070Sgblack@eecs.umich.edu quotient <<= 1; 6487070Sgblack@eecs.umich.edu remaining--; 6497070Sgblack@eecs.umich.edu } 6507070Sgblack@eecs.umich.edu if (dividend & (ULL(1) << 63)) { 6517080Sgblack@eecs.umich.edu bool highBit = false; 6527070Sgblack@eecs.umich.edu if (dividend < divisor && remaining) { 6537080Sgblack@eecs.umich.edu highBit = true; 6547070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6557070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6567070Sgblack@eecs.umich.edu quotient <<= 1; 6577070Sgblack@eecs.umich.edu remaining--; 6587070Sgblack@eecs.umich.edu } 6597080Sgblack@eecs.umich.edu if (highBit || divisor <= dividend) { 6607080Sgblack@eecs.umich.edu quotient++; 6617080Sgblack@eecs.umich.edu dividend -= divisor; 6627080Sgblack@eecs.umich.edu } 6637070Sgblack@eecs.umich.edu } 6647070Sgblack@eecs.umich.edu remainder = dividend; 6657070Sgblack@eecs.umich.edu } else { 6667070Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 6677070Sgblack@eecs.umich.edu while (dividend < divisor && remaining) { 6687070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6697070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6707070Sgblack@eecs.umich.edu quotient <<= 1; 6717070Sgblack@eecs.umich.edu remaining--; 6727070Sgblack@eecs.umich.edu } 6737070Sgblack@eecs.umich.edu remainder = dividend; 6747070Sgblack@eecs.umich.edu //Do the division. 6757070Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6765075Sgblack@eecs.umich.edu } 6775075Sgblack@eecs.umich.edu } 6785075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 6797967Sgblack@eecs.umich.edu %s 6805075Sgblack@eecs.umich.edu //Record the final results 6815075Sgblack@eecs.umich.edu Remainder = remainder; 6825075Sgblack@eecs.umich.edu Quotient = quotient; 6835075Sgblack@eecs.umich.edu ''' 6847967Sgblack@eecs.umich.edu code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" 6857967Sgblack@eecs.umich.edu big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" 6865075Sgblack@eecs.umich.edu flag_code = ''' 6877480Sgblack@eecs.umich.edu if (remaining == 0) 6889212Snilay@cs.wisc.edu PredezfBit = PredezfBit | (ext & EZFBit); 6895075Sgblack@eecs.umich.edu else 6909212Snilay@cs.wisc.edu PredezfBit = PredezfBit & ~(ext & EZFBit); 6915075Sgblack@eecs.umich.edu ''' 6924732Sgblack@eecs.umich.edu 6935075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6945075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6957967Sgblack@eecs.umich.edu big_code = 'DestReg = Quotient & mask(dataSize * 8);' 6965075Sgblack@eecs.umich.edu 6975075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6985075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6997967Sgblack@eecs.umich.edu big_code = 'DestReg = Remainder & mask(dataSize * 8);' 7005040Sgblack@eecs.umich.edu 7015040Sgblack@eecs.umich.edu class Mov(CondRegOp): 7025040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 7036482Sgblack@eecs.umich.edu else_code = 'DestReg = DestReg;' 7045040Sgblack@eecs.umich.edu 7054732Sgblack@eecs.umich.edu # Shift instructions 7065040Sgblack@eecs.umich.edu 7075076Sgblack@eecs.umich.edu class Sll(RegOp): 7085040Sgblack@eecs.umich.edu code = ''' 7094756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7104823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 7115040Sgblack@eecs.umich.edu ''' 7127967Sgblack@eecs.umich.edu big_code = ''' 7137967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7147967Sgblack@eecs.umich.edu DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); 7157967Sgblack@eecs.umich.edu ''' 7165076Sgblack@eecs.umich.edu flag_code = ''' 7175076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7185076Sgblack@eecs.umich.edu if (shiftAmt) { 7195076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7205076Sgblack@eecs.umich.edu //worry about setting them. 7219212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 7229212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 7239010Snilay@cs.wisc.edu 7245076Sgblack@eecs.umich.edu int CFBits = 0; 7255076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 7266441Sgblack@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 7276441Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 7285076Sgblack@eecs.umich.edu CFBits = 1; 7296441Sgblack@eecs.umich.edu } 7309010Snilay@cs.wisc.edu 7315076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7329010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 7339212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 7349212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 7359010Snilay@cs.wisc.edu } 7369010Snilay@cs.wisc.edu 7375076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7385076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 7399212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 7409010Snilay@cs.wisc.edu 7415076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7429212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 7439212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 7449212Snilay@cs.wisc.edu DestReg, psrc1, op2); 7459212Snilay@cs.wisc.edu 7469212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 7479212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 7489212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 7495076Sgblack@eecs.umich.edu } 7505076Sgblack@eecs.umich.edu ''' 7515040Sgblack@eecs.umich.edu 7525076Sgblack@eecs.umich.edu class Srl(RegOp): 7537967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 7547967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to mask them out 7557967Sgblack@eecs.umich.edu # to be sure they're zero. 7565040Sgblack@eecs.umich.edu code = ''' 7574756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7584732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7594823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 7605040Sgblack@eecs.umich.edu ''' 7617967Sgblack@eecs.umich.edu big_code = ''' 7627967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7637967Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7647967Sgblack@eecs.umich.edu DestReg = (psrc1 >> shiftAmt) & logicalMask; 7657967Sgblack@eecs.umich.edu ''' 7665076Sgblack@eecs.umich.edu flag_code = ''' 7675076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7685076Sgblack@eecs.umich.edu if (shiftAmt) { 7695076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7705076Sgblack@eecs.umich.edu //worry about setting them. 7719212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 7729212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 7739010Snilay@cs.wisc.edu 7745076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7756442Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7766442Sgblack@eecs.umich.edu shiftAmt <= dataSize * 8 && 7776442Sgblack@eecs.umich.edu bits(SrcReg1, shiftAmt - 1)) { 7789212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 7799212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 7806442Sgblack@eecs.umich.edu } 7819010Snilay@cs.wisc.edu 7825076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7835076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 7849212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 7859010Snilay@cs.wisc.edu 7865076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7879212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 7889212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 7899212Snilay@cs.wisc.edu DestReg, psrc1, op2); 7909212Snilay@cs.wisc.edu 7919212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 7929212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 7939212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 7945076Sgblack@eecs.umich.edu } 7955076Sgblack@eecs.umich.edu ''' 7965040Sgblack@eecs.umich.edu 7975076Sgblack@eecs.umich.edu class Sra(RegOp): 7987967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 7997967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to sign extend 8007967Sgblack@eecs.umich.edu # them manually to be sure. 8015040Sgblack@eecs.umich.edu code = ''' 8024756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8036443Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 8045032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 8054823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 8065040Sgblack@eecs.umich.edu ''' 8077967Sgblack@eecs.umich.edu big_code = ''' 8087967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8097967Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 8107967Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 8117967Sgblack@eecs.umich.edu DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); 8127967Sgblack@eecs.umich.edu ''' 8135076Sgblack@eecs.umich.edu flag_code = ''' 8145076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8155076Sgblack@eecs.umich.edu if (shiftAmt) { 8165076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8175076Sgblack@eecs.umich.edu //worry about setting them. 8189212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 8199212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 8209010Snilay@cs.wisc.edu 8215076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8226444Sgblack@eecs.umich.edu uint8_t effectiveShift = 8236444Sgblack@eecs.umich.edu (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 8246444Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8256444Sgblack@eecs.umich.edu bits(SrcReg1, effectiveShift - 1)) { 8269212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 8279212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 8286444Sgblack@eecs.umich.edu } 8299010Snilay@cs.wisc.edu 8305076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8319212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 8329212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 8339212Snilay@cs.wisc.edu DestReg, psrc1, op2); 8349212Snilay@cs.wisc.edu 8359212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 8369212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 8379212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 8385076Sgblack@eecs.umich.edu } 8395076Sgblack@eecs.umich.edu ''' 8405040Sgblack@eecs.umich.edu 8415076Sgblack@eecs.umich.edu class Ror(RegOp): 8425040Sgblack@eecs.umich.edu code = ''' 8434732Sgblack@eecs.umich.edu uint8_t shiftAmt = 8444756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8456449Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 8467967Sgblack@eecs.umich.edu if (realShiftAmt) { 8476449Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 8486449Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 8494732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8507967Sgblack@eecs.umich.edu } else 8516447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8525040Sgblack@eecs.umich.edu ''' 8535076Sgblack@eecs.umich.edu flag_code = ''' 8545076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8555076Sgblack@eecs.umich.edu if (shiftAmt) { 8565076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8575076Sgblack@eecs.umich.edu //worry about setting them. 8589212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 8599212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 8609010Snilay@cs.wisc.edu 8615076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 8625076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8635076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 8645076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8659010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && msb) { 8669212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 8679212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 8689010Snilay@cs.wisc.edu } 8699010Snilay@cs.wisc.edu 8705076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8715076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 8729212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 8739010Snilay@cs.wisc.edu 8745076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8759212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 8769212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 8779212Snilay@cs.wisc.edu DestReg, psrc1, op2); 8789212Snilay@cs.wisc.edu 8799212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 8809212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 8819212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 8825076Sgblack@eecs.umich.edu } 8835076Sgblack@eecs.umich.edu ''' 8845040Sgblack@eecs.umich.edu 8855076Sgblack@eecs.umich.edu class Rcr(RegOp): 8865040Sgblack@eecs.umich.edu code = ''' 8874733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8884756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8896454Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 8907967Sgblack@eecs.umich.edu if (realShiftAmt) { 8919010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 8926454Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 8936454Sgblack@eecs.umich.edu if (realShiftAmt > 1) 8946454Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 8956454Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 8964733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8977967Sgblack@eecs.umich.edu } else 8986447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8995040Sgblack@eecs.umich.edu ''' 9005076Sgblack@eecs.umich.edu flag_code = ''' 9015076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9025076Sgblack@eecs.umich.edu if (shiftAmt) { 9039010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 9045076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9055076Sgblack@eecs.umich.edu //worry about setting them. 9069212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 9079212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 9089010Snilay@cs.wisc.edu 9095076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9106453Sgblack@eecs.umich.edu if ((ext & OFBit) && (origCFBit ^ 9116453Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) { 9129212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 9136453Sgblack@eecs.umich.edu } 9145076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9156454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 9166454Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : 9176454Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) { 9189212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 9199212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 9206454Sgblack@eecs.umich.edu } 9219010Snilay@cs.wisc.edu 9225076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9239212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 9249212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 9259212Snilay@cs.wisc.edu DestReg, psrc1, op2); 9269212Snilay@cs.wisc.edu 9279212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 9289212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 9299212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 9305076Sgblack@eecs.umich.edu } 9315076Sgblack@eecs.umich.edu ''' 9325040Sgblack@eecs.umich.edu 9335076Sgblack@eecs.umich.edu class Rol(RegOp): 9345040Sgblack@eecs.umich.edu code = ''' 9354732Sgblack@eecs.umich.edu uint8_t shiftAmt = 9364756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9376446Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 9387967Sgblack@eecs.umich.edu if (realShiftAmt) { 9396446Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 9404732Sgblack@eecs.umich.edu uint64_t bottom = 9416446Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 9424732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9437967Sgblack@eecs.umich.edu } else 9446447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9455040Sgblack@eecs.umich.edu ''' 9465076Sgblack@eecs.umich.edu flag_code = ''' 9475076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9485076Sgblack@eecs.umich.edu if (shiftAmt) { 9495076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9505076Sgblack@eecs.umich.edu //worry about setting them. 9519212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 9529212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 9539010Snilay@cs.wisc.edu 9545076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 9555076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 9565076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 9575076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9589010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && lsb) { 9599212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 9609212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 9619010Snilay@cs.wisc.edu } 9629010Snilay@cs.wisc.edu 9635076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9645076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 9659212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 9669010Snilay@cs.wisc.edu 9675076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9689212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 9699212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 9709212Snilay@cs.wisc.edu DestReg, psrc1, op2); 9719212Snilay@cs.wisc.edu 9729212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 9739212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 9749212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 9755076Sgblack@eecs.umich.edu } 9765076Sgblack@eecs.umich.edu ''' 9775040Sgblack@eecs.umich.edu 9785076Sgblack@eecs.umich.edu class Rcl(RegOp): 9795040Sgblack@eecs.umich.edu code = ''' 9804733Sgblack@eecs.umich.edu uint8_t shiftAmt = 9814756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9826456Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 9837967Sgblack@eecs.umich.edu if (realShiftAmt) { 9849010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 9856456Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 9866456Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (realShiftAmt - 1); 9874733Sgblack@eecs.umich.edu if(shiftAmt > 1) 9884733Sgblack@eecs.umich.edu bottom |= 9894823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 9906456Sgblack@eecs.umich.edu dataSize * 8 - realShiftAmt + 1); 9914733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9927967Sgblack@eecs.umich.edu } else 9936447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9945040Sgblack@eecs.umich.edu ''' 9955076Sgblack@eecs.umich.edu flag_code = ''' 9965076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9975076Sgblack@eecs.umich.edu if (shiftAmt) { 9989010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 9995076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10005076Sgblack@eecs.umich.edu //worry about setting them. 10019212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 10029212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 10039010Snilay@cs.wisc.edu 10045076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 10056456Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 10065076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10076456Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 10089010Snilay@cs.wisc.edu (realShiftAmt == 0) ? origCFBit : CFBits) { 10099212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 10109212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 10119010Snilay@cs.wisc.edu } 10129010Snilay@cs.wisc.edu 10135076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10145076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 10159212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 10169010Snilay@cs.wisc.edu 10175076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10189212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 10199212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 10209212Snilay@cs.wisc.edu DestReg, psrc1, op2); 10219212Snilay@cs.wisc.edu 10229212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 10239212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 10249212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 10255076Sgblack@eecs.umich.edu } 10265076Sgblack@eecs.umich.edu ''' 10274732Sgblack@eecs.umich.edu 10286479Sgblack@eecs.umich.edu class Sld(RegOp): 10297967Sgblack@eecs.umich.edu sldCode = ''' 10306479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 10316479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 10327967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 10336479Sgblack@eecs.umich.edu uint64_t result; 10346479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 10356479Sgblack@eecs.umich.edu result = psrc1; 10366479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 10376479Sgblack@eecs.umich.edu result = (psrc1 << realShiftAmt) | 10386479Sgblack@eecs.umich.edu (DoubleBits >> (dataBits - realShiftAmt)); 10396479Sgblack@eecs.umich.edu } else { 10406479Sgblack@eecs.umich.edu result = (DoubleBits << (realShiftAmt - dataBits)) | 10416479Sgblack@eecs.umich.edu (psrc1 >> (2 * dataBits - realShiftAmt)); 10426479Sgblack@eecs.umich.edu } 10437967Sgblack@eecs.umich.edu %s 10446479Sgblack@eecs.umich.edu ''' 10457967Sgblack@eecs.umich.edu code = sldCode % "DestReg = merge(DestReg, result, dataSize);" 10467967Sgblack@eecs.umich.edu big_code = sldCode % "DestReg = result & mask(dataSize * 8);" 10476479Sgblack@eecs.umich.edu flag_code = ''' 10486479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10496479Sgblack@eecs.umich.edu if (shiftAmt) { 10506479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10516479Sgblack@eecs.umich.edu //worry about setting them. 10529212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 10539212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 10546479Sgblack@eecs.umich.edu int CFBits = 0; 10559010Snilay@cs.wisc.edu 10566479Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 10576479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 10586479Sgblack@eecs.umich.edu bits(DoubleBits, 0)) || 10596479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 10606479Sgblack@eecs.umich.edu bits(SrcReg1, dataBits - realShiftAmt)) || 10616479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 10626479Sgblack@eecs.umich.edu bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 10636479Sgblack@eecs.umich.edu CFBits = 1; 10646479Sgblack@eecs.umich.edu } 10659010Snilay@cs.wisc.edu 10666479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10679010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 10689212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 10699212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 10709010Snilay@cs.wisc.edu } 10719010Snilay@cs.wisc.edu 10726479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10736479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 10746479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 10759212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 10769010Snilay@cs.wisc.edu 10776479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10789212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 10799212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 10809212Snilay@cs.wisc.edu DestReg, psrc1, op2); 10819212Snilay@cs.wisc.edu 10829212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 10839212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 10849212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 10856479Sgblack@eecs.umich.edu } 10866479Sgblack@eecs.umich.edu ''' 10876479Sgblack@eecs.umich.edu 10886479Sgblack@eecs.umich.edu class Srd(RegOp): 10897967Sgblack@eecs.umich.edu srdCode = ''' 10906479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 10916479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 10927967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 10936479Sgblack@eecs.umich.edu uint64_t result; 10946479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 10956479Sgblack@eecs.umich.edu result = psrc1; 10966479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 10976479Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right 10986479Sgblack@eecs.umich.edu // shift is not defined in the C/C++ standard, we have to 10996479Sgblack@eecs.umich.edu // mask them out to be sure they're zero. 11006479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataBits - realShiftAmt); 11016479Sgblack@eecs.umich.edu result = ((psrc1 >> realShiftAmt) & logicalMask) | 11026479Sgblack@eecs.umich.edu (DoubleBits << (dataBits - realShiftAmt)); 11036479Sgblack@eecs.umich.edu } else { 11046479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 11056479Sgblack@eecs.umich.edu result = ((DoubleBits >> (realShiftAmt - dataBits)) & 11066479Sgblack@eecs.umich.edu logicalMask) | 11076479Sgblack@eecs.umich.edu (psrc1 << (2 * dataBits - realShiftAmt)); 11086479Sgblack@eecs.umich.edu } 11097967Sgblack@eecs.umich.edu %s 11106479Sgblack@eecs.umich.edu ''' 11117967Sgblack@eecs.umich.edu code = srdCode % "DestReg = merge(DestReg, result, dataSize);" 11127967Sgblack@eecs.umich.edu big_code = srdCode % "DestReg = result & mask(dataSize * 8);" 11136479Sgblack@eecs.umich.edu flag_code = ''' 11146479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 11156479Sgblack@eecs.umich.edu if (shiftAmt) { 11166479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 11176479Sgblack@eecs.umich.edu //worry about setting them. 11189212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 11199212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 11206479Sgblack@eecs.umich.edu int CFBits = 0; 11219010Snilay@cs.wisc.edu 11226479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11236479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 11246479Sgblack@eecs.umich.edu bits(DoubleBits, dataBits - 1)) || 11256479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 11266479Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) || 11276479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 11286479Sgblack@eecs.umich.edu bits(DoubleBits, realShiftAmt - dataBits - 1))) { 11296479Sgblack@eecs.umich.edu CFBits = 1; 11306479Sgblack@eecs.umich.edu } 11319010Snilay@cs.wisc.edu 11326479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11339010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 11349212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 11359212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 11369010Snilay@cs.wisc.edu } 11379010Snilay@cs.wisc.edu 11386479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 11396479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 11406479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 11419212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 11429010Snilay@cs.wisc.edu 11436479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 11449212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 11459212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 11469212Snilay@cs.wisc.edu DestReg, psrc1, op2); 11479212Snilay@cs.wisc.edu 11489212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 11499212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 11509212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 11516479Sgblack@eecs.umich.edu } 11526479Sgblack@eecs.umich.edu ''' 11536479Sgblack@eecs.umich.edu 11546479Sgblack@eecs.umich.edu class Mdb(WrRegOp): 11556479Sgblack@eecs.umich.edu code = 'DoubleBits = psrc1 ^ op2;' 11566479Sgblack@eecs.umich.edu 11575040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 11587789Sgblack@eecs.umich.edu code = 'NRIP = psrc1 + sop2 + CSBase;' 11597789Sgblack@eecs.umich.edu else_code = "NRIP = NRIP;" 11605040Sgblack@eecs.umich.edu 11615040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 11629010Snilay@cs.wisc.edu code = ''' 11639010Snilay@cs.wisc.edu uint64_t newFlags = psrc1 ^ op2; 11649010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 11659010Snilay@cs.wisc.edu ecfBit = newFlags & ECFBit; 11669010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 11679211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 11689010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11699010Snilay@cs.wisc.edu ''' 11705040Sgblack@eecs.umich.edu 11715426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 11725426Sgblack@eecs.umich.edu code = ''' 11735426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 11745426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 11759010Snilay@cs.wisc.edu 11765426Sgblack@eecs.umich.edu // Get only the user flags 11779010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11789211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 11799010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 11809010Snilay@cs.wisc.edu ecfBit = 0; 11819010Snilay@cs.wisc.edu ezfBit = 0; 11829010Snilay@cs.wisc.edu 11835426Sgblack@eecs.umich.edu // Get everything else 11845426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 11855426Sgblack@eecs.umich.edu ''' 11865426Sgblack@eecs.umich.edu 11875040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 11887789Sgblack@eecs.umich.edu code = 'DestReg = NRIP - CSBase;' 11895040Sgblack@eecs.umich.edu 11905040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 11919211Snilay@cs.wisc.edu code = 'DestReg = ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit;' 11925040Sgblack@eecs.umich.edu 11935426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 11949010Snilay@cs.wisc.edu code = ''' 11959211Snilay@cs.wisc.edu DestReg = ccFlagBits | cfofBits | dfBit | 11969211Snilay@cs.wisc.edu ecfBit | ezfBit | nccFlagBits; 11979010Snilay@cs.wisc.edu ''' 11985426Sgblack@eecs.umich.edu 11995040Sgblack@eecs.umich.edu class Ruflag(RegOp): 12005040Sgblack@eecs.umich.edu code = ''' 12019211Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | dfBit | 12029211Snilay@cs.wisc.edu ecfBit | ezfBit, imm8); 12034951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 12049010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12055040Sgblack@eecs.umich.edu ''' 12069010Snilay@cs.wisc.edu 12077967Sgblack@eecs.umich.edu big_code = ''' 12089211Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | dfBit | 12099211Snilay@cs.wisc.edu ecfBit | ezfBit, imm8); 12107967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 12119010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12127967Sgblack@eecs.umich.edu ''' 12139010Snilay@cs.wisc.edu 12145040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 12155040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 12165040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 12176345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 12184732Sgblack@eecs.umich.edu 12195426Sgblack@eecs.umich.edu class Rflag(RegOp): 12205426Sgblack@eecs.umich.edu code = ''' 12215426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 12229211Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | 12239010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 12249010Snilay@cs.wisc.edu 12255426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 12265426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 12279010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12285426Sgblack@eecs.umich.edu ''' 12299010Snilay@cs.wisc.edu 12307967Sgblack@eecs.umich.edu big_code = ''' 12317967Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 12329211Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | 12339010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 12349010Snilay@cs.wisc.edu 12357967Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 12367967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 12379010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12387967Sgblack@eecs.umich.edu ''' 12399010Snilay@cs.wisc.edu 12405426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 12415426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 12425426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 12436345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 12445426Sgblack@eecs.umich.edu 12455040Sgblack@eecs.umich.edu class Sext(RegOp): 12465040Sgblack@eecs.umich.edu code = ''' 12474823Sgblack@eecs.umich.edu IntReg val = psrc1; 12485239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 12495239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 12505239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 12515239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 12525007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 12535007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 12545040Sgblack@eecs.umich.edu ''' 12559010Snilay@cs.wisc.edu 12567967Sgblack@eecs.umich.edu big_code = ''' 12577967Sgblack@eecs.umich.edu IntReg val = psrc1; 12587967Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 12597967Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 12607967Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 12617967Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 12627967Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 12637967Sgblack@eecs.umich.edu DestReg = val & mask(dataSize * 8); 12647967Sgblack@eecs.umich.edu ''' 12659010Snilay@cs.wisc.edu 12665239Sgblack@eecs.umich.edu flag_code = ''' 12679010Snilay@cs.wisc.edu if (!sign_bit) { 12689212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits & ~(ext & (ZFBit)); 12699212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit)); 12709212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 12719212Snilay@cs.wisc.edu PredezfBit = PredezfBit & ~(ext & EZFBit); 12729010Snilay@cs.wisc.edu } else { 12739212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits | (ext & (ZFBit)); 12749212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & (CFBit)); 12759212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 12769212Snilay@cs.wisc.edu PredezfBit = PredezfBit | (ext & EZFBit); 12779010Snilay@cs.wisc.edu } 12785239Sgblack@eecs.umich.edu ''' 12794714Sgblack@eecs.umich.edu 12805040Sgblack@eecs.umich.edu class Zext(RegOp): 12815927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 12827967Sgblack@eecs.umich.edu big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' 12835241Sgblack@eecs.umich.edu 12845926Sgblack@eecs.umich.edu class Rddr(RegOp): 12855926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12865926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 12876345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12887967Sgblack@eecs.umich.edu rdrCode = ''' 12895926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 12905926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 12915926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 12925926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 12935926Sgblack@eecs.umich.edu } else if (dr7.gd) { 12945926Sgblack@eecs.umich.edu fault = new DebugException(); 12955926Sgblack@eecs.umich.edu } else { 12967967Sgblack@eecs.umich.edu %s 12975926Sgblack@eecs.umich.edu } 12985926Sgblack@eecs.umich.edu ''' 12997967Sgblack@eecs.umich.edu code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" 13007967Sgblack@eecs.umich.edu big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" 13015926Sgblack@eecs.umich.edu 13025926Sgblack@eecs.umich.edu class Wrdr(RegOp): 13035926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13045926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 13056345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13065926Sgblack@eecs.umich.edu code = ''' 13075926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 13085926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 13095926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 13105926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13116345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 13125926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 13135926Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13145926Sgblack@eecs.umich.edu } else if (dr7.gd) { 13155926Sgblack@eecs.umich.edu fault = new DebugException(); 13165926Sgblack@eecs.umich.edu } else { 13175926Sgblack@eecs.umich.edu DebugDest = psrc1; 13185926Sgblack@eecs.umich.edu } 13195926Sgblack@eecs.umich.edu ''' 13205926Sgblack@eecs.umich.edu 13215296Sgblack@eecs.umich.edu class Rdcr(RegOp): 13225296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13235296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 13246345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13257967Sgblack@eecs.umich.edu rdcrCode = ''' 13265924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 13275296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13285296Sgblack@eecs.umich.edu } else { 13297967Sgblack@eecs.umich.edu %s 13305296Sgblack@eecs.umich.edu } 13315296Sgblack@eecs.umich.edu ''' 13327967Sgblack@eecs.umich.edu code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" 13337967Sgblack@eecs.umich.edu big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" 13345296Sgblack@eecs.umich.edu 13355241Sgblack@eecs.umich.edu class Wrcr(RegOp): 13365241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13375241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 13386345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13395241Sgblack@eecs.umich.edu code = ''' 13405241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 13415241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13425241Sgblack@eecs.umich.edu } else { 13435241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 13445241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 13455241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 13465241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 13475241Sgblack@eecs.umich.edu 13485241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 13495241Sgblack@eecs.umich.edu switch(dest) { 13505241Sgblack@eecs.umich.edu case 0: 13515241Sgblack@eecs.umich.edu { 13525241Sgblack@eecs.umich.edu Efer efer = EferOp; 13535241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 13545241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 13555241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 13565241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 13575241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 13585241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 13595241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13605241Sgblack@eecs.umich.edu } 13615241Sgblack@eecs.umich.edu break; 13625241Sgblack@eecs.umich.edu case 2: 13635241Sgblack@eecs.umich.edu break; 13645241Sgblack@eecs.umich.edu case 3: 13655241Sgblack@eecs.umich.edu break; 13665241Sgblack@eecs.umich.edu case 4: 13675241Sgblack@eecs.umich.edu { 13685241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 13695241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 13705241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 13715241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 13725241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13735241Sgblack@eecs.umich.edu } 13745241Sgblack@eecs.umich.edu break; 13755241Sgblack@eecs.umich.edu case 8: 13765241Sgblack@eecs.umich.edu { 13775241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 13785241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13795241Sgblack@eecs.umich.edu } 13805241Sgblack@eecs.umich.edu default: 13818857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 13828857Sgblack@eecs.umich.edu "Unrecognized control register %d.\\n", dest); 13835241Sgblack@eecs.umich.edu } 13845241Sgblack@eecs.umich.edu ControlDest = newVal; 13855241Sgblack@eecs.umich.edu } 13865241Sgblack@eecs.umich.edu ''' 13875290Sgblack@eecs.umich.edu 13885294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 13895672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 13905294Sgblack@eecs.umich.edu abstract = True 13915290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13925294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 13936345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13945294Sgblack@eecs.umich.edu 13955294Sgblack@eecs.umich.edu class Wrbase(SegOp): 13965290Sgblack@eecs.umich.edu code = ''' 13975294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 13985290Sgblack@eecs.umich.edu ''' 13995290Sgblack@eecs.umich.edu 14005294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 14015290Sgblack@eecs.umich.edu code = ''' 14025294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 14035294Sgblack@eecs.umich.edu ''' 14045294Sgblack@eecs.umich.edu 14055294Sgblack@eecs.umich.edu class Wrsel(SegOp): 14065294Sgblack@eecs.umich.edu code = ''' 14075294Sgblack@eecs.umich.edu SegSelDest = psrc1; 14085294Sgblack@eecs.umich.edu ''' 14095294Sgblack@eecs.umich.edu 14105905Sgblack@eecs.umich.edu class WrAttr(SegOp): 14115905Sgblack@eecs.umich.edu code = ''' 14125905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 14135905Sgblack@eecs.umich.edu ''' 14145905Sgblack@eecs.umich.edu 14155294Sgblack@eecs.umich.edu class Rdbase(SegOp): 14167967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' 14177967Sgblack@eecs.umich.edu big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' 14185294Sgblack@eecs.umich.edu 14195294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 14207967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' 14217967Sgblack@eecs.umich.edu big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' 14225294Sgblack@eecs.umich.edu 14235427Sgblack@eecs.umich.edu class RdAttr(SegOp): 14247967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' 14257967Sgblack@eecs.umich.edu big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' 14265427Sgblack@eecs.umich.edu 14275294Sgblack@eecs.umich.edu class Rdsel(SegOp): 14287967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' 14297967Sgblack@eecs.umich.edu big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' 14305294Sgblack@eecs.umich.edu 14315682Sgblack@eecs.umich.edu class Rdval(RegOp): 14325682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14336345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 14346345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14355682Sgblack@eecs.umich.edu code = ''' 14365682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 14375682Sgblack@eecs.umich.edu ''' 14385682Sgblack@eecs.umich.edu 14395682Sgblack@eecs.umich.edu class Wrval(RegOp): 14405682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14416345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 14426345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14435682Sgblack@eecs.umich.edu code = ''' 14445682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 14455682Sgblack@eecs.umich.edu ''' 14465682Sgblack@eecs.umich.edu 14475428Sgblack@eecs.umich.edu class Chks(RegOp): 14485428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 14495428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 14505428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 14515428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 14525294Sgblack@eecs.umich.edu code = ''' 14535424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 14545433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 14555433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 14565433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 14575294Sgblack@eecs.umich.edu 14585428Sgblack@eecs.umich.edu switch (imm8) 14595428Sgblack@eecs.umich.edu { 14605428Sgblack@eecs.umich.edu case SegNoCheck: 14615428Sgblack@eecs.umich.edu break; 14625428Sgblack@eecs.umich.edu case SegCSCheck: 14636060Sgblack@eecs.umich.edu // Make sure it's the right type 14646060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 14656060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14666060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 14676060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14686060Sgblack@eecs.umich.edu } 14695428Sgblack@eecs.umich.edu break; 14705428Sgblack@eecs.umich.edu case SegCallGateCheck: 14718857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault("CS checks for far " 14728857Sgblack@eecs.umich.edu "calls/jumps through call gates not implemented.\\n"); 14735428Sgblack@eecs.umich.edu break; 14745855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 14755853Sgblack@eecs.umich.edu // Check permissions. 14765674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 14775857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14786058Sgblack@eecs.umich.edu break; 14795674Sgblack@eecs.umich.edu } 14805855Sgblack@eecs.umich.edu // Fall through on purpose 14815855Sgblack@eecs.umich.edu case SegIntGateCheck: 14825853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 14835861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 14845853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 14855853Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14865853Sgblack@eecs.umich.edu } 14875674Sgblack@eecs.umich.edu break; 14885428Sgblack@eecs.umich.edu case SegSSCheck: 14895433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 14905433Sgblack@eecs.umich.edu if (!desc.p) { 14915857Sgblack@eecs.umich.edu fault = new StackFault(selector); 14928626Sgblack@eecs.umich.edu } else if (!(desc.s == 1 && desc.type.codeOrData == 0 && 14938626Sgblack@eecs.umich.edu desc.type.w) || 14945433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 14955433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 14965857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14975433Sgblack@eecs.umich.edu } 14988626Sgblack@eecs.umich.edu } else if (m5reg.submode != SixtyFourBitMode || 14998626Sgblack@eecs.umich.edu m5reg.cpl == 3) { 15008626Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15015433Sgblack@eecs.umich.edu } 15025428Sgblack@eecs.umich.edu break; 15035428Sgblack@eecs.umich.edu case SegIretCheck: 15045428Sgblack@eecs.umich.edu { 15055433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 15065433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 15075433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 15085433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 15095679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 15105857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15115679Sgblack@eecs.umich.edu } else if (!desc.p) { 15125857Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 15135679Sgblack@eecs.umich.edu } 15145428Sgblack@eecs.umich.edu break; 15155428Sgblack@eecs.umich.edu } 15165428Sgblack@eecs.umich.edu case SegIntCSCheck: 15175675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 15185675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 15195679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15205675Sgblack@eecs.umich.edu } 15215675Sgblack@eecs.umich.edu } else { 15228857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault("Interrupt CS " 15238857Sgblack@eecs.umich.edu "checks not implemented in legacy mode.\\n"); 15245675Sgblack@eecs.umich.edu } 15255428Sgblack@eecs.umich.edu break; 15265899Sgblack@eecs.umich.edu case SegTRCheck: 15275899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 15285899Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15295899Sgblack@eecs.umich.edu } 15305899Sgblack@eecs.umich.edu break; 15315900Sgblack@eecs.umich.edu case SegTSSCheck: 15325900Sgblack@eecs.umich.edu if (!desc.p) { 15335900Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 15345900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 15355900Sgblack@eecs.umich.edu (desc.type == 1 && 15365900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 15375935Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15385900Sgblack@eecs.umich.edu } 15395900Sgblack@eecs.umich.edu break; 15405936Sgblack@eecs.umich.edu case SegInGDTCheck: 15415936Sgblack@eecs.umich.edu if (selector.ti) { 15425936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15435936Sgblack@eecs.umich.edu } 15445936Sgblack@eecs.umich.edu break; 15455936Sgblack@eecs.umich.edu case SegLDTCheck: 15465936Sgblack@eecs.umich.edu if (!desc.p) { 15475936Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 15485936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 15495936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15505936Sgblack@eecs.umich.edu } 15515936Sgblack@eecs.umich.edu break; 15525428Sgblack@eecs.umich.edu default: 15538857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15548857Sgblack@eecs.umich.edu "Undefined segment check type.\\n"); 15555428Sgblack@eecs.umich.edu } 15565294Sgblack@eecs.umich.edu ''' 15575294Sgblack@eecs.umich.edu flag_code = ''' 15585294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 15599212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits & ~(ext & ZFBit); 15609212Snilay@cs.wisc.edu PredezfBit = PredezfBit & ~(ext & EZFBit); 15619010Snilay@cs.wisc.edu 15629010Snilay@cs.wisc.edu if (!selector.si && !selector.ti) { 15639212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits | (ext & ZFBit); 15649212Snilay@cs.wisc.edu PredezfBit = PredezfBit | (ext & EZFBit); 15659010Snilay@cs.wisc.edu } 15665294Sgblack@eecs.umich.edu ''' 15675294Sgblack@eecs.umich.edu 15685294Sgblack@eecs.umich.edu class Wrdh(RegOp): 15695294Sgblack@eecs.umich.edu code = ''' 15705678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 15715294Sgblack@eecs.umich.edu 15725678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 15735678Sgblack@eecs.umich.edu switch(desc.type) { 15745678Sgblack@eecs.umich.edu case LDT64: 15755678Sgblack@eecs.umich.edu case AvailableTSS64: 15765678Sgblack@eecs.umich.edu case BusyTSS64: 15775678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 15785678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 15795678Sgblack@eecs.umich.edu break; 15805678Sgblack@eecs.umich.edu case CallGate64: 15815678Sgblack@eecs.umich.edu case IntGate64: 15825678Sgblack@eecs.umich.edu case TrapGate64: 15835678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 15845678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 15855678Sgblack@eecs.umich.edu break; 15865678Sgblack@eecs.umich.edu default: 15878857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15888857Sgblack@eecs.umich.edu "Wrdh used with wrong descriptor type!\\n"); 15895678Sgblack@eecs.umich.edu } 15905678Sgblack@eecs.umich.edu DestReg = target; 15915294Sgblack@eecs.umich.edu ''' 15925294Sgblack@eecs.umich.edu 15935409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 15945409Sgblack@eecs.umich.edu code = ''' 15955409Sgblack@eecs.umich.edu TscOp = psrc1; 15965409Sgblack@eecs.umich.edu ''' 15975409Sgblack@eecs.umich.edu 15985409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 15995409Sgblack@eecs.umich.edu code = ''' 16005409Sgblack@eecs.umich.edu DestReg = TscOp; 16015409Sgblack@eecs.umich.edu ''' 16025409Sgblack@eecs.umich.edu 16035429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 16045429Sgblack@eecs.umich.edu code = ''' 16055429Sgblack@eecs.umich.edu DestReg = M5Reg; 16065429Sgblack@eecs.umich.edu ''' 16075429Sgblack@eecs.umich.edu 16085294Sgblack@eecs.umich.edu class Wrdl(RegOp): 16095294Sgblack@eecs.umich.edu code = ''' 16105294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 16115433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 16128857Sgblack@eecs.umich.edu // This while loop is so we can use break statements in the code 16138857Sgblack@eecs.umich.edu // below to skip the rest of this section without a bunch of 16148857Sgblack@eecs.umich.edu // nesting. 16158857Sgblack@eecs.umich.edu while (true) { 16168857Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 16178857Sgblack@eecs.umich.edu if (!desc.p) { 16188857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 16198857Sgblack@eecs.umich.edu "Segment not present.\\n"); 16208857Sgblack@eecs.umich.edu break; 16215901Sgblack@eecs.umich.edu } 16228857Sgblack@eecs.umich.edu SegAttr attr = 0; 16238857Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 16248857Sgblack@eecs.umich.edu attr.unusable = 0; 16258857Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 16268857Sgblack@eecs.umich.edu attr.longMode = desc.l; 16278857Sgblack@eecs.umich.edu attr.avl = desc.avl; 16288857Sgblack@eecs.umich.edu attr.granularity = desc.g; 16298857Sgblack@eecs.umich.edu attr.present = desc.p; 16308857Sgblack@eecs.umich.edu attr.system = desc.s; 16318857Sgblack@eecs.umich.edu attr.type = desc.type; 16328857Sgblack@eecs.umich.edu if (!desc.s) { 16338857Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 16348857Sgblack@eecs.umich.edu if (desc.type.e) { 16358857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 16368857Sgblack@eecs.umich.edu "Gate descriptor encountered.\\n"); 16378857Sgblack@eecs.umich.edu break; 16388857Sgblack@eecs.umich.edu } 16398857Sgblack@eecs.umich.edu attr.readable = 1; 16408857Sgblack@eecs.umich.edu attr.writable = 1; 16418857Sgblack@eecs.umich.edu attr.expandDown = 0; 16428857Sgblack@eecs.umich.edu } else { 16438857Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 16448857Sgblack@eecs.umich.edu attr.expandDown = 0; 16458857Sgblack@eecs.umich.edu attr.readable = desc.type.r; 16468857Sgblack@eecs.umich.edu attr.writable = 0; 16478857Sgblack@eecs.umich.edu } else { 16488857Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 16498857Sgblack@eecs.umich.edu attr.readable = 1; 16508857Sgblack@eecs.umich.edu attr.writable = desc.type.w; 16518857Sgblack@eecs.umich.edu } 16528857Sgblack@eecs.umich.edu } 16538857Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 16548857Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 16558857Sgblack@eecs.umich.edu if (desc.g) 16568857Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 16578857Sgblack@eecs.umich.edu SegBaseDest = base; 16588857Sgblack@eecs.umich.edu SegLimitDest = limit; 16598857Sgblack@eecs.umich.edu SegAttrDest = attr; 16605433Sgblack@eecs.umich.edu } else { 16618857Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 16628857Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 16638857Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 16645433Sgblack@eecs.umich.edu } 16658857Sgblack@eecs.umich.edu break; 16665294Sgblack@eecs.umich.edu } 16675290Sgblack@eecs.umich.edu ''' 16684519Sgblack@eecs.umich.edu}}; 1669