regop.isa revision 9211
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 124519Sgblack@eecs.umich.edu// 137087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 147087Snate@binkert.org// modification, are permitted provided that the following conditions are 157087Snate@binkert.org// met: redistributions of source code must retain the above copyright 167087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org// documentation and/or other materials provided with the distribution; 207087Snate@binkert.org// neither the name of the copyright holders nor the names of its 214519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227087Snate@binkert.org// this software without specific prior written permission. 234519Sgblack@eecs.umich.edu// 244519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354519Sgblack@eecs.umich.edu// 364519Sgblack@eecs.umich.edu// Authors: Gabe Black 374519Sgblack@eecs.umich.edu 384519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 394519Sgblack@eecs.umich.edu// 404519Sgblack@eecs.umich.edu// RegOp Microop templates 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 434519Sgblack@eecs.umich.edu 444519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 454519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 464519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474519Sgblack@eecs.umich.edu { 484519Sgblack@eecs.umich.edu Fault fault = NoFault; 494519Sgblack@eecs.umich.edu 504809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 514519Sgblack@eecs.umich.edu %(op_decl)s; 524519Sgblack@eecs.umich.edu %(op_rd)s; 534688Sgblack@eecs.umich.edu 547969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 557969Sgblack@eecs.umich.edu 564688Sgblack@eecs.umich.edu if(%(cond_check)s) 574688Sgblack@eecs.umich.edu { 584688Sgblack@eecs.umich.edu %(code)s; 594688Sgblack@eecs.umich.edu %(flag_code)s; 604688Sgblack@eecs.umich.edu } 614708Sgblack@eecs.umich.edu else 624708Sgblack@eecs.umich.edu { 634708Sgblack@eecs.umich.edu %(else_code)s; 644708Sgblack@eecs.umich.edu } 654519Sgblack@eecs.umich.edu 664519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 674519Sgblack@eecs.umich.edu if(fault == NoFault) 684519Sgblack@eecs.umich.edu { 694519Sgblack@eecs.umich.edu %(op_wb)s; 704519Sgblack@eecs.umich.edu } 714519Sgblack@eecs.umich.edu return fault; 724519Sgblack@eecs.umich.edu } 734519Sgblack@eecs.umich.edu}}; 744519Sgblack@eecs.umich.edu 754519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 764951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 774519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 784519Sgblack@eecs.umich.edu { 794519Sgblack@eecs.umich.edu Fault fault = NoFault; 804519Sgblack@eecs.umich.edu 814519Sgblack@eecs.umich.edu %(op_decl)s; 824519Sgblack@eecs.umich.edu %(op_rd)s; 834688Sgblack@eecs.umich.edu 847969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 857969Sgblack@eecs.umich.edu 864688Sgblack@eecs.umich.edu if(%(cond_check)s) 874688Sgblack@eecs.umich.edu { 884688Sgblack@eecs.umich.edu %(code)s; 894688Sgblack@eecs.umich.edu %(flag_code)s; 904688Sgblack@eecs.umich.edu } 914708Sgblack@eecs.umich.edu else 924708Sgblack@eecs.umich.edu { 934708Sgblack@eecs.umich.edu %(else_code)s; 944708Sgblack@eecs.umich.edu } 954519Sgblack@eecs.umich.edu 964519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 974519Sgblack@eecs.umich.edu if(fault == NoFault) 984519Sgblack@eecs.umich.edu { 994519Sgblack@eecs.umich.edu %(op_wb)s; 1004519Sgblack@eecs.umich.edu } 1014519Sgblack@eecs.umich.edu return fault; 1024519Sgblack@eecs.umich.edu } 1034519Sgblack@eecs.umich.edu}}; 1044519Sgblack@eecs.umich.edu 1054519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1064519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1074519Sgblack@eecs.umich.edu { 1084519Sgblack@eecs.umich.edu public: 1094519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1107620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1116345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1124712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1134519Sgblack@eecs.umich.edu 1144519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1154519Sgblack@eecs.umich.edu }; 1164519Sgblack@eecs.umich.edu}}; 1174519Sgblack@eecs.umich.edu 1184519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1194519Sgblack@eecs.umich.edu 1204951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu public: 1234951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1247620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1256646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1264712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1274519Sgblack@eecs.umich.edu 1284519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1294519Sgblack@eecs.umich.edu }; 1304519Sgblack@eecs.umich.edu}}; 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1334519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1347620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1356345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1364712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1377620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1384688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1394581Sgblack@eecs.umich.edu %(op_class)s) 1404519Sgblack@eecs.umich.edu { 1417626Sgblack@eecs.umich.edu %(constructor)s; 1427894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1434519Sgblack@eecs.umich.edu } 1444519Sgblack@eecs.umich.edu}}; 1454519Sgblack@eecs.umich.edu 1464519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1474951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1487620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1496646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1504712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1517620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1524688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 1534581Sgblack@eecs.umich.edu %(op_class)s) 1544519Sgblack@eecs.umich.edu { 1557626Sgblack@eecs.umich.edu %(constructor)s; 1567894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1574519Sgblack@eecs.umich.edu } 1584519Sgblack@eecs.umich.edu}}; 1594519Sgblack@eecs.umich.edu 1605075Sgblack@eecs.umich.eduoutput header {{ 1615075Sgblack@eecs.umich.edu void 1625075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1635075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 1645428Sgblack@eecs.umich.edu 1655428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 1665674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 1675899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 1685936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 1695428Sgblack@eecs.umich.edu }; 1705678Sgblack@eecs.umich.edu 1715678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 1725678Sgblack@eecs.umich.edu LDT64 = 2, 1735678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 1745678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 1755678Sgblack@eecs.umich.edu CallGate64 = 0xc, 1765678Sgblack@eecs.umich.edu IntGate64 = 0xe, 1775678Sgblack@eecs.umich.edu TrapGate64 = 0xf 1785678Sgblack@eecs.umich.edu }; 1795075Sgblack@eecs.umich.edu}}; 1805075Sgblack@eecs.umich.edu 1815075Sgblack@eecs.umich.eduoutput decoder {{ 1825075Sgblack@eecs.umich.edu void 1835075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1845075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 1855075Sgblack@eecs.umich.edu { 1865075Sgblack@eecs.umich.edu //Check for divide by zero. 1877719Sgblack@eecs.umich.edu assert(divisor != 0); 1885075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 1895075Sgblack@eecs.umich.edu if (divisor <= dividend) { 1905075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 1915075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 1925075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 1935075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 1945075Sgblack@eecs.umich.edu divisor <<= shift; 1955075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 1965075Sgblack@eecs.umich.edu //now larger than the dividend. 1975075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 1985075Sgblack@eecs.umich.edu quotientBit <<= shift; 1995075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2005075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2015075Sgblack@eecs.umich.edu //part of one or two bit division. 2025075Sgblack@eecs.umich.edu if (divisor > dividend) { 2035075Sgblack@eecs.umich.edu quotientBit >>= 1; 2045075Sgblack@eecs.umich.edu divisor >>= 1; 2055075Sgblack@eecs.umich.edu } 2065075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2075075Sgblack@eecs.umich.edu quotient += quotientBit; 2085075Sgblack@eecs.umich.edu remainder -= divisor; 2095075Sgblack@eecs.umich.edu } 2105075Sgblack@eecs.umich.edu } 2115075Sgblack@eecs.umich.edu}}; 2125075Sgblack@eecs.umich.edu 2134519Sgblack@eecs.umich.edulet {{ 2145040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2155040Sgblack@eecs.umich.edu # them will always work. 2165040Sgblack@eecs.umich.edu header_output = "" 2175040Sgblack@eecs.umich.edu decoder_output = "" 2185040Sgblack@eecs.umich.edu exec_output = "" 2195040Sgblack@eecs.umich.edu 2205040Sgblack@eecs.umich.edu immTemplates = ( 2215040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2225040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2235040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2245040Sgblack@eecs.umich.edu 2255040Sgblack@eecs.umich.edu regTemplates = ( 2265040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2275040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2285040Sgblack@eecs.umich.edu MicroRegOpExecute) 2295040Sgblack@eecs.umich.edu 2305040Sgblack@eecs.umich.edu class RegOpMeta(type): 2317967Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, code, big_code, \ 2327967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, cond_control_flag_init): 2335040Sgblack@eecs.umich.edu 2345040Sgblack@eecs.umich.edu # Globals to stick the output in 2355040Sgblack@eecs.umich.edu global header_output 2365040Sgblack@eecs.umich.edu global decoder_output 2375040Sgblack@eecs.umich.edu global exec_output 2385040Sgblack@eecs.umich.edu 2395040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2407894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 2417894SBrad.Beckmann@amd.com cond_control_flag_init)) 2427967Sgblack@eecs.umich.edu allBigCode = "|".join((big_code, flag_code, cond_check, else_code, 2437967Sgblack@eecs.umich.edu cond_control_flag_init)) 2445040Sgblack@eecs.umich.edu 2455040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2465040Sgblack@eecs.umich.edu # of this code. 2478588Sgblack@eecs.umich.edu matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?") 2487967Sgblack@eecs.umich.edu match = matcher.search(allCode + allBigCode) 2495062Sgblack@eecs.umich.edu if match: 2505062Sgblack@eecs.umich.edu typeQual = "" 2515062Sgblack@eecs.umich.edu if match.group("typeQual"): 2525062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 2535062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 2545040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2555062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 2567967Sgblack@eecs.umich.edu matcher.sub(src2_name, big_code), 2575062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 2585062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 2597894SBrad.Beckmann@amd.com matcher.sub(src2_name, else_code), 2607894SBrad.Beckmann@amd.com matcher.sub(src2_name, cond_control_flag_init)) 2616647Sgblack@eecs.umich.edu imm_name = "%simm8" % match.group("prefix") 2625040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 2636647Sgblack@eecs.umich.edu matcher.sub(imm_name, code), 2647967Sgblack@eecs.umich.edu matcher.sub(imm_name, big_code), 2656647Sgblack@eecs.umich.edu matcher.sub(imm_name, flag_code), 2666647Sgblack@eecs.umich.edu matcher.sub(imm_name, cond_check), 2677894SBrad.Beckmann@amd.com matcher.sub(imm_name, else_code), 2687894SBrad.Beckmann@amd.com matcher.sub(imm_name, cond_control_flag_init)) 2695040Sgblack@eecs.umich.edu return 2705040Sgblack@eecs.umich.edu 2715040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 2725040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 2735239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 2745040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2757967Sgblack@eecs.umich.edu code, big_code, "", "true", else_code, "") 2765040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 2775040Sgblack@eecs.umich.edu 2785040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 2795040Sgblack@eecs.umich.edu # compute it. 2807967Sgblack@eecs.umich.edu for (big, all) in ((False, allCode), (True, allBigCode)): 2817967Sgblack@eecs.umich.edu prefix = "" 2827967Sgblack@eecs.umich.edu for (rex, decl) in ( 2837967Sgblack@eecs.umich.edu ("(?<!\w)psrc1(?!\w)", 2847967Sgblack@eecs.umich.edu "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"), 2857967Sgblack@eecs.umich.edu ("(?<!\w)psrc2(?!\w)", 2867967Sgblack@eecs.umich.edu "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"), 2877967Sgblack@eecs.umich.edu ("(?<!\w)spsrc1(?!\w)", 2887967Sgblack@eecs.umich.edu "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"), 2897967Sgblack@eecs.umich.edu ("(?<!\w)spsrc2(?!\w)", 2907967Sgblack@eecs.umich.edu "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"), 2917967Sgblack@eecs.umich.edu ("(?<!\w)simm8(?!\w)", 2927967Sgblack@eecs.umich.edu "int8_t simm8 = imm8;")): 2937967Sgblack@eecs.umich.edu matcher = re.compile(rex) 2947967Sgblack@eecs.umich.edu if matcher.search(all): 2957967Sgblack@eecs.umich.edu prefix += decl + "\n" 2967967Sgblack@eecs.umich.edu if big: 2977967Sgblack@eecs.umich.edu if big_code != "": 2987967Sgblack@eecs.umich.edu big_code = prefix + big_code 2997967Sgblack@eecs.umich.edu else: 3007967Sgblack@eecs.umich.edu code = prefix + code 3015040Sgblack@eecs.umich.edu 3025040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3035040Sgblack@eecs.umich.edu 3045040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3055040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3065040Sgblack@eecs.umich.edu templates = regTemplates 3076647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3085040Sgblack@eecs.umich.edu if matcher.search(allCode): 3095040Sgblack@eecs.umich.edu base += "Imm" 3105040Sgblack@eecs.umich.edu templates = immTemplates 3115040Sgblack@eecs.umich.edu 3125040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3137967Sgblack@eecs.umich.edu iops = [InstObjParams(name, Name + suffix, base, 3145040Sgblack@eecs.umich.edu {"code" : code, 3155040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3165040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3177894SBrad.Beckmann@amd.com "else_code" : else_code, 3187967Sgblack@eecs.umich.edu "cond_control_flag_init" : cond_control_flag_init})] 3197967Sgblack@eecs.umich.edu if big_code != "": 3207967Sgblack@eecs.umich.edu iops += [InstObjParams(name, Name + suffix + "Big", base, 3217967Sgblack@eecs.umich.edu {"code" : big_code, 3227967Sgblack@eecs.umich.edu "flag_code" : flag_code, 3237967Sgblack@eecs.umich.edu "cond_check" : cond_check, 3247967Sgblack@eecs.umich.edu "else_code" : else_code, 3257967Sgblack@eecs.umich.edu "cond_control_flag_init" : 3267967Sgblack@eecs.umich.edu cond_control_flag_init})] 3275040Sgblack@eecs.umich.edu 3285040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3297967Sgblack@eecs.umich.edu for iop in iops: 3307967Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3317967Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3327967Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3335040Sgblack@eecs.umich.edu 3345040Sgblack@eecs.umich.edu 3355040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3364688Sgblack@eecs.umich.edu abstract = False 3375040Sgblack@eecs.umich.edu name = Name.lower() 3384688Sgblack@eecs.umich.edu if "abstract" in dict: 3394688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3404688Sgblack@eecs.umich.edu del dict['abstract'] 3414688Sgblack@eecs.umich.edu 3425040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3434688Sgblack@eecs.umich.edu if not abstract: 3445040Sgblack@eecs.umich.edu cls.className = Name 3455040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3465040Sgblack@eecs.umich.edu code = cls.code 3477967Sgblack@eecs.umich.edu big_code = cls.big_code 3485040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3495040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3505040Sgblack@eecs.umich.edu else_code = cls.else_code 3517894SBrad.Beckmann@amd.com cond_control_flag_init = cls.cond_control_flag_init 3525040Sgblack@eecs.umich.edu 3535040Sgblack@eecs.umich.edu # Set up the C++ classes 3547967Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", code, big_code, 3557967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, 3567967Sgblack@eecs.umich.edu cond_control_flag_init) 3575040Sgblack@eecs.umich.edu 3585040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3595040Sgblack@eecs.umich.edu global microopClasses 3605040Sgblack@eecs.umich.edu microopClasses[name] = cls 3615040Sgblack@eecs.umich.edu 3627894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 3637894SBrad.Beckmann@amd.com cond_control_flag_init)) 3645040Sgblack@eecs.umich.edu 3655040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3665040Sgblack@eecs.umich.edu # of this code. 3678588Sgblack@eecs.umich.edu matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?") 3685040Sgblack@eecs.umich.edu if matcher.search(allCode): 3695040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3704688Sgblack@eecs.umich.edu return cls 3714688Sgblack@eecs.umich.edu 3725040Sgblack@eecs.umich.edu 3735040Sgblack@eecs.umich.edu class RegOp(X86Microop): 3745040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 3755040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 3764688Sgblack@eecs.umich.edu abstract = True 3774688Sgblack@eecs.umich.edu 3785040Sgblack@eecs.umich.edu # Default template parameter values 3797967Sgblack@eecs.umich.edu big_code = "" 3805040Sgblack@eecs.umich.edu flag_code = "" 3815040Sgblack@eecs.umich.edu cond_check = "true" 3825040Sgblack@eecs.umich.edu else_code = ";" 3837894SBrad.Beckmann@amd.com cond_control_flag_init = "" 3845040Sgblack@eecs.umich.edu 3855040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 3864519Sgblack@eecs.umich.edu self.dest = dest 3874519Sgblack@eecs.umich.edu self.src1 = src1 3885040Sgblack@eecs.umich.edu self.op2 = op2 3894688Sgblack@eecs.umich.edu self.flags = flags 3904701Sgblack@eecs.umich.edu self.dataSize = dataSize 3914688Sgblack@eecs.umich.edu if flags is None: 3924688Sgblack@eecs.umich.edu self.ext = 0 3934688Sgblack@eecs.umich.edu else: 3944688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 3954688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 3964688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 3974688Sgblack@eecs.umich.edu self.className += "Flags" 3984519Sgblack@eecs.umich.edu 3997620Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 4007967Sgblack@eecs.umich.edu if self.big_code != "": 4017967Sgblack@eecs.umich.edu className = self.className 4027967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4037967Sgblack@eecs.umich.edu className += "Imm" 4047967Sgblack@eecs.umich.edu allocString = ''' 4057967Sgblack@eecs.umich.edu (%(dataSize)s >= 4) ? 4067967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)sBig(machInst, 4077967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4087967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) : 4097967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)s(machInst, 4107967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4117967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) 4127967Sgblack@eecs.umich.edu ''' 4137967Sgblack@eecs.umich.edu allocator = allocString % { 4147967Sgblack@eecs.umich.edu "class_name" : className, 4157967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4167967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4177967Sgblack@eecs.umich.edu "dest" : self.dest, 4187967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4197967Sgblack@eecs.umich.edu "ext" : self.ext} 4207967Sgblack@eecs.umich.edu return allocator 4217967Sgblack@eecs.umich.edu else: 4227967Sgblack@eecs.umich.edu className = self.className 4237967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4247967Sgblack@eecs.umich.edu className += "Imm" 4257967Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 4267967Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4277967Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4287967Sgblack@eecs.umich.edu "class_name" : className, 4297967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4307967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4317967Sgblack@eecs.umich.edu "dest" : self.dest, 4327967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4337967Sgblack@eecs.umich.edu "ext" : self.ext} 4347967Sgblack@eecs.umich.edu return allocator 4354519Sgblack@eecs.umich.edu 4365040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4374688Sgblack@eecs.umich.edu abstract = True 4385040Sgblack@eecs.umich.edu flag_code = ''' 4395040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4405115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4419211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 4429211Snilay@cs.wisc.edu ext & ~mask, result, psrc1, op2); 4439010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 4449211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 4459010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 4469010Snilay@cs.wisc.edu 4475040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4489010Snilay@cs.wisc.edu cfofBits = cfofBits & ~((CFBit | OFBit) & ext); 4499010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ECFBit & ext); 4505040Sgblack@eecs.umich.edu ''' 4514519Sgblack@eecs.umich.edu 4525040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4535040Sgblack@eecs.umich.edu abstract = True 4549010Snilay@cs.wisc.edu flag_code = ''' 4559211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit | 4569211Snilay@cs.wisc.edu ecfBit | ezfBit, ext, result, psrc1, op2); 4579010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 4589010Snilay@cs.wisc.edu ecfBit = newFlags & ECFBit; 4599010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 4609211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 4619010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 4629010Snilay@cs.wisc.edu ''' 4634519Sgblack@eecs.umich.edu 4645040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4655040Sgblack@eecs.umich.edu abstract = True 4669010Snilay@cs.wisc.edu flag_code = ''' 4679211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit | 4689211Snilay@cs.wisc.edu ecfBit | ezfBit, ext, result, psrc1, 4699211Snilay@cs.wisc.edu ~op2, true); 4709010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 4719010Snilay@cs.wisc.edu ecfBit = newFlags & ECFBit; 4729010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 4739211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 4749010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 4759010Snilay@cs.wisc.edu ''' 4764519Sgblack@eecs.umich.edu 4775040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4785040Sgblack@eecs.umich.edu abstract = True 4799211Snilay@cs.wisc.edu cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | ecfBit | \ 4809211Snilay@cs.wisc.edu ezfBit, ext)" 4817894SBrad.Beckmann@amd.com cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];" 4824519Sgblack@eecs.umich.edu 4835063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4845063Sgblack@eecs.umich.edu abstract = True 4855063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4865063Sgblack@eecs.umich.edu if not src1: 4875063Sgblack@eecs.umich.edu src1 = dest 4886345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4896345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4905063Sgblack@eecs.umich.edu 4915063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4925063Sgblack@eecs.umich.edu abstract = True 4935063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4946345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4956345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 4965063Sgblack@eecs.umich.edu 4975040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4987969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' 4997969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' 5004595Sgblack@eecs.umich.edu 5015040Sgblack@eecs.umich.edu class Or(LogicRegOp): 5027969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' 5037969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' 5044595Sgblack@eecs.umich.edu 5055040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 5065040Sgblack@eecs.umich.edu code = ''' 5079010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5087969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); 5095040Sgblack@eecs.umich.edu ''' 5107967Sgblack@eecs.umich.edu big_code = ''' 5119010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5127969Sgblack@eecs.umich.edu DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); 5137967Sgblack@eecs.umich.edu ''' 5145040Sgblack@eecs.umich.edu 5155040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 5165040Sgblack@eecs.umich.edu code = ''' 5179010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5187969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); 5195040Sgblack@eecs.umich.edu ''' 5207967Sgblack@eecs.umich.edu big_code = ''' 5219010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5227969Sgblack@eecs.umich.edu DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); 5237967Sgblack@eecs.umich.edu ''' 5245040Sgblack@eecs.umich.edu 5255040Sgblack@eecs.umich.edu class And(LogicRegOp): 5267969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' 5277969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' 5285040Sgblack@eecs.umich.edu 5295040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5307969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' 5317969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' 5325040Sgblack@eecs.umich.edu 5335040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5347969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' 5357969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)' 5365040Sgblack@eecs.umich.edu 5375063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5385040Sgblack@eecs.umich.edu code = ''' 5395063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5405063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5416742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5426430Sgblack@eecs.umich.edu uint64_t hiResult; 5436430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5446430Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5456461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5466430Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5476430Sgblack@eecs.umich.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5486430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 5496430Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5506462Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 5516430Sgblack@eecs.umich.edu hiResult -= op2; 5526462Sgblack@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 5536430Sgblack@eecs.umich.edu hiResult -= psrc1; 5546430Sgblack@eecs.umich.edu ProdHi = hiResult; 5555040Sgblack@eecs.umich.edu ''' 5566463Sgblack@eecs.umich.edu flag_code = ''' 5576463Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 5586463Sgblack@eecs.umich.edu bits(ProdLow, dataSize * 8 - 1)) { 5599010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & (CFBit | OFBit)); 5609010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 5616463Sgblack@eecs.umich.edu } else { 5629010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 5639010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 5646463Sgblack@eecs.umich.edu } 5656463Sgblack@eecs.umich.edu ''' 5665040Sgblack@eecs.umich.edu 5675063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5685040Sgblack@eecs.umich.edu code = ''' 5695063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5704809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5716742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5726430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5735063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5746461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5755063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5765063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5776430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) / shifter) + 5785063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5795040Sgblack@eecs.umich.edu ''' 5806463Sgblack@eecs.umich.edu flag_code = ''' 5816463Sgblack@eecs.umich.edu if (ProdHi) { 5829010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & (CFBit | OFBit)); 5839010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 5846463Sgblack@eecs.umich.edu } else { 5859010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 5869010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 5876463Sgblack@eecs.umich.edu } 5886463Sgblack@eecs.umich.edu ''' 5895040Sgblack@eecs.umich.edu 5905063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5915063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5927967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdLow & mask(dataSize * 8);' 5935040Sgblack@eecs.umich.edu 5945063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5955063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5965063Sgblack@eecs.umich.edu if not src1: 5975063Sgblack@eecs.umich.edu src1 = dest 5986345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 5996345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 6005063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 6017967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdHi & mask(dataSize * 8);' 6025062Sgblack@eecs.umich.edu 6035075Sgblack@eecs.umich.edu # One or two bit divide 6045075Sgblack@eecs.umich.edu class Div1(WrRegOp): 6055040Sgblack@eecs.umich.edu code = ''' 6065075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 6075075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 6085075Sgblack@eecs.umich.edu uint64_t quotient = 0; 6095075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 6105075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 6115075Sgblack@eecs.umich.edu //a source. 6125075Sgblack@eecs.umich.edu uint64_t divisor = op2; 6135075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 6145075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 6155075Sgblack@eecs.umich.edu //Do the division. 6167719Sgblack@eecs.umich.edu if (divisor == 0) { 6177719Sgblack@eecs.umich.edu fault = new DivideByZero; 6187719Sgblack@eecs.umich.edu } else { 6197719Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6207719Sgblack@eecs.umich.edu //Record the final results. 6217719Sgblack@eecs.umich.edu Remainder = remainder; 6227719Sgblack@eecs.umich.edu Quotient = quotient; 6237719Sgblack@eecs.umich.edu Divisor = divisor; 6247719Sgblack@eecs.umich.edu } 6255040Sgblack@eecs.umich.edu ''' 6264823Sgblack@eecs.umich.edu 6275075Sgblack@eecs.umich.edu # Step divide 6285075Sgblack@eecs.umich.edu class Div2(RegOp): 6297967Sgblack@eecs.umich.edu divCode = ''' 6305075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 6315075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 6325075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 6335075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 6345075Sgblack@eecs.umich.edu int remaining = op2; 6355075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 6365075Sgblack@eecs.umich.edu //little. 6377719Sgblack@eecs.umich.edu if (divisor == 0) { 6387719Sgblack@eecs.umich.edu fault = new DivideByZero; 6397719Sgblack@eecs.umich.edu } else if (remaining) { 6407070Sgblack@eecs.umich.edu if (divisor & (ULL(1) << 63)) { 6417070Sgblack@eecs.umich.edu while (remaining && !(dividend & (ULL(1) << 63))) { 6427070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6437070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6447070Sgblack@eecs.umich.edu quotient <<= 1; 6457070Sgblack@eecs.umich.edu remaining--; 6467070Sgblack@eecs.umich.edu } 6477070Sgblack@eecs.umich.edu if (dividend & (ULL(1) << 63)) { 6487080Sgblack@eecs.umich.edu bool highBit = false; 6497070Sgblack@eecs.umich.edu if (dividend < divisor && remaining) { 6507080Sgblack@eecs.umich.edu highBit = true; 6517070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6527070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6537070Sgblack@eecs.umich.edu quotient <<= 1; 6547070Sgblack@eecs.umich.edu remaining--; 6557070Sgblack@eecs.umich.edu } 6567080Sgblack@eecs.umich.edu if (highBit || divisor <= dividend) { 6577080Sgblack@eecs.umich.edu quotient++; 6587080Sgblack@eecs.umich.edu dividend -= divisor; 6597080Sgblack@eecs.umich.edu } 6607070Sgblack@eecs.umich.edu } 6617070Sgblack@eecs.umich.edu remainder = dividend; 6627070Sgblack@eecs.umich.edu } else { 6637070Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 6647070Sgblack@eecs.umich.edu while (dividend < divisor && remaining) { 6657070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6667070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6677070Sgblack@eecs.umich.edu quotient <<= 1; 6687070Sgblack@eecs.umich.edu remaining--; 6697070Sgblack@eecs.umich.edu } 6707070Sgblack@eecs.umich.edu remainder = dividend; 6717070Sgblack@eecs.umich.edu //Do the division. 6727070Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6735075Sgblack@eecs.umich.edu } 6745075Sgblack@eecs.umich.edu } 6755075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 6767967Sgblack@eecs.umich.edu %s 6775075Sgblack@eecs.umich.edu //Record the final results 6785075Sgblack@eecs.umich.edu Remainder = remainder; 6795075Sgblack@eecs.umich.edu Quotient = quotient; 6805075Sgblack@eecs.umich.edu ''' 6817967Sgblack@eecs.umich.edu code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" 6827967Sgblack@eecs.umich.edu big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" 6835075Sgblack@eecs.umich.edu flag_code = ''' 6847480Sgblack@eecs.umich.edu if (remaining == 0) 6859010Snilay@cs.wisc.edu ezfBit = ezfBit | (ext & EZFBit); 6865075Sgblack@eecs.umich.edu else 6879010Snilay@cs.wisc.edu ezfBit = ezfBit & ~(ext & EZFBit); 6885075Sgblack@eecs.umich.edu ''' 6894732Sgblack@eecs.umich.edu 6905075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6915075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6927967Sgblack@eecs.umich.edu big_code = 'DestReg = Quotient & mask(dataSize * 8);' 6935075Sgblack@eecs.umich.edu 6945075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6955075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6967967Sgblack@eecs.umich.edu big_code = 'DestReg = Remainder & mask(dataSize * 8);' 6975040Sgblack@eecs.umich.edu 6985040Sgblack@eecs.umich.edu class Mov(CondRegOp): 6995040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 7006482Sgblack@eecs.umich.edu else_code = 'DestReg = DestReg;' 7015040Sgblack@eecs.umich.edu 7024732Sgblack@eecs.umich.edu # Shift instructions 7035040Sgblack@eecs.umich.edu 7045076Sgblack@eecs.umich.edu class Sll(RegOp): 7055040Sgblack@eecs.umich.edu code = ''' 7064756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7074823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 7085040Sgblack@eecs.umich.edu ''' 7097967Sgblack@eecs.umich.edu big_code = ''' 7107967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7117967Sgblack@eecs.umich.edu DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); 7127967Sgblack@eecs.umich.edu ''' 7135076Sgblack@eecs.umich.edu flag_code = ''' 7145076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7155076Sgblack@eecs.umich.edu if (shiftAmt) { 7165076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7175076Sgblack@eecs.umich.edu //worry about setting them. 7189010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 7199010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 7209010Snilay@cs.wisc.edu 7215076Sgblack@eecs.umich.edu int CFBits = 0; 7225076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 7236441Sgblack@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 7246441Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 7255076Sgblack@eecs.umich.edu CFBits = 1; 7266441Sgblack@eecs.umich.edu } 7279010Snilay@cs.wisc.edu 7285076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7299010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 7309010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 7319010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 7329010Snilay@cs.wisc.edu } 7339010Snilay@cs.wisc.edu 7345076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7355076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 7369010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 7379010Snilay@cs.wisc.edu 7385076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7399211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 7409010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 7419010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 7429211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 7439010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 7445076Sgblack@eecs.umich.edu } 7455076Sgblack@eecs.umich.edu ''' 7465040Sgblack@eecs.umich.edu 7475076Sgblack@eecs.umich.edu class Srl(RegOp): 7487967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 7497967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to mask them out 7507967Sgblack@eecs.umich.edu # to be sure they're zero. 7515040Sgblack@eecs.umich.edu code = ''' 7524756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7534732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7544823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 7555040Sgblack@eecs.umich.edu ''' 7567967Sgblack@eecs.umich.edu big_code = ''' 7577967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7587967Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7597967Sgblack@eecs.umich.edu DestReg = (psrc1 >> shiftAmt) & logicalMask; 7607967Sgblack@eecs.umich.edu ''' 7615076Sgblack@eecs.umich.edu flag_code = ''' 7625076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7635076Sgblack@eecs.umich.edu if (shiftAmt) { 7645076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7655076Sgblack@eecs.umich.edu //worry about setting them. 7669010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 7679010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 7689010Snilay@cs.wisc.edu 7695076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7706442Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7716442Sgblack@eecs.umich.edu shiftAmt <= dataSize * 8 && 7726442Sgblack@eecs.umich.edu bits(SrcReg1, shiftAmt - 1)) { 7739010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 7749010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 7756442Sgblack@eecs.umich.edu } 7769010Snilay@cs.wisc.edu 7775076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7785076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 7799010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 7809010Snilay@cs.wisc.edu 7815076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7829211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 7839010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 7849010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 7859211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 7869010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 7875076Sgblack@eecs.umich.edu } 7885076Sgblack@eecs.umich.edu ''' 7895040Sgblack@eecs.umich.edu 7905076Sgblack@eecs.umich.edu class Sra(RegOp): 7917967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 7927967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to sign extend 7937967Sgblack@eecs.umich.edu # them manually to be sure. 7945040Sgblack@eecs.umich.edu code = ''' 7954756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7966443Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 7975032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 7984823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 7995040Sgblack@eecs.umich.edu ''' 8007967Sgblack@eecs.umich.edu big_code = ''' 8017967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8027967Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 8037967Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 8047967Sgblack@eecs.umich.edu DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); 8057967Sgblack@eecs.umich.edu ''' 8065076Sgblack@eecs.umich.edu flag_code = ''' 8075076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8085076Sgblack@eecs.umich.edu if (shiftAmt) { 8095076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8105076Sgblack@eecs.umich.edu //worry about setting them. 8119010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 8129010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 8139010Snilay@cs.wisc.edu 8145076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8156444Sgblack@eecs.umich.edu uint8_t effectiveShift = 8166444Sgblack@eecs.umich.edu (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 8176444Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8186444Sgblack@eecs.umich.edu bits(SrcReg1, effectiveShift - 1)) { 8199010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 8209010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 8216444Sgblack@eecs.umich.edu } 8229010Snilay@cs.wisc.edu 8235076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8249211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 8259010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 8269010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 8279211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 8289010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 8295076Sgblack@eecs.umich.edu } 8305076Sgblack@eecs.umich.edu ''' 8315040Sgblack@eecs.umich.edu 8325076Sgblack@eecs.umich.edu class Ror(RegOp): 8335040Sgblack@eecs.umich.edu code = ''' 8344732Sgblack@eecs.umich.edu uint8_t shiftAmt = 8354756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8366449Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 8377967Sgblack@eecs.umich.edu if (realShiftAmt) { 8386449Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 8396449Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 8404732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8417967Sgblack@eecs.umich.edu } else 8426447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8435040Sgblack@eecs.umich.edu ''' 8445076Sgblack@eecs.umich.edu flag_code = ''' 8455076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8465076Sgblack@eecs.umich.edu if (shiftAmt) { 8475076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8485076Sgblack@eecs.umich.edu //worry about setting them. 8499010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 8509010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 8519010Snilay@cs.wisc.edu 8525076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 8535076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8545076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 8555076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8569010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && msb) { 8579010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 8589010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 8599010Snilay@cs.wisc.edu } 8609010Snilay@cs.wisc.edu 8615076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8625076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 8639010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 8649010Snilay@cs.wisc.edu 8655076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8669211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 8679010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 8689010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 8699211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 8709010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 8715076Sgblack@eecs.umich.edu } 8725076Sgblack@eecs.umich.edu ''' 8735040Sgblack@eecs.umich.edu 8745076Sgblack@eecs.umich.edu class Rcr(RegOp): 8755040Sgblack@eecs.umich.edu code = ''' 8764733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8774756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8786454Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 8797967Sgblack@eecs.umich.edu if (realShiftAmt) { 8809010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 8816454Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 8826454Sgblack@eecs.umich.edu if (realShiftAmt > 1) 8836454Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 8846454Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 8854733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8867967Sgblack@eecs.umich.edu } else 8876447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8885040Sgblack@eecs.umich.edu ''' 8895076Sgblack@eecs.umich.edu flag_code = ''' 8905076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8915076Sgblack@eecs.umich.edu if (shiftAmt) { 8929010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 8935076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8945076Sgblack@eecs.umich.edu //worry about setting them. 8959010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 8969010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 8979010Snilay@cs.wisc.edu 8985076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8996453Sgblack@eecs.umich.edu if ((ext & OFBit) && (origCFBit ^ 9006453Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) { 9019010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 9026453Sgblack@eecs.umich.edu } 9035076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9046454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 9056454Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : 9066454Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) { 9079010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 9089010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 9096454Sgblack@eecs.umich.edu } 9109010Snilay@cs.wisc.edu 9115076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9129211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 9139010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 9149010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 9159211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 9169010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 9175076Sgblack@eecs.umich.edu } 9185076Sgblack@eecs.umich.edu ''' 9195040Sgblack@eecs.umich.edu 9205076Sgblack@eecs.umich.edu class Rol(RegOp): 9215040Sgblack@eecs.umich.edu code = ''' 9224732Sgblack@eecs.umich.edu uint8_t shiftAmt = 9234756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9246446Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 9257967Sgblack@eecs.umich.edu if (realShiftAmt) { 9266446Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 9274732Sgblack@eecs.umich.edu uint64_t bottom = 9286446Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 9294732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9307967Sgblack@eecs.umich.edu } else 9316447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9325040Sgblack@eecs.umich.edu ''' 9335076Sgblack@eecs.umich.edu flag_code = ''' 9345076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9355076Sgblack@eecs.umich.edu if (shiftAmt) { 9365076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9375076Sgblack@eecs.umich.edu //worry about setting them. 9389010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 9399010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 9409010Snilay@cs.wisc.edu 9415076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 9425076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 9435076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 9445076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9459010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && lsb) { 9469010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 9479010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 9489010Snilay@cs.wisc.edu } 9499010Snilay@cs.wisc.edu 9505076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9515076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 9529010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 9539010Snilay@cs.wisc.edu 9545076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9559211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 9569010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 9579010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 9589211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 9599010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 9605076Sgblack@eecs.umich.edu } 9615076Sgblack@eecs.umich.edu ''' 9625040Sgblack@eecs.umich.edu 9635076Sgblack@eecs.umich.edu class Rcl(RegOp): 9645040Sgblack@eecs.umich.edu code = ''' 9654733Sgblack@eecs.umich.edu uint8_t shiftAmt = 9664756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9676456Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 9687967Sgblack@eecs.umich.edu if (realShiftAmt) { 9699010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 9706456Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 9716456Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (realShiftAmt - 1); 9724733Sgblack@eecs.umich.edu if(shiftAmt > 1) 9734733Sgblack@eecs.umich.edu bottom |= 9744823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 9756456Sgblack@eecs.umich.edu dataSize * 8 - realShiftAmt + 1); 9764733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9777967Sgblack@eecs.umich.edu } else 9786447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9795040Sgblack@eecs.umich.edu ''' 9805076Sgblack@eecs.umich.edu flag_code = ''' 9815076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9825076Sgblack@eecs.umich.edu if (shiftAmt) { 9839010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 9845076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9855076Sgblack@eecs.umich.edu //worry about setting them. 9869010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 9879010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 9889010Snilay@cs.wisc.edu 9895076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 9906456Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 9915076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9926456Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 9939010Snilay@cs.wisc.edu (realShiftAmt == 0) ? origCFBit : CFBits) { 9949010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 9959010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 9969010Snilay@cs.wisc.edu } 9979010Snilay@cs.wisc.edu 9985076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9995076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 10009010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 10019010Snilay@cs.wisc.edu 10025076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10039211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 10049010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 10059010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 10069211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 10079010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 10085076Sgblack@eecs.umich.edu } 10095076Sgblack@eecs.umich.edu ''' 10104732Sgblack@eecs.umich.edu 10116479Sgblack@eecs.umich.edu class Sld(RegOp): 10127967Sgblack@eecs.umich.edu sldCode = ''' 10136479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 10146479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 10157967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 10166479Sgblack@eecs.umich.edu uint64_t result; 10176479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 10186479Sgblack@eecs.umich.edu result = psrc1; 10196479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 10206479Sgblack@eecs.umich.edu result = (psrc1 << realShiftAmt) | 10216479Sgblack@eecs.umich.edu (DoubleBits >> (dataBits - realShiftAmt)); 10226479Sgblack@eecs.umich.edu } else { 10236479Sgblack@eecs.umich.edu result = (DoubleBits << (realShiftAmt - dataBits)) | 10246479Sgblack@eecs.umich.edu (psrc1 >> (2 * dataBits - realShiftAmt)); 10256479Sgblack@eecs.umich.edu } 10267967Sgblack@eecs.umich.edu %s 10276479Sgblack@eecs.umich.edu ''' 10287967Sgblack@eecs.umich.edu code = sldCode % "DestReg = merge(DestReg, result, dataSize);" 10297967Sgblack@eecs.umich.edu big_code = sldCode % "DestReg = result & mask(dataSize * 8);" 10306479Sgblack@eecs.umich.edu flag_code = ''' 10316479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10326479Sgblack@eecs.umich.edu if (shiftAmt) { 10336479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10346479Sgblack@eecs.umich.edu //worry about setting them. 10359010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 10369010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 10376479Sgblack@eecs.umich.edu int CFBits = 0; 10389010Snilay@cs.wisc.edu 10396479Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 10406479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 10416479Sgblack@eecs.umich.edu bits(DoubleBits, 0)) || 10426479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 10436479Sgblack@eecs.umich.edu bits(SrcReg1, dataBits - realShiftAmt)) || 10446479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 10456479Sgblack@eecs.umich.edu bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 10466479Sgblack@eecs.umich.edu CFBits = 1; 10476479Sgblack@eecs.umich.edu } 10489010Snilay@cs.wisc.edu 10496479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10509010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 10519010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 10529010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 10539010Snilay@cs.wisc.edu } 10549010Snilay@cs.wisc.edu 10556479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10566479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 10576479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 10589010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 10599010Snilay@cs.wisc.edu 10606479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10619211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 10629010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 10639010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 10649211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 10659010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 10666479Sgblack@eecs.umich.edu } 10676479Sgblack@eecs.umich.edu ''' 10686479Sgblack@eecs.umich.edu 10696479Sgblack@eecs.umich.edu class Srd(RegOp): 10707967Sgblack@eecs.umich.edu srdCode = ''' 10716479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 10726479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 10737967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 10746479Sgblack@eecs.umich.edu uint64_t result; 10756479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 10766479Sgblack@eecs.umich.edu result = psrc1; 10776479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 10786479Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right 10796479Sgblack@eecs.umich.edu // shift is not defined in the C/C++ standard, we have to 10806479Sgblack@eecs.umich.edu // mask them out to be sure they're zero. 10816479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataBits - realShiftAmt); 10826479Sgblack@eecs.umich.edu result = ((psrc1 >> realShiftAmt) & logicalMask) | 10836479Sgblack@eecs.umich.edu (DoubleBits << (dataBits - realShiftAmt)); 10846479Sgblack@eecs.umich.edu } else { 10856479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 10866479Sgblack@eecs.umich.edu result = ((DoubleBits >> (realShiftAmt - dataBits)) & 10876479Sgblack@eecs.umich.edu logicalMask) | 10886479Sgblack@eecs.umich.edu (psrc1 << (2 * dataBits - realShiftAmt)); 10896479Sgblack@eecs.umich.edu } 10907967Sgblack@eecs.umich.edu %s 10916479Sgblack@eecs.umich.edu ''' 10927967Sgblack@eecs.umich.edu code = srdCode % "DestReg = merge(DestReg, result, dataSize);" 10937967Sgblack@eecs.umich.edu big_code = srdCode % "DestReg = result & mask(dataSize * 8);" 10946479Sgblack@eecs.umich.edu flag_code = ''' 10956479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10966479Sgblack@eecs.umich.edu if (shiftAmt) { 10976479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10986479Sgblack@eecs.umich.edu //worry about setting them. 10999010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 11009010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 11016479Sgblack@eecs.umich.edu int CFBits = 0; 11029010Snilay@cs.wisc.edu 11036479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11046479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 11056479Sgblack@eecs.umich.edu bits(DoubleBits, dataBits - 1)) || 11066479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 11076479Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) || 11086479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 11096479Sgblack@eecs.umich.edu bits(DoubleBits, realShiftAmt - dataBits - 1))) { 11106479Sgblack@eecs.umich.edu CFBits = 1; 11116479Sgblack@eecs.umich.edu } 11129010Snilay@cs.wisc.edu 11136479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11149010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 11159010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 11169010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 11179010Snilay@cs.wisc.edu } 11189010Snilay@cs.wisc.edu 11196479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 11206479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 11216479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 11229010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 11239010Snilay@cs.wisc.edu 11246479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 11259211Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit, 11269010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 11279010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 11289211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 11299010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11306479Sgblack@eecs.umich.edu } 11316479Sgblack@eecs.umich.edu ''' 11326479Sgblack@eecs.umich.edu 11336479Sgblack@eecs.umich.edu class Mdb(WrRegOp): 11346479Sgblack@eecs.umich.edu code = 'DoubleBits = psrc1 ^ op2;' 11356479Sgblack@eecs.umich.edu 11365040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 11377789Sgblack@eecs.umich.edu code = 'NRIP = psrc1 + sop2 + CSBase;' 11387789Sgblack@eecs.umich.edu else_code = "NRIP = NRIP;" 11395040Sgblack@eecs.umich.edu 11405040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 11419010Snilay@cs.wisc.edu code = ''' 11429010Snilay@cs.wisc.edu uint64_t newFlags = psrc1 ^ op2; 11439010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 11449010Snilay@cs.wisc.edu ecfBit = newFlags & ECFBit; 11459010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 11469211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 11479010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11489010Snilay@cs.wisc.edu ''' 11495040Sgblack@eecs.umich.edu 11505426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 11515426Sgblack@eecs.umich.edu code = ''' 11525426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 11535426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 11549010Snilay@cs.wisc.edu 11555426Sgblack@eecs.umich.edu // Get only the user flags 11569010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11579211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 11589010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 11599010Snilay@cs.wisc.edu ecfBit = 0; 11609010Snilay@cs.wisc.edu ezfBit = 0; 11619010Snilay@cs.wisc.edu 11625426Sgblack@eecs.umich.edu // Get everything else 11635426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 11645426Sgblack@eecs.umich.edu ''' 11655426Sgblack@eecs.umich.edu 11665040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 11677789Sgblack@eecs.umich.edu code = 'DestReg = NRIP - CSBase;' 11685040Sgblack@eecs.umich.edu 11695040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 11709211Snilay@cs.wisc.edu code = 'DestReg = ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit;' 11715040Sgblack@eecs.umich.edu 11725426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 11739010Snilay@cs.wisc.edu code = ''' 11749211Snilay@cs.wisc.edu DestReg = ccFlagBits | cfofBits | dfBit | 11759211Snilay@cs.wisc.edu ecfBit | ezfBit | nccFlagBits; 11769010Snilay@cs.wisc.edu ''' 11775426Sgblack@eecs.umich.edu 11785040Sgblack@eecs.umich.edu class Ruflag(RegOp): 11795040Sgblack@eecs.umich.edu code = ''' 11809211Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | dfBit | 11819211Snilay@cs.wisc.edu ecfBit | ezfBit, imm8); 11824951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 11839010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 11845040Sgblack@eecs.umich.edu ''' 11859010Snilay@cs.wisc.edu 11867967Sgblack@eecs.umich.edu big_code = ''' 11879211Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | dfBit | 11889211Snilay@cs.wisc.edu ecfBit | ezfBit, imm8); 11897967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 11909010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 11917967Sgblack@eecs.umich.edu ''' 11929010Snilay@cs.wisc.edu 11935040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 11945040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 11955040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 11966345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 11974732Sgblack@eecs.umich.edu 11985426Sgblack@eecs.umich.edu class Rflag(RegOp): 11995426Sgblack@eecs.umich.edu code = ''' 12005426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 12019211Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | 12029010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 12039010Snilay@cs.wisc.edu 12045426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 12055426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 12069010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12075426Sgblack@eecs.umich.edu ''' 12089010Snilay@cs.wisc.edu 12097967Sgblack@eecs.umich.edu big_code = ''' 12107967Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 12119211Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | 12129010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 12139010Snilay@cs.wisc.edu 12147967Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 12157967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 12169010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12177967Sgblack@eecs.umich.edu ''' 12189010Snilay@cs.wisc.edu 12195426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 12205426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 12215426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 12226345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 12235426Sgblack@eecs.umich.edu 12245040Sgblack@eecs.umich.edu class Sext(RegOp): 12255040Sgblack@eecs.umich.edu code = ''' 12264823Sgblack@eecs.umich.edu IntReg val = psrc1; 12275239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 12285239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 12295239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 12305239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 12315007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 12325007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 12335040Sgblack@eecs.umich.edu ''' 12349010Snilay@cs.wisc.edu 12357967Sgblack@eecs.umich.edu big_code = ''' 12367967Sgblack@eecs.umich.edu IntReg val = psrc1; 12377967Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 12387967Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 12397967Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 12407967Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 12417967Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 12427967Sgblack@eecs.umich.edu DestReg = val & mask(dataSize * 8); 12437967Sgblack@eecs.umich.edu ''' 12449010Snilay@cs.wisc.edu 12455239Sgblack@eecs.umich.edu flag_code = ''' 12469010Snilay@cs.wisc.edu if (!sign_bit) { 12479010Snilay@cs.wisc.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit)); 12489010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit)); 12499010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 12509010Snilay@cs.wisc.edu ezfBit = ezfBit & ~(ext & EZFBit); 12519010Snilay@cs.wisc.edu } else { 12529010Snilay@cs.wisc.edu ccFlagBits = ccFlagBits | (ext & (ZFBit)); 12539010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & (CFBit)); 12549010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 12559010Snilay@cs.wisc.edu ezfBit = ezfBit | (ext & EZFBit); 12569010Snilay@cs.wisc.edu } 12575239Sgblack@eecs.umich.edu ''' 12584714Sgblack@eecs.umich.edu 12595040Sgblack@eecs.umich.edu class Zext(RegOp): 12605927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 12617967Sgblack@eecs.umich.edu big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' 12625241Sgblack@eecs.umich.edu 12635926Sgblack@eecs.umich.edu class Rddr(RegOp): 12645926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12655926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 12666345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12677967Sgblack@eecs.umich.edu rdrCode = ''' 12685926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 12695926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 12705926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 12715926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 12725926Sgblack@eecs.umich.edu } else if (dr7.gd) { 12735926Sgblack@eecs.umich.edu fault = new DebugException(); 12745926Sgblack@eecs.umich.edu } else { 12757967Sgblack@eecs.umich.edu %s 12765926Sgblack@eecs.umich.edu } 12775926Sgblack@eecs.umich.edu ''' 12787967Sgblack@eecs.umich.edu code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" 12797967Sgblack@eecs.umich.edu big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" 12805926Sgblack@eecs.umich.edu 12815926Sgblack@eecs.umich.edu class Wrdr(RegOp): 12825926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12835926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 12846345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12855926Sgblack@eecs.umich.edu code = ''' 12865926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 12875926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 12885926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 12895926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 12906345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 12915926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 12925926Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12935926Sgblack@eecs.umich.edu } else if (dr7.gd) { 12945926Sgblack@eecs.umich.edu fault = new DebugException(); 12955926Sgblack@eecs.umich.edu } else { 12965926Sgblack@eecs.umich.edu DebugDest = psrc1; 12975926Sgblack@eecs.umich.edu } 12985926Sgblack@eecs.umich.edu ''' 12995926Sgblack@eecs.umich.edu 13005296Sgblack@eecs.umich.edu class Rdcr(RegOp): 13015296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13025296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 13036345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13047967Sgblack@eecs.umich.edu rdcrCode = ''' 13055924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 13065296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13075296Sgblack@eecs.umich.edu } else { 13087967Sgblack@eecs.umich.edu %s 13095296Sgblack@eecs.umich.edu } 13105296Sgblack@eecs.umich.edu ''' 13117967Sgblack@eecs.umich.edu code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" 13127967Sgblack@eecs.umich.edu big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" 13135296Sgblack@eecs.umich.edu 13145241Sgblack@eecs.umich.edu class Wrcr(RegOp): 13155241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13165241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 13176345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13185241Sgblack@eecs.umich.edu code = ''' 13195241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 13205241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13215241Sgblack@eecs.umich.edu } else { 13225241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 13235241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 13245241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 13255241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 13265241Sgblack@eecs.umich.edu 13275241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 13285241Sgblack@eecs.umich.edu switch(dest) { 13295241Sgblack@eecs.umich.edu case 0: 13305241Sgblack@eecs.umich.edu { 13315241Sgblack@eecs.umich.edu Efer efer = EferOp; 13325241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 13335241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 13345241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 13355241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 13365241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 13375241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 13385241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13395241Sgblack@eecs.umich.edu } 13405241Sgblack@eecs.umich.edu break; 13415241Sgblack@eecs.umich.edu case 2: 13425241Sgblack@eecs.umich.edu break; 13435241Sgblack@eecs.umich.edu case 3: 13445241Sgblack@eecs.umich.edu break; 13455241Sgblack@eecs.umich.edu case 4: 13465241Sgblack@eecs.umich.edu { 13475241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 13485241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 13495241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 13505241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 13515241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13525241Sgblack@eecs.umich.edu } 13535241Sgblack@eecs.umich.edu break; 13545241Sgblack@eecs.umich.edu case 8: 13555241Sgblack@eecs.umich.edu { 13565241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 13575241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13585241Sgblack@eecs.umich.edu } 13595241Sgblack@eecs.umich.edu default: 13608857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 13618857Sgblack@eecs.umich.edu "Unrecognized control register %d.\\n", dest); 13625241Sgblack@eecs.umich.edu } 13635241Sgblack@eecs.umich.edu ControlDest = newVal; 13645241Sgblack@eecs.umich.edu } 13655241Sgblack@eecs.umich.edu ''' 13665290Sgblack@eecs.umich.edu 13675294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 13685672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 13695294Sgblack@eecs.umich.edu abstract = True 13705290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13715294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 13726345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13735294Sgblack@eecs.umich.edu 13745294Sgblack@eecs.umich.edu class Wrbase(SegOp): 13755290Sgblack@eecs.umich.edu code = ''' 13765294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 13775290Sgblack@eecs.umich.edu ''' 13785290Sgblack@eecs.umich.edu 13795294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 13805290Sgblack@eecs.umich.edu code = ''' 13815294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 13825294Sgblack@eecs.umich.edu ''' 13835294Sgblack@eecs.umich.edu 13845294Sgblack@eecs.umich.edu class Wrsel(SegOp): 13855294Sgblack@eecs.umich.edu code = ''' 13865294Sgblack@eecs.umich.edu SegSelDest = psrc1; 13875294Sgblack@eecs.umich.edu ''' 13885294Sgblack@eecs.umich.edu 13895905Sgblack@eecs.umich.edu class WrAttr(SegOp): 13905905Sgblack@eecs.umich.edu code = ''' 13915905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 13925905Sgblack@eecs.umich.edu ''' 13935905Sgblack@eecs.umich.edu 13945294Sgblack@eecs.umich.edu class Rdbase(SegOp): 13957967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' 13967967Sgblack@eecs.umich.edu big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' 13975294Sgblack@eecs.umich.edu 13985294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 13997967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' 14007967Sgblack@eecs.umich.edu big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' 14015294Sgblack@eecs.umich.edu 14025427Sgblack@eecs.umich.edu class RdAttr(SegOp): 14037967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' 14047967Sgblack@eecs.umich.edu big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' 14055427Sgblack@eecs.umich.edu 14065294Sgblack@eecs.umich.edu class Rdsel(SegOp): 14077967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' 14087967Sgblack@eecs.umich.edu big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' 14095294Sgblack@eecs.umich.edu 14105682Sgblack@eecs.umich.edu class Rdval(RegOp): 14115682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14126345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 14136345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14145682Sgblack@eecs.umich.edu code = ''' 14155682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 14165682Sgblack@eecs.umich.edu ''' 14175682Sgblack@eecs.umich.edu 14185682Sgblack@eecs.umich.edu class Wrval(RegOp): 14195682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14206345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 14216345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14225682Sgblack@eecs.umich.edu code = ''' 14235682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 14245682Sgblack@eecs.umich.edu ''' 14255682Sgblack@eecs.umich.edu 14265428Sgblack@eecs.umich.edu class Chks(RegOp): 14275428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 14285428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 14295428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 14305428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 14315294Sgblack@eecs.umich.edu code = ''' 14325424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 14335433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 14345433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 14355433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 14365294Sgblack@eecs.umich.edu 14375428Sgblack@eecs.umich.edu switch (imm8) 14385428Sgblack@eecs.umich.edu { 14395428Sgblack@eecs.umich.edu case SegNoCheck: 14405428Sgblack@eecs.umich.edu break; 14415428Sgblack@eecs.umich.edu case SegCSCheck: 14426060Sgblack@eecs.umich.edu // Make sure it's the right type 14436060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 14446060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14456060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 14466060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14476060Sgblack@eecs.umich.edu } 14485428Sgblack@eecs.umich.edu break; 14495428Sgblack@eecs.umich.edu case SegCallGateCheck: 14508857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault("CS checks for far " 14518857Sgblack@eecs.umich.edu "calls/jumps through call gates not implemented.\\n"); 14525428Sgblack@eecs.umich.edu break; 14535855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 14545853Sgblack@eecs.umich.edu // Check permissions. 14555674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 14565857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14576058Sgblack@eecs.umich.edu break; 14585674Sgblack@eecs.umich.edu } 14595855Sgblack@eecs.umich.edu // Fall through on purpose 14605855Sgblack@eecs.umich.edu case SegIntGateCheck: 14615853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 14625861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 14635853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 14645853Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14655853Sgblack@eecs.umich.edu } 14665674Sgblack@eecs.umich.edu break; 14675428Sgblack@eecs.umich.edu case SegSSCheck: 14685433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 14695433Sgblack@eecs.umich.edu if (!desc.p) { 14705857Sgblack@eecs.umich.edu fault = new StackFault(selector); 14718626Sgblack@eecs.umich.edu } else if (!(desc.s == 1 && desc.type.codeOrData == 0 && 14728626Sgblack@eecs.umich.edu desc.type.w) || 14735433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 14745433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 14755857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14765433Sgblack@eecs.umich.edu } 14778626Sgblack@eecs.umich.edu } else if (m5reg.submode != SixtyFourBitMode || 14788626Sgblack@eecs.umich.edu m5reg.cpl == 3) { 14798626Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14805433Sgblack@eecs.umich.edu } 14815428Sgblack@eecs.umich.edu break; 14825428Sgblack@eecs.umich.edu case SegIretCheck: 14835428Sgblack@eecs.umich.edu { 14845433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 14855433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 14865433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 14875433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 14885679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 14895857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14905679Sgblack@eecs.umich.edu } else if (!desc.p) { 14915857Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 14925679Sgblack@eecs.umich.edu } 14935428Sgblack@eecs.umich.edu break; 14945428Sgblack@eecs.umich.edu } 14955428Sgblack@eecs.umich.edu case SegIntCSCheck: 14965675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 14975675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 14985679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14995675Sgblack@eecs.umich.edu } 15005675Sgblack@eecs.umich.edu } else { 15018857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault("Interrupt CS " 15028857Sgblack@eecs.umich.edu "checks not implemented in legacy mode.\\n"); 15035675Sgblack@eecs.umich.edu } 15045428Sgblack@eecs.umich.edu break; 15055899Sgblack@eecs.umich.edu case SegTRCheck: 15065899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 15075899Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15085899Sgblack@eecs.umich.edu } 15095899Sgblack@eecs.umich.edu break; 15105900Sgblack@eecs.umich.edu case SegTSSCheck: 15115900Sgblack@eecs.umich.edu if (!desc.p) { 15125900Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 15135900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 15145900Sgblack@eecs.umich.edu (desc.type == 1 && 15155900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 15165935Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15175900Sgblack@eecs.umich.edu } 15185900Sgblack@eecs.umich.edu break; 15195936Sgblack@eecs.umich.edu case SegInGDTCheck: 15205936Sgblack@eecs.umich.edu if (selector.ti) { 15215936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15225936Sgblack@eecs.umich.edu } 15235936Sgblack@eecs.umich.edu break; 15245936Sgblack@eecs.umich.edu case SegLDTCheck: 15255936Sgblack@eecs.umich.edu if (!desc.p) { 15265936Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 15275936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 15285936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15295936Sgblack@eecs.umich.edu } 15305936Sgblack@eecs.umich.edu break; 15315428Sgblack@eecs.umich.edu default: 15328857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15338857Sgblack@eecs.umich.edu "Undefined segment check type.\\n"); 15345428Sgblack@eecs.umich.edu } 15355294Sgblack@eecs.umich.edu ''' 15365294Sgblack@eecs.umich.edu flag_code = ''' 15375294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 15389010Snilay@cs.wisc.edu ccFlagBits = ccFlagBits & ~(ext & ZFBit); 15399010Snilay@cs.wisc.edu ezfBit = ezfBit & ~(ext & EZFBit); 15409010Snilay@cs.wisc.edu 15419010Snilay@cs.wisc.edu if (!selector.si && !selector.ti) { 15429010Snilay@cs.wisc.edu ccFlagBits = ccFlagBits | (ext & ZFBit); 15439010Snilay@cs.wisc.edu ezfBit = ezfBit | (ext & EZFBit); 15449010Snilay@cs.wisc.edu } 15455294Sgblack@eecs.umich.edu ''' 15465294Sgblack@eecs.umich.edu 15475294Sgblack@eecs.umich.edu class Wrdh(RegOp): 15485294Sgblack@eecs.umich.edu code = ''' 15495678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 15505294Sgblack@eecs.umich.edu 15515678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 15525678Sgblack@eecs.umich.edu switch(desc.type) { 15535678Sgblack@eecs.umich.edu case LDT64: 15545678Sgblack@eecs.umich.edu case AvailableTSS64: 15555678Sgblack@eecs.umich.edu case BusyTSS64: 15565678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 15575678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 15585678Sgblack@eecs.umich.edu break; 15595678Sgblack@eecs.umich.edu case CallGate64: 15605678Sgblack@eecs.umich.edu case IntGate64: 15615678Sgblack@eecs.umich.edu case TrapGate64: 15625678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 15635678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 15645678Sgblack@eecs.umich.edu break; 15655678Sgblack@eecs.umich.edu default: 15668857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15678857Sgblack@eecs.umich.edu "Wrdh used with wrong descriptor type!\\n"); 15685678Sgblack@eecs.umich.edu } 15695678Sgblack@eecs.umich.edu DestReg = target; 15705294Sgblack@eecs.umich.edu ''' 15715294Sgblack@eecs.umich.edu 15725409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 15735409Sgblack@eecs.umich.edu code = ''' 15745409Sgblack@eecs.umich.edu TscOp = psrc1; 15755409Sgblack@eecs.umich.edu ''' 15765409Sgblack@eecs.umich.edu 15775409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 15785409Sgblack@eecs.umich.edu code = ''' 15795409Sgblack@eecs.umich.edu DestReg = TscOp; 15805409Sgblack@eecs.umich.edu ''' 15815409Sgblack@eecs.umich.edu 15825429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 15835429Sgblack@eecs.umich.edu code = ''' 15845429Sgblack@eecs.umich.edu DestReg = M5Reg; 15855429Sgblack@eecs.umich.edu ''' 15865429Sgblack@eecs.umich.edu 15875294Sgblack@eecs.umich.edu class Wrdl(RegOp): 15885294Sgblack@eecs.umich.edu code = ''' 15895294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 15905433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 15918857Sgblack@eecs.umich.edu // This while loop is so we can use break statements in the code 15928857Sgblack@eecs.umich.edu // below to skip the rest of this section without a bunch of 15938857Sgblack@eecs.umich.edu // nesting. 15948857Sgblack@eecs.umich.edu while (true) { 15958857Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 15968857Sgblack@eecs.umich.edu if (!desc.p) { 15978857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15988857Sgblack@eecs.umich.edu "Segment not present.\\n"); 15998857Sgblack@eecs.umich.edu break; 16005901Sgblack@eecs.umich.edu } 16018857Sgblack@eecs.umich.edu SegAttr attr = 0; 16028857Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 16038857Sgblack@eecs.umich.edu attr.unusable = 0; 16048857Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 16058857Sgblack@eecs.umich.edu attr.longMode = desc.l; 16068857Sgblack@eecs.umich.edu attr.avl = desc.avl; 16078857Sgblack@eecs.umich.edu attr.granularity = desc.g; 16088857Sgblack@eecs.umich.edu attr.present = desc.p; 16098857Sgblack@eecs.umich.edu attr.system = desc.s; 16108857Sgblack@eecs.umich.edu attr.type = desc.type; 16118857Sgblack@eecs.umich.edu if (!desc.s) { 16128857Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 16138857Sgblack@eecs.umich.edu if (desc.type.e) { 16148857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 16158857Sgblack@eecs.umich.edu "Gate descriptor encountered.\\n"); 16168857Sgblack@eecs.umich.edu break; 16178857Sgblack@eecs.umich.edu } 16188857Sgblack@eecs.umich.edu attr.readable = 1; 16198857Sgblack@eecs.umich.edu attr.writable = 1; 16208857Sgblack@eecs.umich.edu attr.expandDown = 0; 16218857Sgblack@eecs.umich.edu } else { 16228857Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 16238857Sgblack@eecs.umich.edu attr.expandDown = 0; 16248857Sgblack@eecs.umich.edu attr.readable = desc.type.r; 16258857Sgblack@eecs.umich.edu attr.writable = 0; 16268857Sgblack@eecs.umich.edu } else { 16278857Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 16288857Sgblack@eecs.umich.edu attr.readable = 1; 16298857Sgblack@eecs.umich.edu attr.writable = desc.type.w; 16308857Sgblack@eecs.umich.edu } 16318857Sgblack@eecs.umich.edu } 16328857Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 16338857Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 16348857Sgblack@eecs.umich.edu if (desc.g) 16358857Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 16368857Sgblack@eecs.umich.edu SegBaseDest = base; 16378857Sgblack@eecs.umich.edu SegLimitDest = limit; 16388857Sgblack@eecs.umich.edu SegAttrDest = attr; 16395433Sgblack@eecs.umich.edu } else { 16408857Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 16418857Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 16428857Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 16435433Sgblack@eecs.umich.edu } 16448857Sgblack@eecs.umich.edu break; 16455294Sgblack@eecs.umich.edu } 16465290Sgblack@eecs.umich.edu ''' 16474519Sgblack@eecs.umich.edu}}; 1648