regop.isa revision 9010
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 124519Sgblack@eecs.umich.edu// 137087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 147087Snate@binkert.org// modification, are permitted provided that the following conditions are 157087Snate@binkert.org// met: redistributions of source code must retain the above copyright 167087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org// documentation and/or other materials provided with the distribution; 207087Snate@binkert.org// neither the name of the copyright holders nor the names of its 214519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227087Snate@binkert.org// this software without specific prior written permission. 234519Sgblack@eecs.umich.edu// 244519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354519Sgblack@eecs.umich.edu// 364519Sgblack@eecs.umich.edu// Authors: Gabe Black 374519Sgblack@eecs.umich.edu 384519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 394519Sgblack@eecs.umich.edu// 404519Sgblack@eecs.umich.edu// RegOp Microop templates 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 434519Sgblack@eecs.umich.edu 444519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 454519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 464519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474519Sgblack@eecs.umich.edu { 484519Sgblack@eecs.umich.edu Fault fault = NoFault; 494519Sgblack@eecs.umich.edu 504809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 514519Sgblack@eecs.umich.edu %(op_decl)s; 524519Sgblack@eecs.umich.edu %(op_rd)s; 534688Sgblack@eecs.umich.edu 547969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 557969Sgblack@eecs.umich.edu 564688Sgblack@eecs.umich.edu if(%(cond_check)s) 574688Sgblack@eecs.umich.edu { 584688Sgblack@eecs.umich.edu %(code)s; 594688Sgblack@eecs.umich.edu %(flag_code)s; 604688Sgblack@eecs.umich.edu } 614708Sgblack@eecs.umich.edu else 624708Sgblack@eecs.umich.edu { 634708Sgblack@eecs.umich.edu %(else_code)s; 644708Sgblack@eecs.umich.edu } 654519Sgblack@eecs.umich.edu 664519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 674519Sgblack@eecs.umich.edu if(fault == NoFault) 684519Sgblack@eecs.umich.edu { 694519Sgblack@eecs.umich.edu %(op_wb)s; 704519Sgblack@eecs.umich.edu } 714519Sgblack@eecs.umich.edu return fault; 724519Sgblack@eecs.umich.edu } 734519Sgblack@eecs.umich.edu}}; 744519Sgblack@eecs.umich.edu 754519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 764951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 774519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 784519Sgblack@eecs.umich.edu { 794519Sgblack@eecs.umich.edu Fault fault = NoFault; 804519Sgblack@eecs.umich.edu 814519Sgblack@eecs.umich.edu %(op_decl)s; 824519Sgblack@eecs.umich.edu %(op_rd)s; 834688Sgblack@eecs.umich.edu 847969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 857969Sgblack@eecs.umich.edu 864688Sgblack@eecs.umich.edu if(%(cond_check)s) 874688Sgblack@eecs.umich.edu { 884688Sgblack@eecs.umich.edu %(code)s; 894688Sgblack@eecs.umich.edu %(flag_code)s; 904688Sgblack@eecs.umich.edu } 914708Sgblack@eecs.umich.edu else 924708Sgblack@eecs.umich.edu { 934708Sgblack@eecs.umich.edu %(else_code)s; 944708Sgblack@eecs.umich.edu } 954519Sgblack@eecs.umich.edu 964519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 974519Sgblack@eecs.umich.edu if(fault == NoFault) 984519Sgblack@eecs.umich.edu { 994519Sgblack@eecs.umich.edu %(op_wb)s; 1004519Sgblack@eecs.umich.edu } 1014519Sgblack@eecs.umich.edu return fault; 1024519Sgblack@eecs.umich.edu } 1034519Sgblack@eecs.umich.edu}}; 1044519Sgblack@eecs.umich.edu 1054519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1064519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1074519Sgblack@eecs.umich.edu { 1084519Sgblack@eecs.umich.edu public: 1094519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1107620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1116345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1124712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1134519Sgblack@eecs.umich.edu 1144519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1154519Sgblack@eecs.umich.edu }; 1164519Sgblack@eecs.umich.edu}}; 1174519Sgblack@eecs.umich.edu 1184519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1194519Sgblack@eecs.umich.edu 1204951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu public: 1234951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1247620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1256646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1264712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1274519Sgblack@eecs.umich.edu 1284519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1294519Sgblack@eecs.umich.edu }; 1304519Sgblack@eecs.umich.edu}}; 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1334519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1347620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1356345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1364712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1377620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1384688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1394581Sgblack@eecs.umich.edu %(op_class)s) 1404519Sgblack@eecs.umich.edu { 1417626Sgblack@eecs.umich.edu %(constructor)s; 1427894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1434519Sgblack@eecs.umich.edu } 1444519Sgblack@eecs.umich.edu}}; 1454519Sgblack@eecs.umich.edu 1464519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1474951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1487620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1496646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1504712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1517620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1524688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 1534581Sgblack@eecs.umich.edu %(op_class)s) 1544519Sgblack@eecs.umich.edu { 1557626Sgblack@eecs.umich.edu %(constructor)s; 1567894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1574519Sgblack@eecs.umich.edu } 1584519Sgblack@eecs.umich.edu}}; 1594519Sgblack@eecs.umich.edu 1605075Sgblack@eecs.umich.eduoutput header {{ 1615075Sgblack@eecs.umich.edu void 1625075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1635075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 1645428Sgblack@eecs.umich.edu 1655428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 1665674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 1675899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 1685936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 1695428Sgblack@eecs.umich.edu }; 1705678Sgblack@eecs.umich.edu 1715678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 1725678Sgblack@eecs.umich.edu LDT64 = 2, 1735678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 1745678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 1755678Sgblack@eecs.umich.edu CallGate64 = 0xc, 1765678Sgblack@eecs.umich.edu IntGate64 = 0xe, 1775678Sgblack@eecs.umich.edu TrapGate64 = 0xf 1785678Sgblack@eecs.umich.edu }; 1795075Sgblack@eecs.umich.edu}}; 1805075Sgblack@eecs.umich.edu 1815075Sgblack@eecs.umich.eduoutput decoder {{ 1825075Sgblack@eecs.umich.edu void 1835075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1845075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 1855075Sgblack@eecs.umich.edu { 1865075Sgblack@eecs.umich.edu //Check for divide by zero. 1877719Sgblack@eecs.umich.edu assert(divisor != 0); 1885075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 1895075Sgblack@eecs.umich.edu if (divisor <= dividend) { 1905075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 1915075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 1925075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 1935075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 1945075Sgblack@eecs.umich.edu divisor <<= shift; 1955075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 1965075Sgblack@eecs.umich.edu //now larger than the dividend. 1975075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 1985075Sgblack@eecs.umich.edu quotientBit <<= shift; 1995075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2005075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2015075Sgblack@eecs.umich.edu //part of one or two bit division. 2025075Sgblack@eecs.umich.edu if (divisor > dividend) { 2035075Sgblack@eecs.umich.edu quotientBit >>= 1; 2045075Sgblack@eecs.umich.edu divisor >>= 1; 2055075Sgblack@eecs.umich.edu } 2065075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2075075Sgblack@eecs.umich.edu quotient += quotientBit; 2085075Sgblack@eecs.umich.edu remainder -= divisor; 2095075Sgblack@eecs.umich.edu } 2105075Sgblack@eecs.umich.edu } 2115075Sgblack@eecs.umich.edu}}; 2125075Sgblack@eecs.umich.edu 2134519Sgblack@eecs.umich.edulet {{ 2145040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2155040Sgblack@eecs.umich.edu # them will always work. 2165040Sgblack@eecs.umich.edu header_output = "" 2175040Sgblack@eecs.umich.edu decoder_output = "" 2185040Sgblack@eecs.umich.edu exec_output = "" 2195040Sgblack@eecs.umich.edu 2205040Sgblack@eecs.umich.edu immTemplates = ( 2215040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2225040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2235040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2245040Sgblack@eecs.umich.edu 2255040Sgblack@eecs.umich.edu regTemplates = ( 2265040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2275040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2285040Sgblack@eecs.umich.edu MicroRegOpExecute) 2295040Sgblack@eecs.umich.edu 2305040Sgblack@eecs.umich.edu class RegOpMeta(type): 2317967Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, code, big_code, \ 2327967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, cond_control_flag_init): 2335040Sgblack@eecs.umich.edu 2345040Sgblack@eecs.umich.edu # Globals to stick the output in 2355040Sgblack@eecs.umich.edu global header_output 2365040Sgblack@eecs.umich.edu global decoder_output 2375040Sgblack@eecs.umich.edu global exec_output 2385040Sgblack@eecs.umich.edu 2395040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2407894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 2417894SBrad.Beckmann@amd.com cond_control_flag_init)) 2427967Sgblack@eecs.umich.edu allBigCode = "|".join((big_code, flag_code, cond_check, else_code, 2437967Sgblack@eecs.umich.edu cond_control_flag_init)) 2445040Sgblack@eecs.umich.edu 2455040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2465040Sgblack@eecs.umich.edu # of this code. 2478588Sgblack@eecs.umich.edu matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?") 2487967Sgblack@eecs.umich.edu match = matcher.search(allCode + allBigCode) 2495062Sgblack@eecs.umich.edu if match: 2505062Sgblack@eecs.umich.edu typeQual = "" 2515062Sgblack@eecs.umich.edu if match.group("typeQual"): 2525062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 2535062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 2545040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2555062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 2567967Sgblack@eecs.umich.edu matcher.sub(src2_name, big_code), 2575062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 2585062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 2597894SBrad.Beckmann@amd.com matcher.sub(src2_name, else_code), 2607894SBrad.Beckmann@amd.com matcher.sub(src2_name, cond_control_flag_init)) 2616647Sgblack@eecs.umich.edu imm_name = "%simm8" % match.group("prefix") 2625040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 2636647Sgblack@eecs.umich.edu matcher.sub(imm_name, code), 2647967Sgblack@eecs.umich.edu matcher.sub(imm_name, big_code), 2656647Sgblack@eecs.umich.edu matcher.sub(imm_name, flag_code), 2666647Sgblack@eecs.umich.edu matcher.sub(imm_name, cond_check), 2677894SBrad.Beckmann@amd.com matcher.sub(imm_name, else_code), 2687894SBrad.Beckmann@amd.com matcher.sub(imm_name, cond_control_flag_init)) 2695040Sgblack@eecs.umich.edu return 2705040Sgblack@eecs.umich.edu 2715040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 2725040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 2735239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 2745040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2757967Sgblack@eecs.umich.edu code, big_code, "", "true", else_code, "") 2765040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 2775040Sgblack@eecs.umich.edu 2785040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 2795040Sgblack@eecs.umich.edu # compute it. 2807967Sgblack@eecs.umich.edu for (big, all) in ((False, allCode), (True, allBigCode)): 2817967Sgblack@eecs.umich.edu prefix = "" 2827967Sgblack@eecs.umich.edu for (rex, decl) in ( 2837967Sgblack@eecs.umich.edu ("(?<!\w)psrc1(?!\w)", 2847967Sgblack@eecs.umich.edu "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"), 2857967Sgblack@eecs.umich.edu ("(?<!\w)psrc2(?!\w)", 2867967Sgblack@eecs.umich.edu "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"), 2877967Sgblack@eecs.umich.edu ("(?<!\w)spsrc1(?!\w)", 2887967Sgblack@eecs.umich.edu "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"), 2897967Sgblack@eecs.umich.edu ("(?<!\w)spsrc2(?!\w)", 2907967Sgblack@eecs.umich.edu "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"), 2917967Sgblack@eecs.umich.edu ("(?<!\w)simm8(?!\w)", 2927967Sgblack@eecs.umich.edu "int8_t simm8 = imm8;")): 2937967Sgblack@eecs.umich.edu matcher = re.compile(rex) 2947967Sgblack@eecs.umich.edu if matcher.search(all): 2957967Sgblack@eecs.umich.edu prefix += decl + "\n" 2967967Sgblack@eecs.umich.edu if big: 2977967Sgblack@eecs.umich.edu if big_code != "": 2987967Sgblack@eecs.umich.edu big_code = prefix + big_code 2997967Sgblack@eecs.umich.edu else: 3007967Sgblack@eecs.umich.edu code = prefix + code 3015040Sgblack@eecs.umich.edu 3025040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3035040Sgblack@eecs.umich.edu 3045040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3055040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3065040Sgblack@eecs.umich.edu templates = regTemplates 3076647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3085040Sgblack@eecs.umich.edu if matcher.search(allCode): 3095040Sgblack@eecs.umich.edu base += "Imm" 3105040Sgblack@eecs.umich.edu templates = immTemplates 3115040Sgblack@eecs.umich.edu 3125040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3137967Sgblack@eecs.umich.edu iops = [InstObjParams(name, Name + suffix, base, 3145040Sgblack@eecs.umich.edu {"code" : code, 3155040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3165040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3177894SBrad.Beckmann@amd.com "else_code" : else_code, 3187967Sgblack@eecs.umich.edu "cond_control_flag_init" : cond_control_flag_init})] 3197967Sgblack@eecs.umich.edu if big_code != "": 3207967Sgblack@eecs.umich.edu iops += [InstObjParams(name, Name + suffix + "Big", base, 3217967Sgblack@eecs.umich.edu {"code" : big_code, 3227967Sgblack@eecs.umich.edu "flag_code" : flag_code, 3237967Sgblack@eecs.umich.edu "cond_check" : cond_check, 3247967Sgblack@eecs.umich.edu "else_code" : else_code, 3257967Sgblack@eecs.umich.edu "cond_control_flag_init" : 3267967Sgblack@eecs.umich.edu cond_control_flag_init})] 3275040Sgblack@eecs.umich.edu 3285040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3297967Sgblack@eecs.umich.edu for iop in iops: 3307967Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3317967Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3327967Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3335040Sgblack@eecs.umich.edu 3345040Sgblack@eecs.umich.edu 3355040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3364688Sgblack@eecs.umich.edu abstract = False 3375040Sgblack@eecs.umich.edu name = Name.lower() 3384688Sgblack@eecs.umich.edu if "abstract" in dict: 3394688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3404688Sgblack@eecs.umich.edu del dict['abstract'] 3414688Sgblack@eecs.umich.edu 3425040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3434688Sgblack@eecs.umich.edu if not abstract: 3445040Sgblack@eecs.umich.edu cls.className = Name 3455040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3465040Sgblack@eecs.umich.edu code = cls.code 3477967Sgblack@eecs.umich.edu big_code = cls.big_code 3485040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3495040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3505040Sgblack@eecs.umich.edu else_code = cls.else_code 3517894SBrad.Beckmann@amd.com cond_control_flag_init = cls.cond_control_flag_init 3525040Sgblack@eecs.umich.edu 3535040Sgblack@eecs.umich.edu # Set up the C++ classes 3547967Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", code, big_code, 3557967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, 3567967Sgblack@eecs.umich.edu cond_control_flag_init) 3575040Sgblack@eecs.umich.edu 3585040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3595040Sgblack@eecs.umich.edu global microopClasses 3605040Sgblack@eecs.umich.edu microopClasses[name] = cls 3615040Sgblack@eecs.umich.edu 3627894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 3637894SBrad.Beckmann@amd.com cond_control_flag_init)) 3645040Sgblack@eecs.umich.edu 3655040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3665040Sgblack@eecs.umich.edu # of this code. 3678588Sgblack@eecs.umich.edu matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?") 3685040Sgblack@eecs.umich.edu if matcher.search(allCode): 3695040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3704688Sgblack@eecs.umich.edu return cls 3714688Sgblack@eecs.umich.edu 3725040Sgblack@eecs.umich.edu 3735040Sgblack@eecs.umich.edu class RegOp(X86Microop): 3745040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 3755040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 3764688Sgblack@eecs.umich.edu abstract = True 3774688Sgblack@eecs.umich.edu 3785040Sgblack@eecs.umich.edu # Default template parameter values 3797967Sgblack@eecs.umich.edu big_code = "" 3805040Sgblack@eecs.umich.edu flag_code = "" 3815040Sgblack@eecs.umich.edu cond_check = "true" 3825040Sgblack@eecs.umich.edu else_code = ";" 3837894SBrad.Beckmann@amd.com cond_control_flag_init = "" 3845040Sgblack@eecs.umich.edu 3855040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 3864519Sgblack@eecs.umich.edu self.dest = dest 3874519Sgblack@eecs.umich.edu self.src1 = src1 3885040Sgblack@eecs.umich.edu self.op2 = op2 3894688Sgblack@eecs.umich.edu self.flags = flags 3904701Sgblack@eecs.umich.edu self.dataSize = dataSize 3914688Sgblack@eecs.umich.edu if flags is None: 3924688Sgblack@eecs.umich.edu self.ext = 0 3934688Sgblack@eecs.umich.edu else: 3944688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 3954688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 3964688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 3974688Sgblack@eecs.umich.edu self.className += "Flags" 3984519Sgblack@eecs.umich.edu 3997620Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 4007967Sgblack@eecs.umich.edu if self.big_code != "": 4017967Sgblack@eecs.umich.edu className = self.className 4027967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4037967Sgblack@eecs.umich.edu className += "Imm" 4047967Sgblack@eecs.umich.edu allocString = ''' 4057967Sgblack@eecs.umich.edu (%(dataSize)s >= 4) ? 4067967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)sBig(machInst, 4077967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4087967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) : 4097967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)s(machInst, 4107967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4117967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) 4127967Sgblack@eecs.umich.edu ''' 4137967Sgblack@eecs.umich.edu allocator = allocString % { 4147967Sgblack@eecs.umich.edu "class_name" : className, 4157967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4167967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4177967Sgblack@eecs.umich.edu "dest" : self.dest, 4187967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4197967Sgblack@eecs.umich.edu "ext" : self.ext} 4207967Sgblack@eecs.umich.edu return allocator 4217967Sgblack@eecs.umich.edu else: 4227967Sgblack@eecs.umich.edu className = self.className 4237967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4247967Sgblack@eecs.umich.edu className += "Imm" 4257967Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 4267967Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4277967Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4287967Sgblack@eecs.umich.edu "class_name" : className, 4297967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4307967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4317967Sgblack@eecs.umich.edu "dest" : self.dest, 4327967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4337967Sgblack@eecs.umich.edu "ext" : self.ext} 4347967Sgblack@eecs.umich.edu return allocator 4354519Sgblack@eecs.umich.edu 4365040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4374688Sgblack@eecs.umich.edu abstract = True 4385040Sgblack@eecs.umich.edu flag_code = ''' 4395040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4405115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4419010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, ext & ~mask, 4429010Snilay@cs.wisc.edu result, psrc1, op2); 4439010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 4449010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 4459010Snilay@cs.wisc.edu 4465040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4479010Snilay@cs.wisc.edu cfofBits = cfofBits & ~((CFBit | OFBit) & ext); 4489010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ECFBit & ext); 4495040Sgblack@eecs.umich.edu ''' 4504519Sgblack@eecs.umich.edu 4515040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4525040Sgblack@eecs.umich.edu abstract = True 4539010Snilay@cs.wisc.edu flag_code = ''' 4549010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit | 4559010Snilay@cs.wisc.edu ezfBit, ext, result, psrc1, op2); 4569010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 4579010Snilay@cs.wisc.edu ecfBit = newFlags & ECFBit; 4589010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 4599010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 4609010Snilay@cs.wisc.edu ''' 4614519Sgblack@eecs.umich.edu 4625040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4635040Sgblack@eecs.umich.edu abstract = True 4649010Snilay@cs.wisc.edu flag_code = ''' 4659010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit | 4669010Snilay@cs.wisc.edu ezfBit, ext, result, psrc1, ~op2, true); 4679010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 4689010Snilay@cs.wisc.edu ecfBit = newFlags & ECFBit; 4699010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 4709010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 4719010Snilay@cs.wisc.edu ''' 4724519Sgblack@eecs.umich.edu 4735040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4745040Sgblack@eecs.umich.edu abstract = True 4759010Snilay@cs.wisc.edu cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \ 4769010Snilay@cs.wisc.edu ext)" 4777894SBrad.Beckmann@amd.com cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];" 4784519Sgblack@eecs.umich.edu 4795063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4805063Sgblack@eecs.umich.edu abstract = True 4815063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4825063Sgblack@eecs.umich.edu if not src1: 4835063Sgblack@eecs.umich.edu src1 = dest 4846345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4856345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4865063Sgblack@eecs.umich.edu 4875063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4885063Sgblack@eecs.umich.edu abstract = True 4895063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4906345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4916345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 4925063Sgblack@eecs.umich.edu 4935040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4947969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' 4957969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' 4964595Sgblack@eecs.umich.edu 4975040Sgblack@eecs.umich.edu class Or(LogicRegOp): 4987969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' 4997969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' 5004595Sgblack@eecs.umich.edu 5015040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 5025040Sgblack@eecs.umich.edu code = ''' 5039010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5047969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); 5055040Sgblack@eecs.umich.edu ''' 5067967Sgblack@eecs.umich.edu big_code = ''' 5079010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5087969Sgblack@eecs.umich.edu DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); 5097967Sgblack@eecs.umich.edu ''' 5105040Sgblack@eecs.umich.edu 5115040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 5125040Sgblack@eecs.umich.edu code = ''' 5139010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5147969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); 5155040Sgblack@eecs.umich.edu ''' 5167967Sgblack@eecs.umich.edu big_code = ''' 5179010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5187969Sgblack@eecs.umich.edu DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); 5197967Sgblack@eecs.umich.edu ''' 5205040Sgblack@eecs.umich.edu 5215040Sgblack@eecs.umich.edu class And(LogicRegOp): 5227969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' 5237969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' 5245040Sgblack@eecs.umich.edu 5255040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5267969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' 5277969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' 5285040Sgblack@eecs.umich.edu 5295040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5307969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' 5317969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)' 5325040Sgblack@eecs.umich.edu 5335063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5345040Sgblack@eecs.umich.edu code = ''' 5355063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5365063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5376742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5386430Sgblack@eecs.umich.edu uint64_t hiResult; 5396430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5406430Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5416461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5426430Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5436430Sgblack@eecs.umich.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5446430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 5456430Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5466462Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 5476430Sgblack@eecs.umich.edu hiResult -= op2; 5486462Sgblack@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 5496430Sgblack@eecs.umich.edu hiResult -= psrc1; 5506430Sgblack@eecs.umich.edu ProdHi = hiResult; 5515040Sgblack@eecs.umich.edu ''' 5526463Sgblack@eecs.umich.edu flag_code = ''' 5536463Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 5546463Sgblack@eecs.umich.edu bits(ProdLow, dataSize * 8 - 1)) { 5559010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & (CFBit | OFBit)); 5569010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 5576463Sgblack@eecs.umich.edu } else { 5589010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 5599010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 5606463Sgblack@eecs.umich.edu } 5616463Sgblack@eecs.umich.edu ''' 5625040Sgblack@eecs.umich.edu 5635063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5645040Sgblack@eecs.umich.edu code = ''' 5655063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5664809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5676742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5686430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5695063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5706461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5715063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5725063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5736430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) / shifter) + 5745063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5755040Sgblack@eecs.umich.edu ''' 5766463Sgblack@eecs.umich.edu flag_code = ''' 5776463Sgblack@eecs.umich.edu if (ProdHi) { 5789010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & (CFBit | OFBit)); 5799010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 5806463Sgblack@eecs.umich.edu } else { 5819010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 5829010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 5836463Sgblack@eecs.umich.edu } 5846463Sgblack@eecs.umich.edu ''' 5855040Sgblack@eecs.umich.edu 5865063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5875063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5887967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdLow & mask(dataSize * 8);' 5895040Sgblack@eecs.umich.edu 5905063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5915063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5925063Sgblack@eecs.umich.edu if not src1: 5935063Sgblack@eecs.umich.edu src1 = dest 5946345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 5956345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 5965063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5977967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdHi & mask(dataSize * 8);' 5985062Sgblack@eecs.umich.edu 5995075Sgblack@eecs.umich.edu # One or two bit divide 6005075Sgblack@eecs.umich.edu class Div1(WrRegOp): 6015040Sgblack@eecs.umich.edu code = ''' 6025075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 6035075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 6045075Sgblack@eecs.umich.edu uint64_t quotient = 0; 6055075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 6065075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 6075075Sgblack@eecs.umich.edu //a source. 6085075Sgblack@eecs.umich.edu uint64_t divisor = op2; 6095075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 6105075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 6115075Sgblack@eecs.umich.edu //Do the division. 6127719Sgblack@eecs.umich.edu if (divisor == 0) { 6137719Sgblack@eecs.umich.edu fault = new DivideByZero; 6147719Sgblack@eecs.umich.edu } else { 6157719Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6167719Sgblack@eecs.umich.edu //Record the final results. 6177719Sgblack@eecs.umich.edu Remainder = remainder; 6187719Sgblack@eecs.umich.edu Quotient = quotient; 6197719Sgblack@eecs.umich.edu Divisor = divisor; 6207719Sgblack@eecs.umich.edu } 6215040Sgblack@eecs.umich.edu ''' 6224823Sgblack@eecs.umich.edu 6235075Sgblack@eecs.umich.edu # Step divide 6245075Sgblack@eecs.umich.edu class Div2(RegOp): 6257967Sgblack@eecs.umich.edu divCode = ''' 6265075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 6275075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 6285075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 6295075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 6305075Sgblack@eecs.umich.edu int remaining = op2; 6315075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 6325075Sgblack@eecs.umich.edu //little. 6337719Sgblack@eecs.umich.edu if (divisor == 0) { 6347719Sgblack@eecs.umich.edu fault = new DivideByZero; 6357719Sgblack@eecs.umich.edu } else if (remaining) { 6367070Sgblack@eecs.umich.edu if (divisor & (ULL(1) << 63)) { 6377070Sgblack@eecs.umich.edu while (remaining && !(dividend & (ULL(1) << 63))) { 6387070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6397070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6407070Sgblack@eecs.umich.edu quotient <<= 1; 6417070Sgblack@eecs.umich.edu remaining--; 6427070Sgblack@eecs.umich.edu } 6437070Sgblack@eecs.umich.edu if (dividend & (ULL(1) << 63)) { 6447080Sgblack@eecs.umich.edu bool highBit = false; 6457070Sgblack@eecs.umich.edu if (dividend < divisor && remaining) { 6467080Sgblack@eecs.umich.edu highBit = true; 6477070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6487070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6497070Sgblack@eecs.umich.edu quotient <<= 1; 6507070Sgblack@eecs.umich.edu remaining--; 6517070Sgblack@eecs.umich.edu } 6527080Sgblack@eecs.umich.edu if (highBit || divisor <= dividend) { 6537080Sgblack@eecs.umich.edu quotient++; 6547080Sgblack@eecs.umich.edu dividend -= divisor; 6557080Sgblack@eecs.umich.edu } 6567070Sgblack@eecs.umich.edu } 6577070Sgblack@eecs.umich.edu remainder = dividend; 6587070Sgblack@eecs.umich.edu } else { 6597070Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 6607070Sgblack@eecs.umich.edu while (dividend < divisor && remaining) { 6617070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6627070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6637070Sgblack@eecs.umich.edu quotient <<= 1; 6647070Sgblack@eecs.umich.edu remaining--; 6657070Sgblack@eecs.umich.edu } 6667070Sgblack@eecs.umich.edu remainder = dividend; 6677070Sgblack@eecs.umich.edu //Do the division. 6687070Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6695075Sgblack@eecs.umich.edu } 6705075Sgblack@eecs.umich.edu } 6715075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 6727967Sgblack@eecs.umich.edu %s 6735075Sgblack@eecs.umich.edu //Record the final results 6745075Sgblack@eecs.umich.edu Remainder = remainder; 6755075Sgblack@eecs.umich.edu Quotient = quotient; 6765075Sgblack@eecs.umich.edu ''' 6777967Sgblack@eecs.umich.edu code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" 6787967Sgblack@eecs.umich.edu big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" 6795075Sgblack@eecs.umich.edu flag_code = ''' 6807480Sgblack@eecs.umich.edu if (remaining == 0) 6819010Snilay@cs.wisc.edu ezfBit = ezfBit | (ext & EZFBit); 6825075Sgblack@eecs.umich.edu else 6839010Snilay@cs.wisc.edu ezfBit = ezfBit & ~(ext & EZFBit); 6845075Sgblack@eecs.umich.edu ''' 6854732Sgblack@eecs.umich.edu 6865075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6875075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6887967Sgblack@eecs.umich.edu big_code = 'DestReg = Quotient & mask(dataSize * 8);' 6895075Sgblack@eecs.umich.edu 6905075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6915075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6927967Sgblack@eecs.umich.edu big_code = 'DestReg = Remainder & mask(dataSize * 8);' 6935040Sgblack@eecs.umich.edu 6945040Sgblack@eecs.umich.edu class Mov(CondRegOp): 6955040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6966482Sgblack@eecs.umich.edu else_code = 'DestReg = DestReg;' 6975040Sgblack@eecs.umich.edu 6984732Sgblack@eecs.umich.edu # Shift instructions 6995040Sgblack@eecs.umich.edu 7005076Sgblack@eecs.umich.edu class Sll(RegOp): 7015040Sgblack@eecs.umich.edu code = ''' 7024756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7034823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 7045040Sgblack@eecs.umich.edu ''' 7057967Sgblack@eecs.umich.edu big_code = ''' 7067967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7077967Sgblack@eecs.umich.edu DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); 7087967Sgblack@eecs.umich.edu ''' 7095076Sgblack@eecs.umich.edu flag_code = ''' 7105076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7115076Sgblack@eecs.umich.edu if (shiftAmt) { 7125076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7135076Sgblack@eecs.umich.edu //worry about setting them. 7149010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 7159010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 7169010Snilay@cs.wisc.edu 7175076Sgblack@eecs.umich.edu int CFBits = 0; 7185076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 7196441Sgblack@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 7206441Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 7215076Sgblack@eecs.umich.edu CFBits = 1; 7226441Sgblack@eecs.umich.edu } 7239010Snilay@cs.wisc.edu 7245076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7259010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 7269010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 7279010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 7289010Snilay@cs.wisc.edu } 7299010Snilay@cs.wisc.edu 7305076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7315076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 7329010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 7339010Snilay@cs.wisc.edu 7345076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7359010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, 7369010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 7379010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 7389010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 7395076Sgblack@eecs.umich.edu } 7405076Sgblack@eecs.umich.edu ''' 7415040Sgblack@eecs.umich.edu 7425076Sgblack@eecs.umich.edu class Srl(RegOp): 7437967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 7447967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to mask them out 7457967Sgblack@eecs.umich.edu # to be sure they're zero. 7465040Sgblack@eecs.umich.edu code = ''' 7474756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7484732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7494823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 7505040Sgblack@eecs.umich.edu ''' 7517967Sgblack@eecs.umich.edu big_code = ''' 7527967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7537967Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7547967Sgblack@eecs.umich.edu DestReg = (psrc1 >> shiftAmt) & logicalMask; 7557967Sgblack@eecs.umich.edu ''' 7565076Sgblack@eecs.umich.edu flag_code = ''' 7575076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7585076Sgblack@eecs.umich.edu if (shiftAmt) { 7595076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7605076Sgblack@eecs.umich.edu //worry about setting them. 7619010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 7629010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 7639010Snilay@cs.wisc.edu 7645076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7656442Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7666442Sgblack@eecs.umich.edu shiftAmt <= dataSize * 8 && 7676442Sgblack@eecs.umich.edu bits(SrcReg1, shiftAmt - 1)) { 7689010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 7699010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 7706442Sgblack@eecs.umich.edu } 7719010Snilay@cs.wisc.edu 7725076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7735076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 7749010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 7759010Snilay@cs.wisc.edu 7765076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7779010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, 7789010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 7799010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 7809010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 7815076Sgblack@eecs.umich.edu } 7825076Sgblack@eecs.umich.edu ''' 7835040Sgblack@eecs.umich.edu 7845076Sgblack@eecs.umich.edu class Sra(RegOp): 7857967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 7867967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to sign extend 7877967Sgblack@eecs.umich.edu # them manually to be sure. 7885040Sgblack@eecs.umich.edu code = ''' 7894756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7906443Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 7915032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 7924823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 7935040Sgblack@eecs.umich.edu ''' 7947967Sgblack@eecs.umich.edu big_code = ''' 7957967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7967967Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 7977967Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 7987967Sgblack@eecs.umich.edu DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); 7997967Sgblack@eecs.umich.edu ''' 8005076Sgblack@eecs.umich.edu flag_code = ''' 8015076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8025076Sgblack@eecs.umich.edu if (shiftAmt) { 8035076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8045076Sgblack@eecs.umich.edu //worry about setting them. 8059010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 8069010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 8079010Snilay@cs.wisc.edu 8085076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8096444Sgblack@eecs.umich.edu uint8_t effectiveShift = 8106444Sgblack@eecs.umich.edu (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 8116444Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8126444Sgblack@eecs.umich.edu bits(SrcReg1, effectiveShift - 1)) { 8139010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 8149010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 8156444Sgblack@eecs.umich.edu } 8169010Snilay@cs.wisc.edu 8175076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8189010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, 8199010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 8209010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 8219010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 8225076Sgblack@eecs.umich.edu } 8235076Sgblack@eecs.umich.edu ''' 8245040Sgblack@eecs.umich.edu 8255076Sgblack@eecs.umich.edu class Ror(RegOp): 8265040Sgblack@eecs.umich.edu code = ''' 8274732Sgblack@eecs.umich.edu uint8_t shiftAmt = 8284756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8296449Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 8307967Sgblack@eecs.umich.edu if (realShiftAmt) { 8316449Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 8326449Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 8334732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8347967Sgblack@eecs.umich.edu } else 8356447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8365040Sgblack@eecs.umich.edu ''' 8375076Sgblack@eecs.umich.edu flag_code = ''' 8385076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8395076Sgblack@eecs.umich.edu if (shiftAmt) { 8405076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8415076Sgblack@eecs.umich.edu //worry about setting them. 8429010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 8439010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 8449010Snilay@cs.wisc.edu 8455076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 8465076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8475076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 8485076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8499010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && msb) { 8509010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 8519010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 8529010Snilay@cs.wisc.edu } 8539010Snilay@cs.wisc.edu 8545076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8555076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 8569010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 8579010Snilay@cs.wisc.edu 8585076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8599010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, 8609010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 8619010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 8629010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 8635076Sgblack@eecs.umich.edu } 8645076Sgblack@eecs.umich.edu ''' 8655040Sgblack@eecs.umich.edu 8665076Sgblack@eecs.umich.edu class Rcr(RegOp): 8675040Sgblack@eecs.umich.edu code = ''' 8684733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8694756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8706454Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 8717967Sgblack@eecs.umich.edu if (realShiftAmt) { 8729010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 8736454Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 8746454Sgblack@eecs.umich.edu if (realShiftAmt > 1) 8756454Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 8766454Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 8774733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8787967Sgblack@eecs.umich.edu } else 8796447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8805040Sgblack@eecs.umich.edu ''' 8815076Sgblack@eecs.umich.edu flag_code = ''' 8825076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8835076Sgblack@eecs.umich.edu if (shiftAmt) { 8849010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 8855076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8865076Sgblack@eecs.umich.edu //worry about setting them. 8879010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 8889010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 8899010Snilay@cs.wisc.edu 8905076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8916453Sgblack@eecs.umich.edu if ((ext & OFBit) && (origCFBit ^ 8926453Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) { 8939010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 8946453Sgblack@eecs.umich.edu } 8955076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8966454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8976454Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : 8986454Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) { 8999010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 9009010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 9016454Sgblack@eecs.umich.edu } 9029010Snilay@cs.wisc.edu 9035076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9049010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, 9059010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 9069010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 9079010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 9085076Sgblack@eecs.umich.edu } 9095076Sgblack@eecs.umich.edu ''' 9105040Sgblack@eecs.umich.edu 9115076Sgblack@eecs.umich.edu class Rol(RegOp): 9125040Sgblack@eecs.umich.edu code = ''' 9134732Sgblack@eecs.umich.edu uint8_t shiftAmt = 9144756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9156446Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 9167967Sgblack@eecs.umich.edu if (realShiftAmt) { 9176446Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 9184732Sgblack@eecs.umich.edu uint64_t bottom = 9196446Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 9204732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9217967Sgblack@eecs.umich.edu } else 9226447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9235040Sgblack@eecs.umich.edu ''' 9245076Sgblack@eecs.umich.edu flag_code = ''' 9255076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9265076Sgblack@eecs.umich.edu if (shiftAmt) { 9275076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9285076Sgblack@eecs.umich.edu //worry about setting them. 9299010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 9309010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 9319010Snilay@cs.wisc.edu 9325076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 9335076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 9345076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 9355076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9369010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && lsb) { 9379010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 9389010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 9399010Snilay@cs.wisc.edu } 9409010Snilay@cs.wisc.edu 9415076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9425076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 9439010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 9449010Snilay@cs.wisc.edu 9455076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9469010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, 9479010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 9489010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 9499010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 9505076Sgblack@eecs.umich.edu } 9515076Sgblack@eecs.umich.edu ''' 9525040Sgblack@eecs.umich.edu 9535076Sgblack@eecs.umich.edu class Rcl(RegOp): 9545040Sgblack@eecs.umich.edu code = ''' 9554733Sgblack@eecs.umich.edu uint8_t shiftAmt = 9564756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9576456Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 9587967Sgblack@eecs.umich.edu if (realShiftAmt) { 9599010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 9606456Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 9616456Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (realShiftAmt - 1); 9624733Sgblack@eecs.umich.edu if(shiftAmt > 1) 9634733Sgblack@eecs.umich.edu bottom |= 9644823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 9656456Sgblack@eecs.umich.edu dataSize * 8 - realShiftAmt + 1); 9664733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9677967Sgblack@eecs.umich.edu } else 9686447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9695040Sgblack@eecs.umich.edu ''' 9705076Sgblack@eecs.umich.edu flag_code = ''' 9715076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9725076Sgblack@eecs.umich.edu if (shiftAmt) { 9739010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 9745076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9755076Sgblack@eecs.umich.edu //worry about setting them. 9769010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 9779010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 9789010Snilay@cs.wisc.edu 9795076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 9806456Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 9815076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9826456Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 9839010Snilay@cs.wisc.edu (realShiftAmt == 0) ? origCFBit : CFBits) { 9849010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 9859010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 9869010Snilay@cs.wisc.edu } 9879010Snilay@cs.wisc.edu 9885076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9895076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 9909010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 9919010Snilay@cs.wisc.edu 9925076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9939010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, 9949010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 9959010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 9969010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 9975076Sgblack@eecs.umich.edu } 9985076Sgblack@eecs.umich.edu ''' 9994732Sgblack@eecs.umich.edu 10006479Sgblack@eecs.umich.edu class Sld(RegOp): 10017967Sgblack@eecs.umich.edu sldCode = ''' 10026479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 10036479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 10047967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 10056479Sgblack@eecs.umich.edu uint64_t result; 10066479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 10076479Sgblack@eecs.umich.edu result = psrc1; 10086479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 10096479Sgblack@eecs.umich.edu result = (psrc1 << realShiftAmt) | 10106479Sgblack@eecs.umich.edu (DoubleBits >> (dataBits - realShiftAmt)); 10116479Sgblack@eecs.umich.edu } else { 10126479Sgblack@eecs.umich.edu result = (DoubleBits << (realShiftAmt - dataBits)) | 10136479Sgblack@eecs.umich.edu (psrc1 >> (2 * dataBits - realShiftAmt)); 10146479Sgblack@eecs.umich.edu } 10157967Sgblack@eecs.umich.edu %s 10166479Sgblack@eecs.umich.edu ''' 10177967Sgblack@eecs.umich.edu code = sldCode % "DestReg = merge(DestReg, result, dataSize);" 10187967Sgblack@eecs.umich.edu big_code = sldCode % "DestReg = result & mask(dataSize * 8);" 10196479Sgblack@eecs.umich.edu flag_code = ''' 10206479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10216479Sgblack@eecs.umich.edu if (shiftAmt) { 10226479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10236479Sgblack@eecs.umich.edu //worry about setting them. 10249010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 10259010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 10266479Sgblack@eecs.umich.edu int CFBits = 0; 10279010Snilay@cs.wisc.edu 10286479Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 10296479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 10306479Sgblack@eecs.umich.edu bits(DoubleBits, 0)) || 10316479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 10326479Sgblack@eecs.umich.edu bits(SrcReg1, dataBits - realShiftAmt)) || 10336479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 10346479Sgblack@eecs.umich.edu bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 10356479Sgblack@eecs.umich.edu CFBits = 1; 10366479Sgblack@eecs.umich.edu } 10379010Snilay@cs.wisc.edu 10386479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10399010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 10409010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 10419010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 10429010Snilay@cs.wisc.edu } 10439010Snilay@cs.wisc.edu 10446479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10456479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 10466479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 10479010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 10489010Snilay@cs.wisc.edu 10496479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10509010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, 10519010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 10529010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 10539010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 10546479Sgblack@eecs.umich.edu } 10556479Sgblack@eecs.umich.edu ''' 10566479Sgblack@eecs.umich.edu 10576479Sgblack@eecs.umich.edu class Srd(RegOp): 10587967Sgblack@eecs.umich.edu srdCode = ''' 10596479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 10606479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 10617967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 10626479Sgblack@eecs.umich.edu uint64_t result; 10636479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 10646479Sgblack@eecs.umich.edu result = psrc1; 10656479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 10666479Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right 10676479Sgblack@eecs.umich.edu // shift is not defined in the C/C++ standard, we have to 10686479Sgblack@eecs.umich.edu // mask them out to be sure they're zero. 10696479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataBits - realShiftAmt); 10706479Sgblack@eecs.umich.edu result = ((psrc1 >> realShiftAmt) & logicalMask) | 10716479Sgblack@eecs.umich.edu (DoubleBits << (dataBits - realShiftAmt)); 10726479Sgblack@eecs.umich.edu } else { 10736479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 10746479Sgblack@eecs.umich.edu result = ((DoubleBits >> (realShiftAmt - dataBits)) & 10756479Sgblack@eecs.umich.edu logicalMask) | 10766479Sgblack@eecs.umich.edu (psrc1 << (2 * dataBits - realShiftAmt)); 10776479Sgblack@eecs.umich.edu } 10787967Sgblack@eecs.umich.edu %s 10796479Sgblack@eecs.umich.edu ''' 10807967Sgblack@eecs.umich.edu code = srdCode % "DestReg = merge(DestReg, result, dataSize);" 10817967Sgblack@eecs.umich.edu big_code = srdCode % "DestReg = result & mask(dataSize * 8);" 10826479Sgblack@eecs.umich.edu flag_code = ''' 10836479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10846479Sgblack@eecs.umich.edu if (shiftAmt) { 10856479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10866479Sgblack@eecs.umich.edu //worry about setting them. 10879010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); 10889010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 10896479Sgblack@eecs.umich.edu int CFBits = 0; 10909010Snilay@cs.wisc.edu 10916479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10926479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 10936479Sgblack@eecs.umich.edu bits(DoubleBits, dataBits - 1)) || 10946479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 10956479Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) || 10966479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 10976479Sgblack@eecs.umich.edu bits(DoubleBits, realShiftAmt - dataBits - 1))) { 10986479Sgblack@eecs.umich.edu CFBits = 1; 10996479Sgblack@eecs.umich.edu } 11009010Snilay@cs.wisc.edu 11016479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11029010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 11039010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & CFBit); 11049010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 11059010Snilay@cs.wisc.edu } 11069010Snilay@cs.wisc.edu 11076479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 11086479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 11096479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 11109010Snilay@cs.wisc.edu cfofBits = cfofBits | OFBit; 11119010Snilay@cs.wisc.edu 11126479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 11139010Snilay@cs.wisc.edu uint64_t newFlags = genFlags(ccFlagBits | ezfBit, 11149010Snilay@cs.wisc.edu ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); 11159010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 11169010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11176479Sgblack@eecs.umich.edu } 11186479Sgblack@eecs.umich.edu ''' 11196479Sgblack@eecs.umich.edu 11206479Sgblack@eecs.umich.edu class Mdb(WrRegOp): 11216479Sgblack@eecs.umich.edu code = 'DoubleBits = psrc1 ^ op2;' 11226479Sgblack@eecs.umich.edu 11235040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 11247789Sgblack@eecs.umich.edu code = 'NRIP = psrc1 + sop2 + CSBase;' 11257789Sgblack@eecs.umich.edu else_code = "NRIP = NRIP;" 11265040Sgblack@eecs.umich.edu 11275040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 11289010Snilay@cs.wisc.edu code = ''' 11299010Snilay@cs.wisc.edu uint64_t newFlags = psrc1 ^ op2; 11309010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 11319010Snilay@cs.wisc.edu ecfBit = newFlags & ECFBit; 11329010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 11339010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11349010Snilay@cs.wisc.edu ''' 11355040Sgblack@eecs.umich.edu 11365426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 11375426Sgblack@eecs.umich.edu code = ''' 11385426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 11395426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 11409010Snilay@cs.wisc.edu 11415426Sgblack@eecs.umich.edu // Get only the user flags 11429010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11439010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 11449010Snilay@cs.wisc.edu ecfBit = 0; 11459010Snilay@cs.wisc.edu ezfBit = 0; 11469010Snilay@cs.wisc.edu 11475426Sgblack@eecs.umich.edu // Get everything else 11485426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 11495426Sgblack@eecs.umich.edu ''' 11505426Sgblack@eecs.umich.edu 11515040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 11527789Sgblack@eecs.umich.edu code = 'DestReg = NRIP - CSBase;' 11535040Sgblack@eecs.umich.edu 11545040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 11559010Snilay@cs.wisc.edu code = 'DestReg = ccFlagBits | cfofBits | ecfBit | ezfBit;' 11565040Sgblack@eecs.umich.edu 11575426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 11589010Snilay@cs.wisc.edu code = ''' 11599010Snilay@cs.wisc.edu DestReg = ccFlagBits | cfofBits | ecfBit | ezfBit | nccFlagBits; 11609010Snilay@cs.wisc.edu ''' 11615426Sgblack@eecs.umich.edu 11625040Sgblack@eecs.umich.edu class Ruflag(RegOp): 11635040Sgblack@eecs.umich.edu code = ''' 11649010Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | ecfBit | ezfBit, imm8); 11654951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 11669010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 11675040Sgblack@eecs.umich.edu ''' 11689010Snilay@cs.wisc.edu 11697967Sgblack@eecs.umich.edu big_code = ''' 11709010Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | ecfBit | ezfBit, imm8); 11717967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 11729010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 11737967Sgblack@eecs.umich.edu ''' 11749010Snilay@cs.wisc.edu 11755040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 11765040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 11775040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 11786345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 11794732Sgblack@eecs.umich.edu 11805426Sgblack@eecs.umich.edu class Rflag(RegOp): 11815426Sgblack@eecs.umich.edu code = ''' 11825426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 11839010Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | 11849010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 11859010Snilay@cs.wisc.edu 11865426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 11875426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 11889010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 11895426Sgblack@eecs.umich.edu ''' 11909010Snilay@cs.wisc.edu 11917967Sgblack@eecs.umich.edu big_code = ''' 11927967Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 11939010Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | 11949010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 11959010Snilay@cs.wisc.edu 11967967Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 11977967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 11989010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 11997967Sgblack@eecs.umich.edu ''' 12009010Snilay@cs.wisc.edu 12015426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 12025426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 12035426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 12046345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 12055426Sgblack@eecs.umich.edu 12065040Sgblack@eecs.umich.edu class Sext(RegOp): 12075040Sgblack@eecs.umich.edu code = ''' 12084823Sgblack@eecs.umich.edu IntReg val = psrc1; 12095239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 12105239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 12115239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 12125239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 12135007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 12145007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 12155040Sgblack@eecs.umich.edu ''' 12169010Snilay@cs.wisc.edu 12177967Sgblack@eecs.umich.edu big_code = ''' 12187967Sgblack@eecs.umich.edu IntReg val = psrc1; 12197967Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 12207967Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 12217967Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 12227967Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 12237967Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 12247967Sgblack@eecs.umich.edu DestReg = val & mask(dataSize * 8); 12257967Sgblack@eecs.umich.edu ''' 12269010Snilay@cs.wisc.edu 12275239Sgblack@eecs.umich.edu flag_code = ''' 12289010Snilay@cs.wisc.edu if (!sign_bit) { 12299010Snilay@cs.wisc.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit)); 12309010Snilay@cs.wisc.edu cfofBits = cfofBits & ~(ext & (CFBit)); 12319010Snilay@cs.wisc.edu ecfBit = ecfBit & ~(ext & ECFBit); 12329010Snilay@cs.wisc.edu ezfBit = ezfBit & ~(ext & EZFBit); 12339010Snilay@cs.wisc.edu } else { 12349010Snilay@cs.wisc.edu ccFlagBits = ccFlagBits | (ext & (ZFBit)); 12359010Snilay@cs.wisc.edu cfofBits = cfofBits | (ext & (CFBit)); 12369010Snilay@cs.wisc.edu ecfBit = ecfBit | (ext & ECFBit); 12379010Snilay@cs.wisc.edu ezfBit = ezfBit | (ext & EZFBit); 12389010Snilay@cs.wisc.edu } 12395239Sgblack@eecs.umich.edu ''' 12404714Sgblack@eecs.umich.edu 12415040Sgblack@eecs.umich.edu class Zext(RegOp): 12425927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 12437967Sgblack@eecs.umich.edu big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' 12445241Sgblack@eecs.umich.edu 12455926Sgblack@eecs.umich.edu class Rddr(RegOp): 12465926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12475926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 12486345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12497967Sgblack@eecs.umich.edu rdrCode = ''' 12505926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 12515926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 12525926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 12535926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 12545926Sgblack@eecs.umich.edu } else if (dr7.gd) { 12555926Sgblack@eecs.umich.edu fault = new DebugException(); 12565926Sgblack@eecs.umich.edu } else { 12577967Sgblack@eecs.umich.edu %s 12585926Sgblack@eecs.umich.edu } 12595926Sgblack@eecs.umich.edu ''' 12607967Sgblack@eecs.umich.edu code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" 12617967Sgblack@eecs.umich.edu big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" 12625926Sgblack@eecs.umich.edu 12635926Sgblack@eecs.umich.edu class Wrdr(RegOp): 12645926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12655926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 12666345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12675926Sgblack@eecs.umich.edu code = ''' 12685926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 12695926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 12705926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 12715926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 12726345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 12735926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 12745926Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12755926Sgblack@eecs.umich.edu } else if (dr7.gd) { 12765926Sgblack@eecs.umich.edu fault = new DebugException(); 12775926Sgblack@eecs.umich.edu } else { 12785926Sgblack@eecs.umich.edu DebugDest = psrc1; 12795926Sgblack@eecs.umich.edu } 12805926Sgblack@eecs.umich.edu ''' 12815926Sgblack@eecs.umich.edu 12825296Sgblack@eecs.umich.edu class Rdcr(RegOp): 12835296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12845296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 12856345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12867967Sgblack@eecs.umich.edu rdcrCode = ''' 12875924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 12885296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 12895296Sgblack@eecs.umich.edu } else { 12907967Sgblack@eecs.umich.edu %s 12915296Sgblack@eecs.umich.edu } 12925296Sgblack@eecs.umich.edu ''' 12937967Sgblack@eecs.umich.edu code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" 12947967Sgblack@eecs.umich.edu big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" 12955296Sgblack@eecs.umich.edu 12965241Sgblack@eecs.umich.edu class Wrcr(RegOp): 12975241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12985241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 12996345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13005241Sgblack@eecs.umich.edu code = ''' 13015241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 13025241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13035241Sgblack@eecs.umich.edu } else { 13045241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 13055241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 13065241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 13075241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 13085241Sgblack@eecs.umich.edu 13095241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 13105241Sgblack@eecs.umich.edu switch(dest) { 13115241Sgblack@eecs.umich.edu case 0: 13125241Sgblack@eecs.umich.edu { 13135241Sgblack@eecs.umich.edu Efer efer = EferOp; 13145241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 13155241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 13165241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 13175241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 13185241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 13195241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 13205241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13215241Sgblack@eecs.umich.edu } 13225241Sgblack@eecs.umich.edu break; 13235241Sgblack@eecs.umich.edu case 2: 13245241Sgblack@eecs.umich.edu break; 13255241Sgblack@eecs.umich.edu case 3: 13265241Sgblack@eecs.umich.edu break; 13275241Sgblack@eecs.umich.edu case 4: 13285241Sgblack@eecs.umich.edu { 13295241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 13305241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 13315241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 13325241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 13335241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13345241Sgblack@eecs.umich.edu } 13355241Sgblack@eecs.umich.edu break; 13365241Sgblack@eecs.umich.edu case 8: 13375241Sgblack@eecs.umich.edu { 13385241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 13395241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13405241Sgblack@eecs.umich.edu } 13415241Sgblack@eecs.umich.edu default: 13428857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 13438857Sgblack@eecs.umich.edu "Unrecognized control register %d.\\n", dest); 13445241Sgblack@eecs.umich.edu } 13455241Sgblack@eecs.umich.edu ControlDest = newVal; 13465241Sgblack@eecs.umich.edu } 13475241Sgblack@eecs.umich.edu ''' 13485290Sgblack@eecs.umich.edu 13495294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 13505672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 13515294Sgblack@eecs.umich.edu abstract = True 13525290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13535294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 13546345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13555294Sgblack@eecs.umich.edu 13565294Sgblack@eecs.umich.edu class Wrbase(SegOp): 13575290Sgblack@eecs.umich.edu code = ''' 13585294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 13595290Sgblack@eecs.umich.edu ''' 13605290Sgblack@eecs.umich.edu 13615294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 13625290Sgblack@eecs.umich.edu code = ''' 13635294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 13645294Sgblack@eecs.umich.edu ''' 13655294Sgblack@eecs.umich.edu 13665294Sgblack@eecs.umich.edu class Wrsel(SegOp): 13675294Sgblack@eecs.umich.edu code = ''' 13685294Sgblack@eecs.umich.edu SegSelDest = psrc1; 13695294Sgblack@eecs.umich.edu ''' 13705294Sgblack@eecs.umich.edu 13715905Sgblack@eecs.umich.edu class WrAttr(SegOp): 13725905Sgblack@eecs.umich.edu code = ''' 13735905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 13745905Sgblack@eecs.umich.edu ''' 13755905Sgblack@eecs.umich.edu 13765294Sgblack@eecs.umich.edu class Rdbase(SegOp): 13777967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' 13787967Sgblack@eecs.umich.edu big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' 13795294Sgblack@eecs.umich.edu 13805294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 13817967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' 13827967Sgblack@eecs.umich.edu big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' 13835294Sgblack@eecs.umich.edu 13845427Sgblack@eecs.umich.edu class RdAttr(SegOp): 13857967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' 13867967Sgblack@eecs.umich.edu big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' 13875427Sgblack@eecs.umich.edu 13885294Sgblack@eecs.umich.edu class Rdsel(SegOp): 13897967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' 13907967Sgblack@eecs.umich.edu big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' 13915294Sgblack@eecs.umich.edu 13925682Sgblack@eecs.umich.edu class Rdval(RegOp): 13935682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13946345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 13956345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13965682Sgblack@eecs.umich.edu code = ''' 13975682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 13985682Sgblack@eecs.umich.edu ''' 13995682Sgblack@eecs.umich.edu 14005682Sgblack@eecs.umich.edu class Wrval(RegOp): 14015682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14026345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 14036345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14045682Sgblack@eecs.umich.edu code = ''' 14055682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 14065682Sgblack@eecs.umich.edu ''' 14075682Sgblack@eecs.umich.edu 14085428Sgblack@eecs.umich.edu class Chks(RegOp): 14095428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 14105428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 14115428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 14125428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 14135294Sgblack@eecs.umich.edu code = ''' 14145424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 14155433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 14165433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 14175433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 14185294Sgblack@eecs.umich.edu 14195428Sgblack@eecs.umich.edu switch (imm8) 14205428Sgblack@eecs.umich.edu { 14215428Sgblack@eecs.umich.edu case SegNoCheck: 14225428Sgblack@eecs.umich.edu break; 14235428Sgblack@eecs.umich.edu case SegCSCheck: 14246060Sgblack@eecs.umich.edu // Make sure it's the right type 14256060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 14266060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14276060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 14286060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14296060Sgblack@eecs.umich.edu } 14305428Sgblack@eecs.umich.edu break; 14315428Sgblack@eecs.umich.edu case SegCallGateCheck: 14328857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault("CS checks for far " 14338857Sgblack@eecs.umich.edu "calls/jumps through call gates not implemented.\\n"); 14345428Sgblack@eecs.umich.edu break; 14355855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 14365853Sgblack@eecs.umich.edu // Check permissions. 14375674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 14385857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14396058Sgblack@eecs.umich.edu break; 14405674Sgblack@eecs.umich.edu } 14415855Sgblack@eecs.umich.edu // Fall through on purpose 14425855Sgblack@eecs.umich.edu case SegIntGateCheck: 14435853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 14445861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 14455853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 14465853Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14475853Sgblack@eecs.umich.edu } 14485674Sgblack@eecs.umich.edu break; 14495428Sgblack@eecs.umich.edu case SegSSCheck: 14505433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 14515433Sgblack@eecs.umich.edu if (!desc.p) { 14525857Sgblack@eecs.umich.edu fault = new StackFault(selector); 14538626Sgblack@eecs.umich.edu } else if (!(desc.s == 1 && desc.type.codeOrData == 0 && 14548626Sgblack@eecs.umich.edu desc.type.w) || 14555433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 14565433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 14575857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14585433Sgblack@eecs.umich.edu } 14598626Sgblack@eecs.umich.edu } else if (m5reg.submode != SixtyFourBitMode || 14608626Sgblack@eecs.umich.edu m5reg.cpl == 3) { 14618626Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14625433Sgblack@eecs.umich.edu } 14635428Sgblack@eecs.umich.edu break; 14645428Sgblack@eecs.umich.edu case SegIretCheck: 14655428Sgblack@eecs.umich.edu { 14665433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 14675433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 14685433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 14695433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 14705679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 14715857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14725679Sgblack@eecs.umich.edu } else if (!desc.p) { 14735857Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 14745679Sgblack@eecs.umich.edu } 14755428Sgblack@eecs.umich.edu break; 14765428Sgblack@eecs.umich.edu } 14775428Sgblack@eecs.umich.edu case SegIntCSCheck: 14785675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 14795675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 14805679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14815675Sgblack@eecs.umich.edu } 14825675Sgblack@eecs.umich.edu } else { 14838857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault("Interrupt CS " 14848857Sgblack@eecs.umich.edu "checks not implemented in legacy mode.\\n"); 14855675Sgblack@eecs.umich.edu } 14865428Sgblack@eecs.umich.edu break; 14875899Sgblack@eecs.umich.edu case SegTRCheck: 14885899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 14895899Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14905899Sgblack@eecs.umich.edu } 14915899Sgblack@eecs.umich.edu break; 14925900Sgblack@eecs.umich.edu case SegTSSCheck: 14935900Sgblack@eecs.umich.edu if (!desc.p) { 14945900Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 14955900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 14965900Sgblack@eecs.umich.edu (desc.type == 1 && 14975900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 14985935Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14995900Sgblack@eecs.umich.edu } 15005900Sgblack@eecs.umich.edu break; 15015936Sgblack@eecs.umich.edu case SegInGDTCheck: 15025936Sgblack@eecs.umich.edu if (selector.ti) { 15035936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15045936Sgblack@eecs.umich.edu } 15055936Sgblack@eecs.umich.edu break; 15065936Sgblack@eecs.umich.edu case SegLDTCheck: 15075936Sgblack@eecs.umich.edu if (!desc.p) { 15085936Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 15095936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 15105936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15115936Sgblack@eecs.umich.edu } 15125936Sgblack@eecs.umich.edu break; 15135428Sgblack@eecs.umich.edu default: 15148857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15158857Sgblack@eecs.umich.edu "Undefined segment check type.\\n"); 15165428Sgblack@eecs.umich.edu } 15175294Sgblack@eecs.umich.edu ''' 15185294Sgblack@eecs.umich.edu flag_code = ''' 15195294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 15209010Snilay@cs.wisc.edu ccFlagBits = ccFlagBits & ~(ext & ZFBit); 15219010Snilay@cs.wisc.edu ezfBit = ezfBit & ~(ext & EZFBit); 15229010Snilay@cs.wisc.edu 15239010Snilay@cs.wisc.edu if (!selector.si && !selector.ti) { 15249010Snilay@cs.wisc.edu ccFlagBits = ccFlagBits | (ext & ZFBit); 15259010Snilay@cs.wisc.edu ezfBit = ezfBit | (ext & EZFBit); 15269010Snilay@cs.wisc.edu } 15275294Sgblack@eecs.umich.edu ''' 15285294Sgblack@eecs.umich.edu 15295294Sgblack@eecs.umich.edu class Wrdh(RegOp): 15305294Sgblack@eecs.umich.edu code = ''' 15315678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 15325294Sgblack@eecs.umich.edu 15335678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 15345678Sgblack@eecs.umich.edu switch(desc.type) { 15355678Sgblack@eecs.umich.edu case LDT64: 15365678Sgblack@eecs.umich.edu case AvailableTSS64: 15375678Sgblack@eecs.umich.edu case BusyTSS64: 15385678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 15395678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 15405678Sgblack@eecs.umich.edu break; 15415678Sgblack@eecs.umich.edu case CallGate64: 15425678Sgblack@eecs.umich.edu case IntGate64: 15435678Sgblack@eecs.umich.edu case TrapGate64: 15445678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 15455678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 15465678Sgblack@eecs.umich.edu break; 15475678Sgblack@eecs.umich.edu default: 15488857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15498857Sgblack@eecs.umich.edu "Wrdh used with wrong descriptor type!\\n"); 15505678Sgblack@eecs.umich.edu } 15515678Sgblack@eecs.umich.edu DestReg = target; 15525294Sgblack@eecs.umich.edu ''' 15535294Sgblack@eecs.umich.edu 15545409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 15555409Sgblack@eecs.umich.edu code = ''' 15565409Sgblack@eecs.umich.edu TscOp = psrc1; 15575409Sgblack@eecs.umich.edu ''' 15585409Sgblack@eecs.umich.edu 15595409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 15605409Sgblack@eecs.umich.edu code = ''' 15615409Sgblack@eecs.umich.edu DestReg = TscOp; 15625409Sgblack@eecs.umich.edu ''' 15635409Sgblack@eecs.umich.edu 15645429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 15655429Sgblack@eecs.umich.edu code = ''' 15665429Sgblack@eecs.umich.edu DestReg = M5Reg; 15675429Sgblack@eecs.umich.edu ''' 15685429Sgblack@eecs.umich.edu 15695294Sgblack@eecs.umich.edu class Wrdl(RegOp): 15705294Sgblack@eecs.umich.edu code = ''' 15715294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 15725433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 15738857Sgblack@eecs.umich.edu // This while loop is so we can use break statements in the code 15748857Sgblack@eecs.umich.edu // below to skip the rest of this section without a bunch of 15758857Sgblack@eecs.umich.edu // nesting. 15768857Sgblack@eecs.umich.edu while (true) { 15778857Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 15788857Sgblack@eecs.umich.edu if (!desc.p) { 15798857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15808857Sgblack@eecs.umich.edu "Segment not present.\\n"); 15818857Sgblack@eecs.umich.edu break; 15825901Sgblack@eecs.umich.edu } 15838857Sgblack@eecs.umich.edu SegAttr attr = 0; 15848857Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 15858857Sgblack@eecs.umich.edu attr.unusable = 0; 15868857Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 15878857Sgblack@eecs.umich.edu attr.longMode = desc.l; 15888857Sgblack@eecs.umich.edu attr.avl = desc.avl; 15898857Sgblack@eecs.umich.edu attr.granularity = desc.g; 15908857Sgblack@eecs.umich.edu attr.present = desc.p; 15918857Sgblack@eecs.umich.edu attr.system = desc.s; 15928857Sgblack@eecs.umich.edu attr.type = desc.type; 15938857Sgblack@eecs.umich.edu if (!desc.s) { 15948857Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 15958857Sgblack@eecs.umich.edu if (desc.type.e) { 15968857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15978857Sgblack@eecs.umich.edu "Gate descriptor encountered.\\n"); 15988857Sgblack@eecs.umich.edu break; 15998857Sgblack@eecs.umich.edu } 16008857Sgblack@eecs.umich.edu attr.readable = 1; 16018857Sgblack@eecs.umich.edu attr.writable = 1; 16028857Sgblack@eecs.umich.edu attr.expandDown = 0; 16038857Sgblack@eecs.umich.edu } else { 16048857Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 16058857Sgblack@eecs.umich.edu attr.expandDown = 0; 16068857Sgblack@eecs.umich.edu attr.readable = desc.type.r; 16078857Sgblack@eecs.umich.edu attr.writable = 0; 16088857Sgblack@eecs.umich.edu } else { 16098857Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 16108857Sgblack@eecs.umich.edu attr.readable = 1; 16118857Sgblack@eecs.umich.edu attr.writable = desc.type.w; 16128857Sgblack@eecs.umich.edu } 16138857Sgblack@eecs.umich.edu } 16148857Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 16158857Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 16168857Sgblack@eecs.umich.edu if (desc.g) 16178857Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 16188857Sgblack@eecs.umich.edu SegBaseDest = base; 16198857Sgblack@eecs.umich.edu SegLimitDest = limit; 16208857Sgblack@eecs.umich.edu SegAttrDest = attr; 16215433Sgblack@eecs.umich.edu } else { 16228857Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 16238857Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 16248857Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 16255433Sgblack@eecs.umich.edu } 16268857Sgblack@eecs.umich.edu break; 16275294Sgblack@eecs.umich.edu } 16285290Sgblack@eecs.umich.edu ''' 16294519Sgblack@eecs.umich.edu}}; 1630