regop.isa revision 8588
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 124519Sgblack@eecs.umich.edu// 137087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 147087Snate@binkert.org// modification, are permitted provided that the following conditions are 157087Snate@binkert.org// met: redistributions of source code must retain the above copyright 167087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org// documentation and/or other materials provided with the distribution; 207087Snate@binkert.org// neither the name of the copyright holders nor the names of its 214519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227087Snate@binkert.org// this software without specific prior written permission. 234519Sgblack@eecs.umich.edu// 244519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354519Sgblack@eecs.umich.edu// 364519Sgblack@eecs.umich.edu// Authors: Gabe Black 374519Sgblack@eecs.umich.edu 384519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 394519Sgblack@eecs.umich.edu// 404519Sgblack@eecs.umich.edu// RegOp Microop templates 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 434519Sgblack@eecs.umich.edu 444519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 454519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 464519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474519Sgblack@eecs.umich.edu { 484519Sgblack@eecs.umich.edu Fault fault = NoFault; 494519Sgblack@eecs.umich.edu 504809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 514519Sgblack@eecs.umich.edu %(op_decl)s; 524519Sgblack@eecs.umich.edu %(op_rd)s; 534688Sgblack@eecs.umich.edu 547969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 557969Sgblack@eecs.umich.edu 564688Sgblack@eecs.umich.edu if(%(cond_check)s) 574688Sgblack@eecs.umich.edu { 584688Sgblack@eecs.umich.edu %(code)s; 594688Sgblack@eecs.umich.edu %(flag_code)s; 604688Sgblack@eecs.umich.edu } 614708Sgblack@eecs.umich.edu else 624708Sgblack@eecs.umich.edu { 634708Sgblack@eecs.umich.edu %(else_code)s; 644708Sgblack@eecs.umich.edu } 654519Sgblack@eecs.umich.edu 664519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 674519Sgblack@eecs.umich.edu if(fault == NoFault) 684519Sgblack@eecs.umich.edu { 694519Sgblack@eecs.umich.edu %(op_wb)s; 704519Sgblack@eecs.umich.edu } 714519Sgblack@eecs.umich.edu return fault; 724519Sgblack@eecs.umich.edu } 734519Sgblack@eecs.umich.edu}}; 744519Sgblack@eecs.umich.edu 754519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 764951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 774519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 784519Sgblack@eecs.umich.edu { 794519Sgblack@eecs.umich.edu Fault fault = NoFault; 804519Sgblack@eecs.umich.edu 814519Sgblack@eecs.umich.edu %(op_decl)s; 824519Sgblack@eecs.umich.edu %(op_rd)s; 834688Sgblack@eecs.umich.edu 847969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 857969Sgblack@eecs.umich.edu 864688Sgblack@eecs.umich.edu if(%(cond_check)s) 874688Sgblack@eecs.umich.edu { 884688Sgblack@eecs.umich.edu %(code)s; 894688Sgblack@eecs.umich.edu %(flag_code)s; 904688Sgblack@eecs.umich.edu } 914708Sgblack@eecs.umich.edu else 924708Sgblack@eecs.umich.edu { 934708Sgblack@eecs.umich.edu %(else_code)s; 944708Sgblack@eecs.umich.edu } 954519Sgblack@eecs.umich.edu 964519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 974519Sgblack@eecs.umich.edu if(fault == NoFault) 984519Sgblack@eecs.umich.edu { 994519Sgblack@eecs.umich.edu %(op_wb)s; 1004519Sgblack@eecs.umich.edu } 1014519Sgblack@eecs.umich.edu return fault; 1024519Sgblack@eecs.umich.edu } 1034519Sgblack@eecs.umich.edu}}; 1044519Sgblack@eecs.umich.edu 1054519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1064519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1074519Sgblack@eecs.umich.edu { 1084519Sgblack@eecs.umich.edu public: 1094519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1107620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1116345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1124712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1134519Sgblack@eecs.umich.edu 1144519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1154519Sgblack@eecs.umich.edu }; 1164519Sgblack@eecs.umich.edu}}; 1174519Sgblack@eecs.umich.edu 1184519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1194519Sgblack@eecs.umich.edu 1204951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu public: 1234951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1247620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1256646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1264712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1274519Sgblack@eecs.umich.edu 1284519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1294519Sgblack@eecs.umich.edu }; 1304519Sgblack@eecs.umich.edu}}; 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1334519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1347620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1356345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1364712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1377620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1384688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1394581Sgblack@eecs.umich.edu %(op_class)s) 1404519Sgblack@eecs.umich.edu { 1417626Sgblack@eecs.umich.edu %(constructor)s; 1427894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1434519Sgblack@eecs.umich.edu } 1444519Sgblack@eecs.umich.edu}}; 1454519Sgblack@eecs.umich.edu 1464519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1474951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1487620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1496646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1504712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1517620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1524688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 1534581Sgblack@eecs.umich.edu %(op_class)s) 1544519Sgblack@eecs.umich.edu { 1557626Sgblack@eecs.umich.edu %(constructor)s; 1567894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1574519Sgblack@eecs.umich.edu } 1584519Sgblack@eecs.umich.edu}}; 1594519Sgblack@eecs.umich.edu 1605075Sgblack@eecs.umich.eduoutput header {{ 1615075Sgblack@eecs.umich.edu void 1625075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1635075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 1645428Sgblack@eecs.umich.edu 1655428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 1665674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 1675899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 1685936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 1695428Sgblack@eecs.umich.edu }; 1705678Sgblack@eecs.umich.edu 1715678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 1725678Sgblack@eecs.umich.edu LDT64 = 2, 1735678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 1745678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 1755678Sgblack@eecs.umich.edu CallGate64 = 0xc, 1765678Sgblack@eecs.umich.edu IntGate64 = 0xe, 1775678Sgblack@eecs.umich.edu TrapGate64 = 0xf 1785678Sgblack@eecs.umich.edu }; 1795075Sgblack@eecs.umich.edu}}; 1805075Sgblack@eecs.umich.edu 1815075Sgblack@eecs.umich.eduoutput decoder {{ 1825075Sgblack@eecs.umich.edu void 1835075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1845075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 1855075Sgblack@eecs.umich.edu { 1865075Sgblack@eecs.umich.edu //Check for divide by zero. 1877719Sgblack@eecs.umich.edu assert(divisor != 0); 1885075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 1895075Sgblack@eecs.umich.edu if (divisor <= dividend) { 1905075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 1915075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 1925075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 1935075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 1945075Sgblack@eecs.umich.edu divisor <<= shift; 1955075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 1965075Sgblack@eecs.umich.edu //now larger than the dividend. 1975075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 1985075Sgblack@eecs.umich.edu quotientBit <<= shift; 1995075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2005075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2015075Sgblack@eecs.umich.edu //part of one or two bit division. 2025075Sgblack@eecs.umich.edu if (divisor > dividend) { 2035075Sgblack@eecs.umich.edu quotientBit >>= 1; 2045075Sgblack@eecs.umich.edu divisor >>= 1; 2055075Sgblack@eecs.umich.edu } 2065075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2075075Sgblack@eecs.umich.edu quotient += quotientBit; 2085075Sgblack@eecs.umich.edu remainder -= divisor; 2095075Sgblack@eecs.umich.edu } 2105075Sgblack@eecs.umich.edu } 2115075Sgblack@eecs.umich.edu}}; 2125075Sgblack@eecs.umich.edu 2134519Sgblack@eecs.umich.edulet {{ 2145040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2155040Sgblack@eecs.umich.edu # them will always work. 2165040Sgblack@eecs.umich.edu header_output = "" 2175040Sgblack@eecs.umich.edu decoder_output = "" 2185040Sgblack@eecs.umich.edu exec_output = "" 2195040Sgblack@eecs.umich.edu 2205040Sgblack@eecs.umich.edu immTemplates = ( 2215040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2225040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2235040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2245040Sgblack@eecs.umich.edu 2255040Sgblack@eecs.umich.edu regTemplates = ( 2265040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2275040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2285040Sgblack@eecs.umich.edu MicroRegOpExecute) 2295040Sgblack@eecs.umich.edu 2305040Sgblack@eecs.umich.edu class RegOpMeta(type): 2317967Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, code, big_code, \ 2327967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, cond_control_flag_init): 2335040Sgblack@eecs.umich.edu 2345040Sgblack@eecs.umich.edu # Globals to stick the output in 2355040Sgblack@eecs.umich.edu global header_output 2365040Sgblack@eecs.umich.edu global decoder_output 2375040Sgblack@eecs.umich.edu global exec_output 2385040Sgblack@eecs.umich.edu 2395040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2407894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 2417894SBrad.Beckmann@amd.com cond_control_flag_init)) 2427967Sgblack@eecs.umich.edu allBigCode = "|".join((big_code, flag_code, cond_check, else_code, 2437967Sgblack@eecs.umich.edu cond_control_flag_init)) 2445040Sgblack@eecs.umich.edu 2455040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2465040Sgblack@eecs.umich.edu # of this code. 2478588Sgblack@eecs.umich.edu matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?") 2487967Sgblack@eecs.umich.edu match = matcher.search(allCode + allBigCode) 2495062Sgblack@eecs.umich.edu if match: 2505062Sgblack@eecs.umich.edu typeQual = "" 2515062Sgblack@eecs.umich.edu if match.group("typeQual"): 2525062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 2535062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 2545040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2555062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 2567967Sgblack@eecs.umich.edu matcher.sub(src2_name, big_code), 2575062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 2585062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 2597894SBrad.Beckmann@amd.com matcher.sub(src2_name, else_code), 2607894SBrad.Beckmann@amd.com matcher.sub(src2_name, cond_control_flag_init)) 2616647Sgblack@eecs.umich.edu imm_name = "%simm8" % match.group("prefix") 2625040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 2636647Sgblack@eecs.umich.edu matcher.sub(imm_name, code), 2647967Sgblack@eecs.umich.edu matcher.sub(imm_name, big_code), 2656647Sgblack@eecs.umich.edu matcher.sub(imm_name, flag_code), 2666647Sgblack@eecs.umich.edu matcher.sub(imm_name, cond_check), 2677894SBrad.Beckmann@amd.com matcher.sub(imm_name, else_code), 2687894SBrad.Beckmann@amd.com matcher.sub(imm_name, cond_control_flag_init)) 2695040Sgblack@eecs.umich.edu return 2705040Sgblack@eecs.umich.edu 2715040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 2725040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 2735239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 2745040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2757967Sgblack@eecs.umich.edu code, big_code, "", "true", else_code, "") 2765040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 2775040Sgblack@eecs.umich.edu 2785040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 2795040Sgblack@eecs.umich.edu # compute it. 2807967Sgblack@eecs.umich.edu for (big, all) in ((False, allCode), (True, allBigCode)): 2817967Sgblack@eecs.umich.edu prefix = "" 2827967Sgblack@eecs.umich.edu for (rex, decl) in ( 2837967Sgblack@eecs.umich.edu ("(?<!\w)psrc1(?!\w)", 2847967Sgblack@eecs.umich.edu "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"), 2857967Sgblack@eecs.umich.edu ("(?<!\w)psrc2(?!\w)", 2867967Sgblack@eecs.umich.edu "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"), 2877967Sgblack@eecs.umich.edu ("(?<!\w)spsrc1(?!\w)", 2887967Sgblack@eecs.umich.edu "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"), 2897967Sgblack@eecs.umich.edu ("(?<!\w)spsrc2(?!\w)", 2907967Sgblack@eecs.umich.edu "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"), 2917967Sgblack@eecs.umich.edu ("(?<!\w)simm8(?!\w)", 2927967Sgblack@eecs.umich.edu "int8_t simm8 = imm8;")): 2937967Sgblack@eecs.umich.edu matcher = re.compile(rex) 2947967Sgblack@eecs.umich.edu if matcher.search(all): 2957967Sgblack@eecs.umich.edu prefix += decl + "\n" 2967967Sgblack@eecs.umich.edu if big: 2977967Sgblack@eecs.umich.edu if big_code != "": 2987967Sgblack@eecs.umich.edu big_code = prefix + big_code 2997967Sgblack@eecs.umich.edu else: 3007967Sgblack@eecs.umich.edu code = prefix + code 3015040Sgblack@eecs.umich.edu 3025040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3035040Sgblack@eecs.umich.edu 3045040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3055040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3065040Sgblack@eecs.umich.edu templates = regTemplates 3076647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3085040Sgblack@eecs.umich.edu if matcher.search(allCode): 3095040Sgblack@eecs.umich.edu base += "Imm" 3105040Sgblack@eecs.umich.edu templates = immTemplates 3115040Sgblack@eecs.umich.edu 3125040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3137967Sgblack@eecs.umich.edu iops = [InstObjParams(name, Name + suffix, base, 3145040Sgblack@eecs.umich.edu {"code" : code, 3155040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3165040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3177894SBrad.Beckmann@amd.com "else_code" : else_code, 3187967Sgblack@eecs.umich.edu "cond_control_flag_init" : cond_control_flag_init})] 3197967Sgblack@eecs.umich.edu if big_code != "": 3207967Sgblack@eecs.umich.edu iops += [InstObjParams(name, Name + suffix + "Big", base, 3217967Sgblack@eecs.umich.edu {"code" : big_code, 3227967Sgblack@eecs.umich.edu "flag_code" : flag_code, 3237967Sgblack@eecs.umich.edu "cond_check" : cond_check, 3247967Sgblack@eecs.umich.edu "else_code" : else_code, 3257967Sgblack@eecs.umich.edu "cond_control_flag_init" : 3267967Sgblack@eecs.umich.edu cond_control_flag_init})] 3275040Sgblack@eecs.umich.edu 3285040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3297967Sgblack@eecs.umich.edu for iop in iops: 3307967Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3317967Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3327967Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3335040Sgblack@eecs.umich.edu 3345040Sgblack@eecs.umich.edu 3355040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3364688Sgblack@eecs.umich.edu abstract = False 3375040Sgblack@eecs.umich.edu name = Name.lower() 3384688Sgblack@eecs.umich.edu if "abstract" in dict: 3394688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3404688Sgblack@eecs.umich.edu del dict['abstract'] 3414688Sgblack@eecs.umich.edu 3425040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3434688Sgblack@eecs.umich.edu if not abstract: 3445040Sgblack@eecs.umich.edu cls.className = Name 3455040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3465040Sgblack@eecs.umich.edu code = cls.code 3477967Sgblack@eecs.umich.edu big_code = cls.big_code 3485040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3495040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3505040Sgblack@eecs.umich.edu else_code = cls.else_code 3517894SBrad.Beckmann@amd.com cond_control_flag_init = cls.cond_control_flag_init 3525040Sgblack@eecs.umich.edu 3535040Sgblack@eecs.umich.edu # Set up the C++ classes 3547967Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", code, big_code, 3557967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, 3567967Sgblack@eecs.umich.edu cond_control_flag_init) 3575040Sgblack@eecs.umich.edu 3585040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3595040Sgblack@eecs.umich.edu global microopClasses 3605040Sgblack@eecs.umich.edu microopClasses[name] = cls 3615040Sgblack@eecs.umich.edu 3627894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 3637894SBrad.Beckmann@amd.com cond_control_flag_init)) 3645040Sgblack@eecs.umich.edu 3655040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3665040Sgblack@eecs.umich.edu # of this code. 3678588Sgblack@eecs.umich.edu matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?") 3685040Sgblack@eecs.umich.edu if matcher.search(allCode): 3695040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3704688Sgblack@eecs.umich.edu return cls 3714688Sgblack@eecs.umich.edu 3725040Sgblack@eecs.umich.edu 3735040Sgblack@eecs.umich.edu class RegOp(X86Microop): 3745040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 3755040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 3764688Sgblack@eecs.umich.edu abstract = True 3774688Sgblack@eecs.umich.edu 3785040Sgblack@eecs.umich.edu # Default template parameter values 3797967Sgblack@eecs.umich.edu big_code = "" 3805040Sgblack@eecs.umich.edu flag_code = "" 3815040Sgblack@eecs.umich.edu cond_check = "true" 3825040Sgblack@eecs.umich.edu else_code = ";" 3837894SBrad.Beckmann@amd.com cond_control_flag_init = "" 3845040Sgblack@eecs.umich.edu 3855040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 3864519Sgblack@eecs.umich.edu self.dest = dest 3874519Sgblack@eecs.umich.edu self.src1 = src1 3885040Sgblack@eecs.umich.edu self.op2 = op2 3894688Sgblack@eecs.umich.edu self.flags = flags 3904701Sgblack@eecs.umich.edu self.dataSize = dataSize 3914688Sgblack@eecs.umich.edu if flags is None: 3924688Sgblack@eecs.umich.edu self.ext = 0 3934688Sgblack@eecs.umich.edu else: 3944688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 3954688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 3964688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 3974688Sgblack@eecs.umich.edu self.className += "Flags" 3984519Sgblack@eecs.umich.edu 3997620Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 4007967Sgblack@eecs.umich.edu if self.big_code != "": 4017967Sgblack@eecs.umich.edu className = self.className 4027967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4037967Sgblack@eecs.umich.edu className += "Imm" 4047967Sgblack@eecs.umich.edu allocString = ''' 4057967Sgblack@eecs.umich.edu (%(dataSize)s >= 4) ? 4067967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)sBig(machInst, 4077967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4087967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) : 4097967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)s(machInst, 4107967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4117967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) 4127967Sgblack@eecs.umich.edu ''' 4137967Sgblack@eecs.umich.edu allocator = allocString % { 4147967Sgblack@eecs.umich.edu "class_name" : className, 4157967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4167967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4177967Sgblack@eecs.umich.edu "dest" : self.dest, 4187967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4197967Sgblack@eecs.umich.edu "ext" : self.ext} 4207967Sgblack@eecs.umich.edu return allocator 4217967Sgblack@eecs.umich.edu else: 4227967Sgblack@eecs.umich.edu className = self.className 4237967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4247967Sgblack@eecs.umich.edu className += "Imm" 4257967Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 4267967Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4277967Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4287967Sgblack@eecs.umich.edu "class_name" : className, 4297967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4307967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4317967Sgblack@eecs.umich.edu "dest" : self.dest, 4327967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4337967Sgblack@eecs.umich.edu "ext" : self.ext} 4347967Sgblack@eecs.umich.edu return allocator 4354519Sgblack@eecs.umich.edu 4365040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4374688Sgblack@eecs.umich.edu abstract = True 4385040Sgblack@eecs.umich.edu flag_code = ''' 4395040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4405115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4417969Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2); 4425040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4435040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 4445115Sgblack@eecs.umich.edu ccFlagBits &= ~(ECFBit & ext); 4455040Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 4465040Sgblack@eecs.umich.edu ''' 4474519Sgblack@eecs.umich.edu 4485040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4495040Sgblack@eecs.umich.edu abstract = True 4505040Sgblack@eecs.umich.edu flag_code = \ 4517969Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);" 4524519Sgblack@eecs.umich.edu 4535040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4545040Sgblack@eecs.umich.edu abstract = True 4555040Sgblack@eecs.umich.edu flag_code = \ 4567969Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);" 4574519Sgblack@eecs.umich.edu 4585040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4595040Sgblack@eecs.umich.edu abstract = True 4605083Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits, ext)" 4617894SBrad.Beckmann@amd.com cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];" 4624519Sgblack@eecs.umich.edu 4635063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4645063Sgblack@eecs.umich.edu abstract = True 4655063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4665063Sgblack@eecs.umich.edu if not src1: 4675063Sgblack@eecs.umich.edu src1 = dest 4686345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4696345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4705063Sgblack@eecs.umich.edu 4715063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4725063Sgblack@eecs.umich.edu abstract = True 4735063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4746345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4756345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 4765063Sgblack@eecs.umich.edu 4775040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4787969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' 4797969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' 4804595Sgblack@eecs.umich.edu 4815040Sgblack@eecs.umich.edu class Or(LogicRegOp): 4827969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' 4837969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' 4844595Sgblack@eecs.umich.edu 4855040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 4865040Sgblack@eecs.umich.edu code = ''' 4874732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4887969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); 4895040Sgblack@eecs.umich.edu ''' 4907967Sgblack@eecs.umich.edu big_code = ''' 4917967Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4927969Sgblack@eecs.umich.edu DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); 4937967Sgblack@eecs.umich.edu ''' 4945040Sgblack@eecs.umich.edu 4955040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 4965040Sgblack@eecs.umich.edu code = ''' 4974732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4987969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); 4995040Sgblack@eecs.umich.edu ''' 5007967Sgblack@eecs.umich.edu big_code = ''' 5017967Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5027969Sgblack@eecs.umich.edu DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); 5037967Sgblack@eecs.umich.edu ''' 5045040Sgblack@eecs.umich.edu 5055040Sgblack@eecs.umich.edu class And(LogicRegOp): 5067969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' 5077969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' 5085040Sgblack@eecs.umich.edu 5095040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5107969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' 5117969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' 5125040Sgblack@eecs.umich.edu 5135040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5147969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' 5157969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)' 5165040Sgblack@eecs.umich.edu 5175063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5185040Sgblack@eecs.umich.edu code = ''' 5195063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5205063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5216742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5226430Sgblack@eecs.umich.edu uint64_t hiResult; 5236430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5246430Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5256461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5266430Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5276430Sgblack@eecs.umich.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5286430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 5296430Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5306462Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 5316430Sgblack@eecs.umich.edu hiResult -= op2; 5326462Sgblack@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 5336430Sgblack@eecs.umich.edu hiResult -= psrc1; 5346430Sgblack@eecs.umich.edu ProdHi = hiResult; 5355040Sgblack@eecs.umich.edu ''' 5366463Sgblack@eecs.umich.edu flag_code = ''' 5376463Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 5386463Sgblack@eecs.umich.edu bits(ProdLow, dataSize * 8 - 1)) { 5396463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5406463Sgblack@eecs.umich.edu } else { 5416463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5426463Sgblack@eecs.umich.edu } 5436463Sgblack@eecs.umich.edu ''' 5445040Sgblack@eecs.umich.edu 5455063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5465040Sgblack@eecs.umich.edu code = ''' 5475063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5484809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5496742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5506430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5515063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5526461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5535063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5545063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5556430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) / shifter) + 5565063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5575040Sgblack@eecs.umich.edu ''' 5586463Sgblack@eecs.umich.edu flag_code = ''' 5596463Sgblack@eecs.umich.edu if (ProdHi) { 5606463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5616463Sgblack@eecs.umich.edu } else { 5626463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5636463Sgblack@eecs.umich.edu } 5646463Sgblack@eecs.umich.edu ''' 5655040Sgblack@eecs.umich.edu 5665063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5675063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5687967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdLow & mask(dataSize * 8);' 5695040Sgblack@eecs.umich.edu 5705063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5715063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5725063Sgblack@eecs.umich.edu if not src1: 5735063Sgblack@eecs.umich.edu src1 = dest 5746345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 5756345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 5765063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5777967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdHi & mask(dataSize * 8);' 5785062Sgblack@eecs.umich.edu 5795075Sgblack@eecs.umich.edu # One or two bit divide 5805075Sgblack@eecs.umich.edu class Div1(WrRegOp): 5815040Sgblack@eecs.umich.edu code = ''' 5825075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 5835075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5845075Sgblack@eecs.umich.edu uint64_t quotient = 0; 5855075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 5865075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 5875075Sgblack@eecs.umich.edu //a source. 5885075Sgblack@eecs.umich.edu uint64_t divisor = op2; 5895075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 5905075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 5915075Sgblack@eecs.umich.edu //Do the division. 5927719Sgblack@eecs.umich.edu if (divisor == 0) { 5937719Sgblack@eecs.umich.edu fault = new DivideByZero; 5947719Sgblack@eecs.umich.edu } else { 5957719Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5967719Sgblack@eecs.umich.edu //Record the final results. 5977719Sgblack@eecs.umich.edu Remainder = remainder; 5987719Sgblack@eecs.umich.edu Quotient = quotient; 5997719Sgblack@eecs.umich.edu Divisor = divisor; 6007719Sgblack@eecs.umich.edu } 6015040Sgblack@eecs.umich.edu ''' 6024823Sgblack@eecs.umich.edu 6035075Sgblack@eecs.umich.edu # Step divide 6045075Sgblack@eecs.umich.edu class Div2(RegOp): 6057967Sgblack@eecs.umich.edu divCode = ''' 6065075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 6075075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 6085075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 6095075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 6105075Sgblack@eecs.umich.edu int remaining = op2; 6115075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 6125075Sgblack@eecs.umich.edu //little. 6137719Sgblack@eecs.umich.edu if (divisor == 0) { 6147719Sgblack@eecs.umich.edu fault = new DivideByZero; 6157719Sgblack@eecs.umich.edu } else if (remaining) { 6167070Sgblack@eecs.umich.edu if (divisor & (ULL(1) << 63)) { 6177070Sgblack@eecs.umich.edu while (remaining && !(dividend & (ULL(1) << 63))) { 6187070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6197070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6207070Sgblack@eecs.umich.edu quotient <<= 1; 6217070Sgblack@eecs.umich.edu remaining--; 6227070Sgblack@eecs.umich.edu } 6237070Sgblack@eecs.umich.edu if (dividend & (ULL(1) << 63)) { 6247080Sgblack@eecs.umich.edu bool highBit = false; 6257070Sgblack@eecs.umich.edu if (dividend < divisor && remaining) { 6267080Sgblack@eecs.umich.edu highBit = true; 6277070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6287070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6297070Sgblack@eecs.umich.edu quotient <<= 1; 6307070Sgblack@eecs.umich.edu remaining--; 6317070Sgblack@eecs.umich.edu } 6327080Sgblack@eecs.umich.edu if (highBit || divisor <= dividend) { 6337080Sgblack@eecs.umich.edu quotient++; 6347080Sgblack@eecs.umich.edu dividend -= divisor; 6357080Sgblack@eecs.umich.edu } 6367070Sgblack@eecs.umich.edu } 6377070Sgblack@eecs.umich.edu remainder = dividend; 6387070Sgblack@eecs.umich.edu } else { 6397070Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 6407070Sgblack@eecs.umich.edu while (dividend < divisor && remaining) { 6417070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6427070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6437070Sgblack@eecs.umich.edu quotient <<= 1; 6447070Sgblack@eecs.umich.edu remaining--; 6457070Sgblack@eecs.umich.edu } 6467070Sgblack@eecs.umich.edu remainder = dividend; 6477070Sgblack@eecs.umich.edu //Do the division. 6487070Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6495075Sgblack@eecs.umich.edu } 6505075Sgblack@eecs.umich.edu } 6515075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 6527967Sgblack@eecs.umich.edu %s 6535075Sgblack@eecs.umich.edu //Record the final results 6545075Sgblack@eecs.umich.edu Remainder = remainder; 6555075Sgblack@eecs.umich.edu Quotient = quotient; 6565075Sgblack@eecs.umich.edu ''' 6577967Sgblack@eecs.umich.edu code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" 6587967Sgblack@eecs.umich.edu big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" 6595075Sgblack@eecs.umich.edu flag_code = ''' 6607480Sgblack@eecs.umich.edu if (remaining == 0) 6615075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & EZFBit); 6625075Sgblack@eecs.umich.edu else 6635075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6645075Sgblack@eecs.umich.edu ''' 6654732Sgblack@eecs.umich.edu 6665075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6675075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6687967Sgblack@eecs.umich.edu big_code = 'DestReg = Quotient & mask(dataSize * 8);' 6695075Sgblack@eecs.umich.edu 6705075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6715075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6727967Sgblack@eecs.umich.edu big_code = 'DestReg = Remainder & mask(dataSize * 8);' 6735040Sgblack@eecs.umich.edu 6745040Sgblack@eecs.umich.edu class Mov(CondRegOp): 6755040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6766482Sgblack@eecs.umich.edu else_code = 'DestReg = DestReg;' 6775040Sgblack@eecs.umich.edu 6784732Sgblack@eecs.umich.edu # Shift instructions 6795040Sgblack@eecs.umich.edu 6805076Sgblack@eecs.umich.edu class Sll(RegOp): 6815040Sgblack@eecs.umich.edu code = ''' 6824756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6834823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6845040Sgblack@eecs.umich.edu ''' 6857967Sgblack@eecs.umich.edu big_code = ''' 6867967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6877967Sgblack@eecs.umich.edu DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); 6887967Sgblack@eecs.umich.edu ''' 6895076Sgblack@eecs.umich.edu flag_code = ''' 6905076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6915076Sgblack@eecs.umich.edu if (shiftAmt) { 6925076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6935076Sgblack@eecs.umich.edu //worry about setting them. 6945076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6955076Sgblack@eecs.umich.edu int CFBits = 0; 6965076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 6976441Sgblack@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 6986441Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 6995076Sgblack@eecs.umich.edu CFBits = 1; 7006441Sgblack@eecs.umich.edu } 7015076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7025076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 7035076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7045076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7055076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 7065076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7075076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7085076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7095076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7105076Sgblack@eecs.umich.edu } 7115076Sgblack@eecs.umich.edu ''' 7125040Sgblack@eecs.umich.edu 7135076Sgblack@eecs.umich.edu class Srl(RegOp): 7147967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 7157967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to mask them out 7167967Sgblack@eecs.umich.edu # to be sure they're zero. 7175040Sgblack@eecs.umich.edu code = ''' 7184756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7194732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7204823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 7215040Sgblack@eecs.umich.edu ''' 7227967Sgblack@eecs.umich.edu big_code = ''' 7237967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7247967Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7257967Sgblack@eecs.umich.edu DestReg = (psrc1 >> shiftAmt) & logicalMask; 7267967Sgblack@eecs.umich.edu ''' 7275076Sgblack@eecs.umich.edu flag_code = ''' 7285076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7295076Sgblack@eecs.umich.edu if (shiftAmt) { 7305076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7315076Sgblack@eecs.umich.edu //worry about setting them. 7325076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7335076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7346442Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7356442Sgblack@eecs.umich.edu shiftAmt <= dataSize * 8 && 7366442Sgblack@eecs.umich.edu bits(SrcReg1, shiftAmt - 1)) { 7375076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7386442Sgblack@eecs.umich.edu } 7395076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7405076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 7415076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7425076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7435076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7445076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7455076Sgblack@eecs.umich.edu } 7465076Sgblack@eecs.umich.edu ''' 7475040Sgblack@eecs.umich.edu 7485076Sgblack@eecs.umich.edu class Sra(RegOp): 7497967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 7507967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to sign extend 7517967Sgblack@eecs.umich.edu # them manually to be sure. 7525040Sgblack@eecs.umich.edu code = ''' 7534756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7546443Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 7555032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 7564823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 7575040Sgblack@eecs.umich.edu ''' 7587967Sgblack@eecs.umich.edu big_code = ''' 7597967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7607967Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 7617967Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 7627967Sgblack@eecs.umich.edu DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); 7637967Sgblack@eecs.umich.edu ''' 7645076Sgblack@eecs.umich.edu flag_code = ''' 7655076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7665076Sgblack@eecs.umich.edu if (shiftAmt) { 7675076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7685076Sgblack@eecs.umich.edu //worry about setting them. 7695076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7705076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7716444Sgblack@eecs.umich.edu uint8_t effectiveShift = 7726444Sgblack@eecs.umich.edu (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 7736444Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7746444Sgblack@eecs.umich.edu bits(SrcReg1, effectiveShift - 1)) { 7755076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7766444Sgblack@eecs.umich.edu } 7775076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7785076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7795076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7805076Sgblack@eecs.umich.edu } 7815076Sgblack@eecs.umich.edu ''' 7825040Sgblack@eecs.umich.edu 7835076Sgblack@eecs.umich.edu class Ror(RegOp): 7845040Sgblack@eecs.umich.edu code = ''' 7854732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7864756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7876449Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 7887967Sgblack@eecs.umich.edu if (realShiftAmt) { 7896449Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 7906449Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 7914732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7927967Sgblack@eecs.umich.edu } else 7936447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 7945040Sgblack@eecs.umich.edu ''' 7955076Sgblack@eecs.umich.edu flag_code = ''' 7965076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7975076Sgblack@eecs.umich.edu if (shiftAmt) { 7985076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7995076Sgblack@eecs.umich.edu //worry about setting them. 8005076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8015076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 8025076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8035076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 8045076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8055076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && msb) 8065076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8075076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8085076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 8095076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8105076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8115076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8125076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8135076Sgblack@eecs.umich.edu } 8145076Sgblack@eecs.umich.edu ''' 8155040Sgblack@eecs.umich.edu 8165076Sgblack@eecs.umich.edu class Rcr(RegOp): 8175040Sgblack@eecs.umich.edu code = ''' 8184733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8194756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8206454Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 8217967Sgblack@eecs.umich.edu if (realShiftAmt) { 8224733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8236454Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 8246454Sgblack@eecs.umich.edu if (realShiftAmt > 1) 8256454Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 8266454Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 8274733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8287967Sgblack@eecs.umich.edu } else 8296447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8305040Sgblack@eecs.umich.edu ''' 8315076Sgblack@eecs.umich.edu flag_code = ''' 8325076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8335076Sgblack@eecs.umich.edu if (shiftAmt) { 8346453Sgblack@eecs.umich.edu int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 8355076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8365076Sgblack@eecs.umich.edu //worry about setting them. 8375076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8385076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8396453Sgblack@eecs.umich.edu if ((ext & OFBit) && (origCFBit ^ 8406453Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) { 8415076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8426453Sgblack@eecs.umich.edu } 8435076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8446454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8456454Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : 8466454Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) { 8475076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8486454Sgblack@eecs.umich.edu } 8495076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8505076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8515076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8525076Sgblack@eecs.umich.edu } 8535076Sgblack@eecs.umich.edu ''' 8545040Sgblack@eecs.umich.edu 8555076Sgblack@eecs.umich.edu class Rol(RegOp): 8565040Sgblack@eecs.umich.edu code = ''' 8574732Sgblack@eecs.umich.edu uint8_t shiftAmt = 8584756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8596446Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 8607967Sgblack@eecs.umich.edu if (realShiftAmt) { 8616446Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 8624732Sgblack@eecs.umich.edu uint64_t bottom = 8636446Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 8644732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8657967Sgblack@eecs.umich.edu } else 8666447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8675040Sgblack@eecs.umich.edu ''' 8685076Sgblack@eecs.umich.edu flag_code = ''' 8695076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8705076Sgblack@eecs.umich.edu if (shiftAmt) { 8715076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8725076Sgblack@eecs.umich.edu //worry about setting them. 8735076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8745076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 8755076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 8765076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8775076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8785076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && lsb) 8795076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8805076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8815076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 8825076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8835076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8845076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8855076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8865076Sgblack@eecs.umich.edu } 8875076Sgblack@eecs.umich.edu ''' 8885040Sgblack@eecs.umich.edu 8895076Sgblack@eecs.umich.edu class Rcl(RegOp): 8905040Sgblack@eecs.umich.edu code = ''' 8914733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8924756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8936456Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 8947967Sgblack@eecs.umich.edu if (realShiftAmt) { 8954733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8966456Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 8976456Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (realShiftAmt - 1); 8984733Sgblack@eecs.umich.edu if(shiftAmt > 1) 8994733Sgblack@eecs.umich.edu bottom |= 9004823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 9016456Sgblack@eecs.umich.edu dataSize * 8 - realShiftAmt + 1); 9024733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9037967Sgblack@eecs.umich.edu } else 9046447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9055040Sgblack@eecs.umich.edu ''' 9065076Sgblack@eecs.umich.edu flag_code = ''' 9075076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9085076Sgblack@eecs.umich.edu if (shiftAmt) { 9096456Sgblack@eecs.umich.edu int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 9105076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9115076Sgblack@eecs.umich.edu //worry about setting them. 9125076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 9135076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 9146456Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 9155076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9166456Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 9176456Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : CFBits) 9185076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 9195076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9205076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 9215076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 9225076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9235076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 9245076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 9255076Sgblack@eecs.umich.edu } 9265076Sgblack@eecs.umich.edu ''' 9274732Sgblack@eecs.umich.edu 9286479Sgblack@eecs.umich.edu class Sld(RegOp): 9297967Sgblack@eecs.umich.edu sldCode = ''' 9306479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9316479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 9327967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 9336479Sgblack@eecs.umich.edu uint64_t result; 9346479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 9356479Sgblack@eecs.umich.edu result = psrc1; 9366479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 9376479Sgblack@eecs.umich.edu result = (psrc1 << realShiftAmt) | 9386479Sgblack@eecs.umich.edu (DoubleBits >> (dataBits - realShiftAmt)); 9396479Sgblack@eecs.umich.edu } else { 9406479Sgblack@eecs.umich.edu result = (DoubleBits << (realShiftAmt - dataBits)) | 9416479Sgblack@eecs.umich.edu (psrc1 >> (2 * dataBits - realShiftAmt)); 9426479Sgblack@eecs.umich.edu } 9437967Sgblack@eecs.umich.edu %s 9446479Sgblack@eecs.umich.edu ''' 9457967Sgblack@eecs.umich.edu code = sldCode % "DestReg = merge(DestReg, result, dataSize);" 9467967Sgblack@eecs.umich.edu big_code = sldCode % "DestReg = result & mask(dataSize * 8);" 9476479Sgblack@eecs.umich.edu flag_code = ''' 9486479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9496479Sgblack@eecs.umich.edu if (shiftAmt) { 9506479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9516479Sgblack@eecs.umich.edu //worry about setting them. 9526479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 9536479Sgblack@eecs.umich.edu int CFBits = 0; 9546479Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 9556479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 9566479Sgblack@eecs.umich.edu bits(DoubleBits, 0)) || 9576479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 9586479Sgblack@eecs.umich.edu bits(SrcReg1, dataBits - realShiftAmt)) || 9596479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 9606479Sgblack@eecs.umich.edu bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 9616479Sgblack@eecs.umich.edu CFBits = 1; 9626479Sgblack@eecs.umich.edu } 9636479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9646479Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 9656479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 9666479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9676479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 9686479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 9696479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 9706479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9716479Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 9726479Sgblack@eecs.umich.edu DestReg, psrc1, op2); 9736479Sgblack@eecs.umich.edu } 9746479Sgblack@eecs.umich.edu ''' 9756479Sgblack@eecs.umich.edu 9766479Sgblack@eecs.umich.edu class Srd(RegOp): 9777967Sgblack@eecs.umich.edu srdCode = ''' 9786479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9796479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 9807967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 9816479Sgblack@eecs.umich.edu uint64_t result; 9826479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 9836479Sgblack@eecs.umich.edu result = psrc1; 9846479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 9856479Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right 9866479Sgblack@eecs.umich.edu // shift is not defined in the C/C++ standard, we have to 9876479Sgblack@eecs.umich.edu // mask them out to be sure they're zero. 9886479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataBits - realShiftAmt); 9896479Sgblack@eecs.umich.edu result = ((psrc1 >> realShiftAmt) & logicalMask) | 9906479Sgblack@eecs.umich.edu (DoubleBits << (dataBits - realShiftAmt)); 9916479Sgblack@eecs.umich.edu } else { 9926479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 9936479Sgblack@eecs.umich.edu result = ((DoubleBits >> (realShiftAmt - dataBits)) & 9946479Sgblack@eecs.umich.edu logicalMask) | 9956479Sgblack@eecs.umich.edu (psrc1 << (2 * dataBits - realShiftAmt)); 9966479Sgblack@eecs.umich.edu } 9977967Sgblack@eecs.umich.edu %s 9986479Sgblack@eecs.umich.edu ''' 9997967Sgblack@eecs.umich.edu code = srdCode % "DestReg = merge(DestReg, result, dataSize);" 10007967Sgblack@eecs.umich.edu big_code = srdCode % "DestReg = result & mask(dataSize * 8);" 10016479Sgblack@eecs.umich.edu flag_code = ''' 10026479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10036479Sgblack@eecs.umich.edu if (shiftAmt) { 10046479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10056479Sgblack@eecs.umich.edu //worry about setting them. 10066479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 10076479Sgblack@eecs.umich.edu int CFBits = 0; 10086479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10096479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 10106479Sgblack@eecs.umich.edu bits(DoubleBits, dataBits - 1)) || 10116479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 10126479Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) || 10136479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 10146479Sgblack@eecs.umich.edu bits(DoubleBits, realShiftAmt - dataBits - 1))) { 10156479Sgblack@eecs.umich.edu CFBits = 1; 10166479Sgblack@eecs.umich.edu } 10176479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10186479Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 10196479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 10206479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10216479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 10226479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 10236479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 10246479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10256479Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 10266479Sgblack@eecs.umich.edu DestReg, psrc1, op2); 10276479Sgblack@eecs.umich.edu } 10286479Sgblack@eecs.umich.edu ''' 10296479Sgblack@eecs.umich.edu 10306479Sgblack@eecs.umich.edu class Mdb(WrRegOp): 10316479Sgblack@eecs.umich.edu code = 'DoubleBits = psrc1 ^ op2;' 10326479Sgblack@eecs.umich.edu 10335040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 10347789Sgblack@eecs.umich.edu code = 'NRIP = psrc1 + sop2 + CSBase;' 10357789Sgblack@eecs.umich.edu else_code = "NRIP = NRIP;" 10365040Sgblack@eecs.umich.edu 10375040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 10385040Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 10395040Sgblack@eecs.umich.edu 10405426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 10415426Sgblack@eecs.umich.edu code = ''' 10425426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 10435426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 10445426Sgblack@eecs.umich.edu // Get only the user flags 10455426Sgblack@eecs.umich.edu ccFlagBits = newFlags & userFlagMask; 10465426Sgblack@eecs.umich.edu // Get everything else 10475426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 10485426Sgblack@eecs.umich.edu ''' 10495426Sgblack@eecs.umich.edu 10505040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 10517789Sgblack@eecs.umich.edu code = 'DestReg = NRIP - CSBase;' 10525040Sgblack@eecs.umich.edu 10535040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 10545040Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 10555040Sgblack@eecs.umich.edu 10565426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 10575426Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits | nccFlagBits' 10585426Sgblack@eecs.umich.edu 10595040Sgblack@eecs.umich.edu class Ruflag(RegOp): 10605040Sgblack@eecs.umich.edu code = ''' 10615116Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8); 10624951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 10635011Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 10645011Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 10655040Sgblack@eecs.umich.edu ''' 10667967Sgblack@eecs.umich.edu big_code = ''' 10677967Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8); 10687967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 10697967Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 10707967Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 10717967Sgblack@eecs.umich.edu ''' 10725040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 10735040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 10745040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 10756345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 10764732Sgblack@eecs.umich.edu 10775426Sgblack@eecs.umich.edu class Rflag(RegOp): 10785426Sgblack@eecs.umich.edu code = ''' 10795426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 10805426Sgblack@eecs.umich.edu MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 10815426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 10825426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 10835426Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 10845426Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 10855426Sgblack@eecs.umich.edu ''' 10867967Sgblack@eecs.umich.edu big_code = ''' 10877967Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 10887967Sgblack@eecs.umich.edu MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 10897967Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 10907967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 10917967Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 10927967Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 10937967Sgblack@eecs.umich.edu ''' 10945426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 10955426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 10965426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 10976345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 10985426Sgblack@eecs.umich.edu 10995040Sgblack@eecs.umich.edu class Sext(RegOp): 11005040Sgblack@eecs.umich.edu code = ''' 11014823Sgblack@eecs.umich.edu IntReg val = psrc1; 11025239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 11035239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 11045239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 11055239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 11065007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 11075007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 11085040Sgblack@eecs.umich.edu ''' 11097967Sgblack@eecs.umich.edu big_code = ''' 11107967Sgblack@eecs.umich.edu IntReg val = psrc1; 11117967Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 11127967Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 11137967Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 11147967Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 11157967Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 11167967Sgblack@eecs.umich.edu DestReg = val & mask(dataSize * 8); 11177967Sgblack@eecs.umich.edu ''' 11185239Sgblack@eecs.umich.edu flag_code = ''' 11195239Sgblack@eecs.umich.edu if (!sign_bit) 11205239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & 11215239Sgblack@eecs.umich.edu ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 11225239Sgblack@eecs.umich.edu else 11235239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | 11245239Sgblack@eecs.umich.edu (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 11255239Sgblack@eecs.umich.edu ''' 11264714Sgblack@eecs.umich.edu 11275040Sgblack@eecs.umich.edu class Zext(RegOp): 11285927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 11297967Sgblack@eecs.umich.edu big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' 11305241Sgblack@eecs.umich.edu 11315926Sgblack@eecs.umich.edu class Rddr(RegOp): 11325926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11335926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 11346345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11357967Sgblack@eecs.umich.edu rdrCode = ''' 11365926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 11375926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 11385926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 11395926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11405926Sgblack@eecs.umich.edu } else if (dr7.gd) { 11415926Sgblack@eecs.umich.edu fault = new DebugException(); 11425926Sgblack@eecs.umich.edu } else { 11437967Sgblack@eecs.umich.edu %s 11445926Sgblack@eecs.umich.edu } 11455926Sgblack@eecs.umich.edu ''' 11467967Sgblack@eecs.umich.edu code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" 11477967Sgblack@eecs.umich.edu big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" 11485926Sgblack@eecs.umich.edu 11495926Sgblack@eecs.umich.edu class Wrdr(RegOp): 11505926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11515926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 11526345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11535926Sgblack@eecs.umich.edu code = ''' 11545926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 11555926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 11565926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 11575926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11586345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 11595926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 11605926Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11615926Sgblack@eecs.umich.edu } else if (dr7.gd) { 11625926Sgblack@eecs.umich.edu fault = new DebugException(); 11635926Sgblack@eecs.umich.edu } else { 11645926Sgblack@eecs.umich.edu DebugDest = psrc1; 11655926Sgblack@eecs.umich.edu } 11665926Sgblack@eecs.umich.edu ''' 11675926Sgblack@eecs.umich.edu 11685296Sgblack@eecs.umich.edu class Rdcr(RegOp): 11695296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11705296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 11716345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11727967Sgblack@eecs.umich.edu rdcrCode = ''' 11735924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 11745296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11755296Sgblack@eecs.umich.edu } else { 11767967Sgblack@eecs.umich.edu %s 11775296Sgblack@eecs.umich.edu } 11785296Sgblack@eecs.umich.edu ''' 11797967Sgblack@eecs.umich.edu code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" 11807967Sgblack@eecs.umich.edu big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" 11815296Sgblack@eecs.umich.edu 11825241Sgblack@eecs.umich.edu class Wrcr(RegOp): 11835241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11845241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 11856345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11865241Sgblack@eecs.umich.edu code = ''' 11875241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 11885241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11895241Sgblack@eecs.umich.edu } else { 11905241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 11915241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 11925241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 11935241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 11945241Sgblack@eecs.umich.edu 11955241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 11965241Sgblack@eecs.umich.edu switch(dest) { 11975241Sgblack@eecs.umich.edu case 0: 11985241Sgblack@eecs.umich.edu { 11995241Sgblack@eecs.umich.edu Efer efer = EferOp; 12005241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 12015241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 12025241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 12035241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 12045241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 12055241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 12065241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12075241Sgblack@eecs.umich.edu } 12085241Sgblack@eecs.umich.edu break; 12095241Sgblack@eecs.umich.edu case 2: 12105241Sgblack@eecs.umich.edu break; 12115241Sgblack@eecs.umich.edu case 3: 12125241Sgblack@eecs.umich.edu break; 12135241Sgblack@eecs.umich.edu case 4: 12145241Sgblack@eecs.umich.edu { 12155241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 12165241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 12175241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 12185241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 12195241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12205241Sgblack@eecs.umich.edu } 12215241Sgblack@eecs.umich.edu break; 12225241Sgblack@eecs.umich.edu case 8: 12235241Sgblack@eecs.umich.edu { 12245241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 12255241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12265241Sgblack@eecs.umich.edu } 12275241Sgblack@eecs.umich.edu default: 12285241Sgblack@eecs.umich.edu panic("Unrecognized control register %d.\\n", dest); 12295241Sgblack@eecs.umich.edu } 12305241Sgblack@eecs.umich.edu ControlDest = newVal; 12315241Sgblack@eecs.umich.edu } 12325241Sgblack@eecs.umich.edu ''' 12335290Sgblack@eecs.umich.edu 12345294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 12355672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 12365294Sgblack@eecs.umich.edu abstract = True 12375290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12385294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 12396345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12405294Sgblack@eecs.umich.edu 12415294Sgblack@eecs.umich.edu class Wrbase(SegOp): 12425290Sgblack@eecs.umich.edu code = ''' 12435294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 12445290Sgblack@eecs.umich.edu ''' 12455290Sgblack@eecs.umich.edu 12465294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 12475290Sgblack@eecs.umich.edu code = ''' 12485294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 12495294Sgblack@eecs.umich.edu ''' 12505294Sgblack@eecs.umich.edu 12515294Sgblack@eecs.umich.edu class Wrsel(SegOp): 12525294Sgblack@eecs.umich.edu code = ''' 12535294Sgblack@eecs.umich.edu SegSelDest = psrc1; 12545294Sgblack@eecs.umich.edu ''' 12555294Sgblack@eecs.umich.edu 12565905Sgblack@eecs.umich.edu class WrAttr(SegOp): 12575905Sgblack@eecs.umich.edu code = ''' 12585905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 12595905Sgblack@eecs.umich.edu ''' 12605905Sgblack@eecs.umich.edu 12615294Sgblack@eecs.umich.edu class Rdbase(SegOp): 12627967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' 12637967Sgblack@eecs.umich.edu big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' 12645294Sgblack@eecs.umich.edu 12655294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 12667967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' 12677967Sgblack@eecs.umich.edu big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' 12685294Sgblack@eecs.umich.edu 12695427Sgblack@eecs.umich.edu class RdAttr(SegOp): 12707967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' 12717967Sgblack@eecs.umich.edu big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' 12725427Sgblack@eecs.umich.edu 12735294Sgblack@eecs.umich.edu class Rdsel(SegOp): 12747967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' 12757967Sgblack@eecs.umich.edu big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' 12765294Sgblack@eecs.umich.edu 12775682Sgblack@eecs.umich.edu class Rdval(RegOp): 12785682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12796345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 12806345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12815682Sgblack@eecs.umich.edu code = ''' 12825682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 12835682Sgblack@eecs.umich.edu ''' 12845682Sgblack@eecs.umich.edu 12855682Sgblack@eecs.umich.edu class Wrval(RegOp): 12865682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12876345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 12886345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12895682Sgblack@eecs.umich.edu code = ''' 12905682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 12915682Sgblack@eecs.umich.edu ''' 12925682Sgblack@eecs.umich.edu 12935428Sgblack@eecs.umich.edu class Chks(RegOp): 12945428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 12955428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 12965428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 12975428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 12985294Sgblack@eecs.umich.edu code = ''' 12995424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 13005433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 13015433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 13025433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 13035294Sgblack@eecs.umich.edu 13045428Sgblack@eecs.umich.edu switch (imm8) 13055428Sgblack@eecs.umich.edu { 13065428Sgblack@eecs.umich.edu case SegNoCheck: 13075428Sgblack@eecs.umich.edu break; 13085428Sgblack@eecs.umich.edu case SegCSCheck: 13096060Sgblack@eecs.umich.edu // Make sure it's the right type 13106060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 13116060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13126060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 13136060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13146060Sgblack@eecs.umich.edu } 13155428Sgblack@eecs.umich.edu break; 13165428Sgblack@eecs.umich.edu case SegCallGateCheck: 13175428Sgblack@eecs.umich.edu panic("CS checks for far calls/jumps through call gates" 13185428Sgblack@eecs.umich.edu "not implemented.\\n"); 13195428Sgblack@eecs.umich.edu break; 13205855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 13215853Sgblack@eecs.umich.edu // Check permissions. 13225674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 13235857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13246058Sgblack@eecs.umich.edu break; 13255674Sgblack@eecs.umich.edu } 13265855Sgblack@eecs.umich.edu // Fall through on purpose 13275855Sgblack@eecs.umich.edu case SegIntGateCheck: 13285853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 13295861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 13305853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 13315853Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13325853Sgblack@eecs.umich.edu } 13335674Sgblack@eecs.umich.edu break; 13345428Sgblack@eecs.umich.edu case SegSSCheck: 13355433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 13365433Sgblack@eecs.umich.edu if (!desc.p) { 13375857Sgblack@eecs.umich.edu fault = new StackFault(selector); 13385433Sgblack@eecs.umich.edu } 13395433Sgblack@eecs.umich.edu } else { 13405673Sgblack@eecs.umich.edu if ((m5reg.submode != SixtyFourBitMode || 13415673Sgblack@eecs.umich.edu m5reg.cpl == 3) || 13425433Sgblack@eecs.umich.edu !(desc.s == 1 && 13435433Sgblack@eecs.umich.edu desc.type.codeOrData == 0 && desc.type.w) || 13445433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 13455433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 13465857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13475433Sgblack@eecs.umich.edu } 13485433Sgblack@eecs.umich.edu } 13495428Sgblack@eecs.umich.edu break; 13505428Sgblack@eecs.umich.edu case SegIretCheck: 13515428Sgblack@eecs.umich.edu { 13525433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 13535433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 13545433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 13555433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 13565679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 13575857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13585679Sgblack@eecs.umich.edu } else if (!desc.p) { 13595857Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 13605679Sgblack@eecs.umich.edu } 13615428Sgblack@eecs.umich.edu break; 13625428Sgblack@eecs.umich.edu } 13635428Sgblack@eecs.umich.edu case SegIntCSCheck: 13645675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 13655675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 13665679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13675675Sgblack@eecs.umich.edu } 13685675Sgblack@eecs.umich.edu } else { 13695675Sgblack@eecs.umich.edu panic("Interrupt CS checks not implemented " 13705675Sgblack@eecs.umich.edu "in legacy mode.\\n"); 13715675Sgblack@eecs.umich.edu } 13725428Sgblack@eecs.umich.edu break; 13735899Sgblack@eecs.umich.edu case SegTRCheck: 13745899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 13755899Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13765899Sgblack@eecs.umich.edu } 13775899Sgblack@eecs.umich.edu break; 13785900Sgblack@eecs.umich.edu case SegTSSCheck: 13795900Sgblack@eecs.umich.edu if (!desc.p) { 13805900Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 13815900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 13825900Sgblack@eecs.umich.edu (desc.type == 1 && 13835900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 13845935Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13855900Sgblack@eecs.umich.edu } 13865900Sgblack@eecs.umich.edu break; 13875936Sgblack@eecs.umich.edu case SegInGDTCheck: 13885936Sgblack@eecs.umich.edu if (selector.ti) { 13895936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13905936Sgblack@eecs.umich.edu } 13915936Sgblack@eecs.umich.edu break; 13925936Sgblack@eecs.umich.edu case SegLDTCheck: 13935936Sgblack@eecs.umich.edu if (!desc.p) { 13945936Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 13955936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 13965936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13975936Sgblack@eecs.umich.edu } 13985936Sgblack@eecs.umich.edu break; 13995428Sgblack@eecs.umich.edu default: 14005428Sgblack@eecs.umich.edu panic("Undefined segment check type.\\n"); 14015428Sgblack@eecs.umich.edu } 14025294Sgblack@eecs.umich.edu ''' 14035294Sgblack@eecs.umich.edu flag_code = ''' 14045294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 14055294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 14065424Sgblack@eecs.umich.edu if (!selector.si && !selector.ti) 14075294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 14085294Sgblack@eecs.umich.edu ''' 14095294Sgblack@eecs.umich.edu 14105294Sgblack@eecs.umich.edu class Wrdh(RegOp): 14115294Sgblack@eecs.umich.edu code = ''' 14125678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 14135294Sgblack@eecs.umich.edu 14145678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 14155678Sgblack@eecs.umich.edu switch(desc.type) { 14165678Sgblack@eecs.umich.edu case LDT64: 14175678Sgblack@eecs.umich.edu case AvailableTSS64: 14185678Sgblack@eecs.umich.edu case BusyTSS64: 14195678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 14205678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 14215678Sgblack@eecs.umich.edu break; 14225678Sgblack@eecs.umich.edu case CallGate64: 14235678Sgblack@eecs.umich.edu case IntGate64: 14245678Sgblack@eecs.umich.edu case TrapGate64: 14255678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 14265678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 14275678Sgblack@eecs.umich.edu break; 14285678Sgblack@eecs.umich.edu default: 14295678Sgblack@eecs.umich.edu panic("Wrdh used with wrong descriptor type!\\n"); 14305678Sgblack@eecs.umich.edu } 14315678Sgblack@eecs.umich.edu DestReg = target; 14325294Sgblack@eecs.umich.edu ''' 14335294Sgblack@eecs.umich.edu 14345409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 14355409Sgblack@eecs.umich.edu code = ''' 14365409Sgblack@eecs.umich.edu TscOp = psrc1; 14375409Sgblack@eecs.umich.edu ''' 14385409Sgblack@eecs.umich.edu 14395409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 14405409Sgblack@eecs.umich.edu code = ''' 14415409Sgblack@eecs.umich.edu DestReg = TscOp; 14425409Sgblack@eecs.umich.edu ''' 14435409Sgblack@eecs.umich.edu 14445429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 14455429Sgblack@eecs.umich.edu code = ''' 14465429Sgblack@eecs.umich.edu DestReg = M5Reg; 14475429Sgblack@eecs.umich.edu ''' 14485429Sgblack@eecs.umich.edu 14495294Sgblack@eecs.umich.edu class Wrdl(RegOp): 14505294Sgblack@eecs.umich.edu code = ''' 14515294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 14525433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 14535433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 14546222Sgblack@eecs.umich.edu if (!desc.p) 14556222Sgblack@eecs.umich.edu panic("Segment not present.\\n"); 14565433Sgblack@eecs.umich.edu SegAttr attr = 0; 14575433Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 14586222Sgblack@eecs.umich.edu attr.unusable = 0; 14595433Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 14606222Sgblack@eecs.umich.edu attr.longMode = desc.l; 14616222Sgblack@eecs.umich.edu attr.avl = desc.avl; 14626222Sgblack@eecs.umich.edu attr.granularity = desc.g; 14636222Sgblack@eecs.umich.edu attr.present = desc.p; 14646222Sgblack@eecs.umich.edu attr.system = desc.s; 14656222Sgblack@eecs.umich.edu attr.type = desc.type; 14665433Sgblack@eecs.umich.edu if (!desc.s) { 14675901Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 14685901Sgblack@eecs.umich.edu if (desc.type.e) { 14695901Sgblack@eecs.umich.edu panic("Gate descriptor encountered.\\n"); 14705901Sgblack@eecs.umich.edu } 14715901Sgblack@eecs.umich.edu attr.readable = 1; 14725901Sgblack@eecs.umich.edu attr.writable = 1; 14736222Sgblack@eecs.umich.edu attr.expandDown = 0; 14745433Sgblack@eecs.umich.edu } else { 14755433Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 14766222Sgblack@eecs.umich.edu attr.expandDown = 0; 14775433Sgblack@eecs.umich.edu attr.readable = desc.type.r; 14786222Sgblack@eecs.umich.edu attr.writable = 0; 14795433Sgblack@eecs.umich.edu } else { 14805433Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 14815433Sgblack@eecs.umich.edu attr.readable = 1; 14825433Sgblack@eecs.umich.edu attr.writable = desc.type.w; 14835433Sgblack@eecs.umich.edu } 14845433Sgblack@eecs.umich.edu } 14855901Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 14865901Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 14875901Sgblack@eecs.umich.edu if (desc.g) 14885901Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 14895901Sgblack@eecs.umich.edu SegBaseDest = base; 14905901Sgblack@eecs.umich.edu SegLimitDest = limit; 14915901Sgblack@eecs.umich.edu SegAttrDest = attr; 14925433Sgblack@eecs.umich.edu } else { 14935295Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 14945295Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 14955295Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 14965294Sgblack@eecs.umich.edu } 14975290Sgblack@eecs.umich.edu ''' 14984519Sgblack@eecs.umich.edu}}; 1499