regop.isa revision 7626
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 124519Sgblack@eecs.umich.edu// 137087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 147087Snate@binkert.org// modification, are permitted provided that the following conditions are 157087Snate@binkert.org// met: redistributions of source code must retain the above copyright 167087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org// documentation and/or other materials provided with the distribution; 207087Snate@binkert.org// neither the name of the copyright holders nor the names of its 214519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227087Snate@binkert.org// this software without specific prior written permission. 234519Sgblack@eecs.umich.edu// 244519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354519Sgblack@eecs.umich.edu// 364519Sgblack@eecs.umich.edu// Authors: Gabe Black 374519Sgblack@eecs.umich.edu 384519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 394519Sgblack@eecs.umich.edu// 404519Sgblack@eecs.umich.edu// RegOp Microop templates 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 434519Sgblack@eecs.umich.edu 444519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 454519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 464519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474519Sgblack@eecs.umich.edu { 484519Sgblack@eecs.umich.edu Fault fault = NoFault; 494519Sgblack@eecs.umich.edu 504809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 514519Sgblack@eecs.umich.edu %(op_decl)s; 524519Sgblack@eecs.umich.edu %(op_rd)s; 534688Sgblack@eecs.umich.edu 544688Sgblack@eecs.umich.edu if(%(cond_check)s) 554688Sgblack@eecs.umich.edu { 564688Sgblack@eecs.umich.edu %(code)s; 574688Sgblack@eecs.umich.edu %(flag_code)s; 584688Sgblack@eecs.umich.edu } 594708Sgblack@eecs.umich.edu else 604708Sgblack@eecs.umich.edu { 614708Sgblack@eecs.umich.edu %(else_code)s; 624708Sgblack@eecs.umich.edu } 634519Sgblack@eecs.umich.edu 644519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 654519Sgblack@eecs.umich.edu if(fault == NoFault) 664519Sgblack@eecs.umich.edu { 674519Sgblack@eecs.umich.edu %(op_wb)s; 684519Sgblack@eecs.umich.edu } 694519Sgblack@eecs.umich.edu return fault; 704519Sgblack@eecs.umich.edu } 714519Sgblack@eecs.umich.edu}}; 724519Sgblack@eecs.umich.edu 734519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 744951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 754519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 764519Sgblack@eecs.umich.edu { 774519Sgblack@eecs.umich.edu Fault fault = NoFault; 784519Sgblack@eecs.umich.edu 794519Sgblack@eecs.umich.edu %(op_decl)s; 804519Sgblack@eecs.umich.edu %(op_rd)s; 814688Sgblack@eecs.umich.edu 824688Sgblack@eecs.umich.edu if(%(cond_check)s) 834688Sgblack@eecs.umich.edu { 844688Sgblack@eecs.umich.edu %(code)s; 854688Sgblack@eecs.umich.edu %(flag_code)s; 864688Sgblack@eecs.umich.edu } 874708Sgblack@eecs.umich.edu else 884708Sgblack@eecs.umich.edu { 894708Sgblack@eecs.umich.edu %(else_code)s; 904708Sgblack@eecs.umich.edu } 914519Sgblack@eecs.umich.edu 924519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 934519Sgblack@eecs.umich.edu if(fault == NoFault) 944519Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu %(op_wb)s; 964519Sgblack@eecs.umich.edu } 974519Sgblack@eecs.umich.edu return fault; 984519Sgblack@eecs.umich.edu } 994519Sgblack@eecs.umich.edu}}; 1004519Sgblack@eecs.umich.edu 1014519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1024519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1034519Sgblack@eecs.umich.edu { 1044519Sgblack@eecs.umich.edu public: 1054519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1067620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1076345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1084712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1094519Sgblack@eecs.umich.edu 1104519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1114519Sgblack@eecs.umich.edu }; 1124519Sgblack@eecs.umich.edu}}; 1134519Sgblack@eecs.umich.edu 1144519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1154519Sgblack@eecs.umich.edu 1164951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1174519Sgblack@eecs.umich.edu { 1184519Sgblack@eecs.umich.edu public: 1194951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1207620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1216646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1224712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1234519Sgblack@eecs.umich.edu 1244519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1254519Sgblack@eecs.umich.edu }; 1264519Sgblack@eecs.umich.edu}}; 1274519Sgblack@eecs.umich.edu 1284519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1294519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1307620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1316345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1324712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1337620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1344688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1354581Sgblack@eecs.umich.edu %(op_class)s) 1364519Sgblack@eecs.umich.edu { 1377626Sgblack@eecs.umich.edu %(constructor)s; 1384519Sgblack@eecs.umich.edu } 1394519Sgblack@eecs.umich.edu}}; 1404519Sgblack@eecs.umich.edu 1414519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1424951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1437620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1446646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1454712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1467620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1474688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 1484581Sgblack@eecs.umich.edu %(op_class)s) 1494519Sgblack@eecs.umich.edu { 1507626Sgblack@eecs.umich.edu %(constructor)s; 1514519Sgblack@eecs.umich.edu } 1524519Sgblack@eecs.umich.edu}}; 1534519Sgblack@eecs.umich.edu 1545075Sgblack@eecs.umich.eduoutput header {{ 1555075Sgblack@eecs.umich.edu void 1565075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1575075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 1585428Sgblack@eecs.umich.edu 1595428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 1605674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 1615899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 1625936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 1635428Sgblack@eecs.umich.edu }; 1645678Sgblack@eecs.umich.edu 1655678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 1665678Sgblack@eecs.umich.edu LDT64 = 2, 1675678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 1685678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 1695678Sgblack@eecs.umich.edu CallGate64 = 0xc, 1705678Sgblack@eecs.umich.edu IntGate64 = 0xe, 1715678Sgblack@eecs.umich.edu TrapGate64 = 0xf 1725678Sgblack@eecs.umich.edu }; 1735075Sgblack@eecs.umich.edu}}; 1745075Sgblack@eecs.umich.edu 1755075Sgblack@eecs.umich.eduoutput decoder {{ 1765075Sgblack@eecs.umich.edu void 1775075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1785075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 1795075Sgblack@eecs.umich.edu { 1805075Sgblack@eecs.umich.edu //Check for divide by zero. 1815075Sgblack@eecs.umich.edu if (divisor == 0) 1825075Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 1835075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 1845075Sgblack@eecs.umich.edu if (divisor <= dividend) { 1855075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 1865075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 1875075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 1885075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 1895075Sgblack@eecs.umich.edu divisor <<= shift; 1905075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 1915075Sgblack@eecs.umich.edu //now larger than the dividend. 1925075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 1935075Sgblack@eecs.umich.edu quotientBit <<= shift; 1945075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 1955075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 1965075Sgblack@eecs.umich.edu //part of one or two bit division. 1975075Sgblack@eecs.umich.edu if (divisor > dividend) { 1985075Sgblack@eecs.umich.edu quotientBit >>= 1; 1995075Sgblack@eecs.umich.edu divisor >>= 1; 2005075Sgblack@eecs.umich.edu } 2015075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2025075Sgblack@eecs.umich.edu quotient += quotientBit; 2035075Sgblack@eecs.umich.edu remainder -= divisor; 2045075Sgblack@eecs.umich.edu } 2055075Sgblack@eecs.umich.edu } 2065075Sgblack@eecs.umich.edu}}; 2075075Sgblack@eecs.umich.edu 2084519Sgblack@eecs.umich.edulet {{ 2095040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2105040Sgblack@eecs.umich.edu # them will always work. 2115040Sgblack@eecs.umich.edu header_output = "" 2125040Sgblack@eecs.umich.edu decoder_output = "" 2135040Sgblack@eecs.umich.edu exec_output = "" 2145040Sgblack@eecs.umich.edu 2155040Sgblack@eecs.umich.edu immTemplates = ( 2165040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2175040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2185040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2195040Sgblack@eecs.umich.edu 2205040Sgblack@eecs.umich.edu regTemplates = ( 2215040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2225040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2235040Sgblack@eecs.umich.edu MicroRegOpExecute) 2245040Sgblack@eecs.umich.edu 2255040Sgblack@eecs.umich.edu class RegOpMeta(type): 2265040Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 2275040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code): 2285040Sgblack@eecs.umich.edu 2295040Sgblack@eecs.umich.edu # Globals to stick the output in 2305040Sgblack@eecs.umich.edu global header_output 2315040Sgblack@eecs.umich.edu global decoder_output 2325040Sgblack@eecs.umich.edu global exec_output 2335040Sgblack@eecs.umich.edu 2345040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2355040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 2365040Sgblack@eecs.umich.edu 2375040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2385040Sgblack@eecs.umich.edu # of this code. 2395062Sgblack@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 2405062Sgblack@eecs.umich.edu match = matcher.search(allCode) 2415062Sgblack@eecs.umich.edu if match: 2425062Sgblack@eecs.umich.edu typeQual = "" 2435062Sgblack@eecs.umich.edu if match.group("typeQual"): 2445062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 2455062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 2465040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2475062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 2485062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 2495062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 2505062Sgblack@eecs.umich.edu matcher.sub(src2_name, else_code)) 2516647Sgblack@eecs.umich.edu imm_name = "%simm8" % match.group("prefix") 2525040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 2536647Sgblack@eecs.umich.edu matcher.sub(imm_name, code), 2546647Sgblack@eecs.umich.edu matcher.sub(imm_name, flag_code), 2556647Sgblack@eecs.umich.edu matcher.sub(imm_name, cond_check), 2566647Sgblack@eecs.umich.edu matcher.sub(imm_name, else_code)) 2575040Sgblack@eecs.umich.edu return 2585040Sgblack@eecs.umich.edu 2595040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 2605040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 2615239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 2625040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2635040Sgblack@eecs.umich.edu code, "", "true", else_code) 2645040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 2655040Sgblack@eecs.umich.edu 2665040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 2675040Sgblack@eecs.umich.edu # compute it. 2685040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 2695040Sgblack@eecs.umich.edu if matcher.search(allCode): 2705061Sgblack@eecs.umich.edu code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 2715040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 2725040Sgblack@eecs.umich.edu if matcher.search(allCode): 2735061Sgblack@eecs.umich.edu code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 2745061Sgblack@eecs.umich.edu # Also make available versions which do sign extension 2755061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc1(?!\w)") 2765061Sgblack@eecs.umich.edu if matcher.search(allCode): 2775061Sgblack@eecs.umich.edu code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 2785061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc2(?!\w)") 2795061Sgblack@eecs.umich.edu if matcher.search(allCode): 2805061Sgblack@eecs.umich.edu code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 2816647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)simm8(?!\w)") 2826647Sgblack@eecs.umich.edu if matcher.search(allCode): 2836647Sgblack@eecs.umich.edu code = "int8_t simm8 = imm8;" + code 2845040Sgblack@eecs.umich.edu 2855040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 2865040Sgblack@eecs.umich.edu 2875040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 2885040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 2895040Sgblack@eecs.umich.edu templates = regTemplates 2906647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 2915040Sgblack@eecs.umich.edu if matcher.search(allCode): 2925040Sgblack@eecs.umich.edu base += "Imm" 2935040Sgblack@eecs.umich.edu templates = immTemplates 2945040Sgblack@eecs.umich.edu 2955040Sgblack@eecs.umich.edu # Get everything ready for the substitution 2965040Sgblack@eecs.umich.edu iop = InstObjParams(name, Name + suffix, base, 2975040Sgblack@eecs.umich.edu {"code" : code, 2985040Sgblack@eecs.umich.edu "flag_code" : flag_code, 2995040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3005040Sgblack@eecs.umich.edu "else_code" : else_code}) 3015040Sgblack@eecs.umich.edu 3025040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3035040Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3045040Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3055040Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3065040Sgblack@eecs.umich.edu 3075040Sgblack@eecs.umich.edu 3085040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3094688Sgblack@eecs.umich.edu abstract = False 3105040Sgblack@eecs.umich.edu name = Name.lower() 3114688Sgblack@eecs.umich.edu if "abstract" in dict: 3124688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3134688Sgblack@eecs.umich.edu del dict['abstract'] 3144688Sgblack@eecs.umich.edu 3155040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3164688Sgblack@eecs.umich.edu if not abstract: 3175040Sgblack@eecs.umich.edu cls.className = Name 3185040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3195040Sgblack@eecs.umich.edu code = cls.code 3205040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3215040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3225040Sgblack@eecs.umich.edu else_code = cls.else_code 3235040Sgblack@eecs.umich.edu 3245040Sgblack@eecs.umich.edu # Set up the C++ classes 3255040Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", 3265040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code) 3275040Sgblack@eecs.umich.edu 3285040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3295040Sgblack@eecs.umich.edu global microopClasses 3305040Sgblack@eecs.umich.edu microopClasses[name] = cls 3315040Sgblack@eecs.umich.edu 3325040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3335040Sgblack@eecs.umich.edu 3345040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3355040Sgblack@eecs.umich.edu # of this code. 3365040Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3375040Sgblack@eecs.umich.edu if matcher.search(allCode): 3385040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3394688Sgblack@eecs.umich.edu return cls 3404688Sgblack@eecs.umich.edu 3415040Sgblack@eecs.umich.edu 3425040Sgblack@eecs.umich.edu class RegOp(X86Microop): 3435040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 3445040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 3454688Sgblack@eecs.umich.edu abstract = True 3464688Sgblack@eecs.umich.edu 3475040Sgblack@eecs.umich.edu # Default template parameter values 3485040Sgblack@eecs.umich.edu flag_code = "" 3495040Sgblack@eecs.umich.edu cond_check = "true" 3505040Sgblack@eecs.umich.edu else_code = ";" 3515040Sgblack@eecs.umich.edu 3525040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 3534519Sgblack@eecs.umich.edu self.dest = dest 3544519Sgblack@eecs.umich.edu self.src1 = src1 3555040Sgblack@eecs.umich.edu self.op2 = op2 3564688Sgblack@eecs.umich.edu self.flags = flags 3574701Sgblack@eecs.umich.edu self.dataSize = dataSize 3584688Sgblack@eecs.umich.edu if flags is None: 3594688Sgblack@eecs.umich.edu self.ext = 0 3604688Sgblack@eecs.umich.edu else: 3614688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 3624688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 3634688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 3644688Sgblack@eecs.umich.edu self.className += "Flags" 3654519Sgblack@eecs.umich.edu 3667620Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 3675040Sgblack@eecs.umich.edu className = self.className 3685040Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 3695040Sgblack@eecs.umich.edu className += "Imm" 3707620Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 3715040Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 3724688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 3735040Sgblack@eecs.umich.edu "class_name" : className, 3744519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 3755040Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 3764519Sgblack@eecs.umich.edu "dest" : self.dest, 3774519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 3784519Sgblack@eecs.umich.edu "ext" : self.ext} 3794539Sgblack@eecs.umich.edu return allocator 3804519Sgblack@eecs.umich.edu 3815040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 3824688Sgblack@eecs.umich.edu abstract = True 3835040Sgblack@eecs.umich.edu flag_code = ''' 3845040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 3855115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 3865040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 3875040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 3885040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 3895115Sgblack@eecs.umich.edu ccFlagBits &= ~(ECFBit & ext); 3905040Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 3915040Sgblack@eecs.umich.edu ''' 3924519Sgblack@eecs.umich.edu 3935040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 3945040Sgblack@eecs.umich.edu abstract = True 3955040Sgblack@eecs.umich.edu flag_code = \ 3965040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 3974519Sgblack@eecs.umich.edu 3985040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 3995040Sgblack@eecs.umich.edu abstract = True 4005040Sgblack@eecs.umich.edu flag_code = \ 4015040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4024519Sgblack@eecs.umich.edu 4035040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4045040Sgblack@eecs.umich.edu abstract = True 4055083Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits, ext)" 4064519Sgblack@eecs.umich.edu 4075063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4085063Sgblack@eecs.umich.edu abstract = True 4095063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4105063Sgblack@eecs.umich.edu if not src1: 4115063Sgblack@eecs.umich.edu src1 = dest 4126345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4136345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4145063Sgblack@eecs.umich.edu 4155063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4165063Sgblack@eecs.umich.edu abstract = True 4175063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4186345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4196345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 4205063Sgblack@eecs.umich.edu 4215040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4225040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4234595Sgblack@eecs.umich.edu 4245040Sgblack@eecs.umich.edu class Or(LogicRegOp): 4255040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4264595Sgblack@eecs.umich.edu 4275040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 4285040Sgblack@eecs.umich.edu code = ''' 4294732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4305138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 4315040Sgblack@eecs.umich.edu ''' 4325040Sgblack@eecs.umich.edu 4335040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 4345040Sgblack@eecs.umich.edu code = ''' 4354732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4365138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 4375040Sgblack@eecs.umich.edu ''' 4385040Sgblack@eecs.umich.edu 4395040Sgblack@eecs.umich.edu class And(LogicRegOp): 4405040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 4415040Sgblack@eecs.umich.edu 4425040Sgblack@eecs.umich.edu class Sub(SubRegOp): 4435040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 4445040Sgblack@eecs.umich.edu 4455040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 4465040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 4475040Sgblack@eecs.umich.edu 4485063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 4495040Sgblack@eecs.umich.edu code = ''' 4505063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 4515063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 4526742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 4536430Sgblack@eecs.umich.edu uint64_t hiResult; 4546430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 4556430Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 4566461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 4576430Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 4586430Sgblack@eecs.umich.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 4596430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 4606430Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 4616462Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 4626430Sgblack@eecs.umich.edu hiResult -= op2; 4636462Sgblack@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 4646430Sgblack@eecs.umich.edu hiResult -= psrc1; 4656430Sgblack@eecs.umich.edu ProdHi = hiResult; 4665040Sgblack@eecs.umich.edu ''' 4676463Sgblack@eecs.umich.edu flag_code = ''' 4686463Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 4696463Sgblack@eecs.umich.edu bits(ProdLow, dataSize * 8 - 1)) { 4706463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 4716463Sgblack@eecs.umich.edu } else { 4726463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 4736463Sgblack@eecs.umich.edu } 4746463Sgblack@eecs.umich.edu ''' 4755040Sgblack@eecs.umich.edu 4765063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 4775040Sgblack@eecs.umich.edu code = ''' 4785063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 4794809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 4806742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 4816430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 4825063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 4836461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 4845063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 4855063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 4866430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) / shifter) + 4875063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 4885040Sgblack@eecs.umich.edu ''' 4896463Sgblack@eecs.umich.edu flag_code = ''' 4906463Sgblack@eecs.umich.edu if (ProdHi) { 4916463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 4926463Sgblack@eecs.umich.edu } else { 4936463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 4946463Sgblack@eecs.umich.edu } 4956463Sgblack@eecs.umich.edu ''' 4965040Sgblack@eecs.umich.edu 4975063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 4985063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 4995040Sgblack@eecs.umich.edu 5005063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5015063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5025063Sgblack@eecs.umich.edu if not src1: 5035063Sgblack@eecs.umich.edu src1 = dest 5046345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 5056345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 5065063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5075062Sgblack@eecs.umich.edu 5085075Sgblack@eecs.umich.edu # One or two bit divide 5095075Sgblack@eecs.umich.edu class Div1(WrRegOp): 5105040Sgblack@eecs.umich.edu code = ''' 5115075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 5125075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5135075Sgblack@eecs.umich.edu uint64_t quotient = 0; 5145075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 5155075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 5165075Sgblack@eecs.umich.edu //a source. 5175075Sgblack@eecs.umich.edu uint64_t divisor = op2; 5185075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 5195075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 5205075Sgblack@eecs.umich.edu //Do the division. 5215075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5225075Sgblack@eecs.umich.edu //Record the final results. 5235075Sgblack@eecs.umich.edu Remainder = remainder; 5245075Sgblack@eecs.umich.edu Quotient = quotient; 5255075Sgblack@eecs.umich.edu Divisor = divisor; 5265040Sgblack@eecs.umich.edu ''' 5274823Sgblack@eecs.umich.edu 5285075Sgblack@eecs.umich.edu # Step divide 5295075Sgblack@eecs.umich.edu class Div2(RegOp): 5305075Sgblack@eecs.umich.edu code = ''' 5315075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 5325075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 5335075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 5345075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 5355075Sgblack@eecs.umich.edu int remaining = op2; 5365075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 5375075Sgblack@eecs.umich.edu //little. 5385075Sgblack@eecs.umich.edu if (remaining) { 5397070Sgblack@eecs.umich.edu if (divisor & (ULL(1) << 63)) { 5407070Sgblack@eecs.umich.edu while (remaining && !(dividend & (ULL(1) << 63))) { 5417070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 5427070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 5437070Sgblack@eecs.umich.edu quotient <<= 1; 5447070Sgblack@eecs.umich.edu remaining--; 5457070Sgblack@eecs.umich.edu } 5467070Sgblack@eecs.umich.edu if (dividend & (ULL(1) << 63)) { 5477080Sgblack@eecs.umich.edu bool highBit = false; 5487070Sgblack@eecs.umich.edu if (dividend < divisor && remaining) { 5497080Sgblack@eecs.umich.edu highBit = true; 5507070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 5517070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 5527070Sgblack@eecs.umich.edu quotient <<= 1; 5537070Sgblack@eecs.umich.edu remaining--; 5547070Sgblack@eecs.umich.edu } 5557080Sgblack@eecs.umich.edu if (highBit || divisor <= dividend) { 5567080Sgblack@eecs.umich.edu quotient++; 5577080Sgblack@eecs.umich.edu dividend -= divisor; 5587080Sgblack@eecs.umich.edu } 5597070Sgblack@eecs.umich.edu } 5607070Sgblack@eecs.umich.edu remainder = dividend; 5617070Sgblack@eecs.umich.edu } else { 5627070Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 5637070Sgblack@eecs.umich.edu while (dividend < divisor && remaining) { 5647070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 5657070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 5667070Sgblack@eecs.umich.edu quotient <<= 1; 5677070Sgblack@eecs.umich.edu remaining--; 5687070Sgblack@eecs.umich.edu } 5697070Sgblack@eecs.umich.edu remainder = dividend; 5707070Sgblack@eecs.umich.edu //Do the division. 5717070Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5725075Sgblack@eecs.umich.edu } 5735075Sgblack@eecs.umich.edu } 5745075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 5755075Sgblack@eecs.umich.edu DestReg = merge(DestReg, remaining, dataSize); 5765075Sgblack@eecs.umich.edu //Record the final results 5775075Sgblack@eecs.umich.edu Remainder = remainder; 5785075Sgblack@eecs.umich.edu Quotient = quotient; 5795075Sgblack@eecs.umich.edu ''' 5805075Sgblack@eecs.umich.edu flag_code = ''' 5817480Sgblack@eecs.umich.edu if (remaining == 0) 5825075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & EZFBit); 5835075Sgblack@eecs.umich.edu else 5845075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & EZFBit); 5855075Sgblack@eecs.umich.edu ''' 5864732Sgblack@eecs.umich.edu 5875075Sgblack@eecs.umich.edu class Divq(RdRegOp): 5885075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 5895075Sgblack@eecs.umich.edu 5905075Sgblack@eecs.umich.edu class Divr(RdRegOp): 5915075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 5925040Sgblack@eecs.umich.edu 5935040Sgblack@eecs.umich.edu class Mov(CondRegOp): 5945040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 5956482Sgblack@eecs.umich.edu else_code = 'DestReg = DestReg;' 5965040Sgblack@eecs.umich.edu 5974732Sgblack@eecs.umich.edu # Shift instructions 5985040Sgblack@eecs.umich.edu 5995076Sgblack@eecs.umich.edu class Sll(RegOp): 6005040Sgblack@eecs.umich.edu code = ''' 6014756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6024823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6035040Sgblack@eecs.umich.edu ''' 6045076Sgblack@eecs.umich.edu flag_code = ''' 6055076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6065076Sgblack@eecs.umich.edu if (shiftAmt) { 6075076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6085076Sgblack@eecs.umich.edu //worry about setting them. 6095076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6105076Sgblack@eecs.umich.edu int CFBits = 0; 6115076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 6126441Sgblack@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 6136441Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 6145076Sgblack@eecs.umich.edu CFBits = 1; 6156441Sgblack@eecs.umich.edu } 6165076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6175076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 6185076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6195076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6205076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 6215076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6225076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6235076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6245076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6255076Sgblack@eecs.umich.edu } 6265076Sgblack@eecs.umich.edu ''' 6275040Sgblack@eecs.umich.edu 6285076Sgblack@eecs.umich.edu class Srl(RegOp): 6295040Sgblack@eecs.umich.edu code = ''' 6304756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6314732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6324732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 6334732Sgblack@eecs.umich.edu // to be sure they're zero. 6344732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 6354823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 6365040Sgblack@eecs.umich.edu ''' 6375076Sgblack@eecs.umich.edu flag_code = ''' 6385076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6395076Sgblack@eecs.umich.edu if (shiftAmt) { 6405076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6415076Sgblack@eecs.umich.edu //worry about setting them. 6425076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6435076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6446442Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 6456442Sgblack@eecs.umich.edu shiftAmt <= dataSize * 8 && 6466442Sgblack@eecs.umich.edu bits(SrcReg1, shiftAmt - 1)) { 6475076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6486442Sgblack@eecs.umich.edu } 6495076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6505076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 6515076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6525076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6535076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6545076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6555076Sgblack@eecs.umich.edu } 6565076Sgblack@eecs.umich.edu ''' 6575040Sgblack@eecs.umich.edu 6585076Sgblack@eecs.umich.edu class Sra(RegOp): 6595040Sgblack@eecs.umich.edu code = ''' 6604756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6614732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6624732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 6634732Sgblack@eecs.umich.edu // them manually to be sure. 6646443Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 6655032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 6664823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 6675040Sgblack@eecs.umich.edu ''' 6685076Sgblack@eecs.umich.edu flag_code = ''' 6695076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6705076Sgblack@eecs.umich.edu if (shiftAmt) { 6715076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6725076Sgblack@eecs.umich.edu //worry about setting them. 6735076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6745076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6756444Sgblack@eecs.umich.edu uint8_t effectiveShift = 6766444Sgblack@eecs.umich.edu (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 6776444Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 6786444Sgblack@eecs.umich.edu bits(SrcReg1, effectiveShift - 1)) { 6795076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6806444Sgblack@eecs.umich.edu } 6815076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6825076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6835076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6845076Sgblack@eecs.umich.edu } 6855076Sgblack@eecs.umich.edu ''' 6865040Sgblack@eecs.umich.edu 6875076Sgblack@eecs.umich.edu class Ror(RegOp): 6885040Sgblack@eecs.umich.edu code = ''' 6894732Sgblack@eecs.umich.edu uint8_t shiftAmt = 6904756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6916449Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 6926449Sgblack@eecs.umich.edu if(realShiftAmt) 6934732Sgblack@eecs.umich.edu { 6946449Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 6956449Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 6964732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 6974732Sgblack@eecs.umich.edu } 6984732Sgblack@eecs.umich.edu else 6996447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 7005040Sgblack@eecs.umich.edu ''' 7015076Sgblack@eecs.umich.edu flag_code = ''' 7025076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7035076Sgblack@eecs.umich.edu if (shiftAmt) { 7045076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7055076Sgblack@eecs.umich.edu //worry about setting them. 7065076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7075076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 7085076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7095076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 7105076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7115076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && msb) 7125076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7135076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7145076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 7155076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7165076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7175076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7185076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7195076Sgblack@eecs.umich.edu } 7205076Sgblack@eecs.umich.edu ''' 7215040Sgblack@eecs.umich.edu 7225076Sgblack@eecs.umich.edu class Rcr(RegOp): 7235040Sgblack@eecs.umich.edu code = ''' 7244733Sgblack@eecs.umich.edu uint8_t shiftAmt = 7254756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7266454Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 7276454Sgblack@eecs.umich.edu if(realShiftAmt) 7284733Sgblack@eecs.umich.edu { 7294733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 7306454Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 7316454Sgblack@eecs.umich.edu if (realShiftAmt > 1) 7326454Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 7336454Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 7344733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7354733Sgblack@eecs.umich.edu } 7364733Sgblack@eecs.umich.edu else 7376447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 7385040Sgblack@eecs.umich.edu ''' 7395076Sgblack@eecs.umich.edu flag_code = ''' 7405076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7415076Sgblack@eecs.umich.edu if (shiftAmt) { 7426453Sgblack@eecs.umich.edu int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 7435076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7445076Sgblack@eecs.umich.edu //worry about setting them. 7455076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7465076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7476453Sgblack@eecs.umich.edu if ((ext & OFBit) && (origCFBit ^ 7486453Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) { 7495076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7506453Sgblack@eecs.umich.edu } 7515076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7526454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7536454Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : 7546454Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) { 7555076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7566454Sgblack@eecs.umich.edu } 7575076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7585076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7595076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7605076Sgblack@eecs.umich.edu } 7615076Sgblack@eecs.umich.edu ''' 7625040Sgblack@eecs.umich.edu 7635076Sgblack@eecs.umich.edu class Rol(RegOp): 7645040Sgblack@eecs.umich.edu code = ''' 7654732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7664756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7676446Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 7686446Sgblack@eecs.umich.edu if(realShiftAmt) 7694732Sgblack@eecs.umich.edu { 7706446Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 7714732Sgblack@eecs.umich.edu uint64_t bottom = 7726446Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 7734732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7744732Sgblack@eecs.umich.edu } 7754732Sgblack@eecs.umich.edu else 7766447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 7775040Sgblack@eecs.umich.edu ''' 7785076Sgblack@eecs.umich.edu flag_code = ''' 7795076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7805076Sgblack@eecs.umich.edu if (shiftAmt) { 7815076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7825076Sgblack@eecs.umich.edu //worry about setting them. 7835076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7845076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 7855076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 7865076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7875076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7885076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && lsb) 7895076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7905076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7915076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 7925076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7935076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7945076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7955076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7965076Sgblack@eecs.umich.edu } 7975076Sgblack@eecs.umich.edu ''' 7985040Sgblack@eecs.umich.edu 7995076Sgblack@eecs.umich.edu class Rcl(RegOp): 8005040Sgblack@eecs.umich.edu code = ''' 8014733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8024756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8036456Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 8046456Sgblack@eecs.umich.edu if(realShiftAmt) 8054733Sgblack@eecs.umich.edu { 8064733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8076456Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 8086456Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (realShiftAmt - 1); 8094733Sgblack@eecs.umich.edu if(shiftAmt > 1) 8104733Sgblack@eecs.umich.edu bottom |= 8114823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 8126456Sgblack@eecs.umich.edu dataSize * 8 - realShiftAmt + 1); 8134733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8144733Sgblack@eecs.umich.edu } 8154733Sgblack@eecs.umich.edu else 8166447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8175040Sgblack@eecs.umich.edu ''' 8185076Sgblack@eecs.umich.edu flag_code = ''' 8195076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8205076Sgblack@eecs.umich.edu if (shiftAmt) { 8216456Sgblack@eecs.umich.edu int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 8225076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8235076Sgblack@eecs.umich.edu //worry about setting them. 8245076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8255076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8266456Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 8275076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8286456Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8296456Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : CFBits) 8305076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8315076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8325076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 8335076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8345076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8355076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8365076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8375076Sgblack@eecs.umich.edu } 8385076Sgblack@eecs.umich.edu ''' 8394732Sgblack@eecs.umich.edu 8406479Sgblack@eecs.umich.edu class Sld(RegOp): 8416479Sgblack@eecs.umich.edu code = ''' 8426479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8436479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 8446479Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 8456479Sgblack@eecs.umich.edu uint64_t result; 8466479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 8476479Sgblack@eecs.umich.edu result = psrc1; 8486479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 8496479Sgblack@eecs.umich.edu result = (psrc1 << realShiftAmt) | 8506479Sgblack@eecs.umich.edu (DoubleBits >> (dataBits - realShiftAmt)); 8516479Sgblack@eecs.umich.edu } else { 8526479Sgblack@eecs.umich.edu result = (DoubleBits << (realShiftAmt - dataBits)) | 8536479Sgblack@eecs.umich.edu (psrc1 >> (2 * dataBits - realShiftAmt)); 8546479Sgblack@eecs.umich.edu } 8556479Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 8566479Sgblack@eecs.umich.edu ''' 8576479Sgblack@eecs.umich.edu flag_code = ''' 8586479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8596479Sgblack@eecs.umich.edu if (shiftAmt) { 8606479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8616479Sgblack@eecs.umich.edu //worry about setting them. 8626479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8636479Sgblack@eecs.umich.edu int CFBits = 0; 8646479Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 8656479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 8666479Sgblack@eecs.umich.edu bits(DoubleBits, 0)) || 8676479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 8686479Sgblack@eecs.umich.edu bits(SrcReg1, dataBits - realShiftAmt)) || 8696479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 8706479Sgblack@eecs.umich.edu bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 8716479Sgblack@eecs.umich.edu CFBits = 1; 8726479Sgblack@eecs.umich.edu } 8736479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8746479Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 8756479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8766479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8776479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 8786479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 8796479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8806479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8816479Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8826479Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8836479Sgblack@eecs.umich.edu } 8846479Sgblack@eecs.umich.edu ''' 8856479Sgblack@eecs.umich.edu 8866479Sgblack@eecs.umich.edu class Srd(RegOp): 8876479Sgblack@eecs.umich.edu code = ''' 8886479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8896479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 8906479Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 8916479Sgblack@eecs.umich.edu uint64_t result; 8926479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 8936479Sgblack@eecs.umich.edu result = psrc1; 8946479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 8956479Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right 8966479Sgblack@eecs.umich.edu // shift is not defined in the C/C++ standard, we have to 8976479Sgblack@eecs.umich.edu // mask them out to be sure they're zero. 8986479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataBits - realShiftAmt); 8996479Sgblack@eecs.umich.edu result = ((psrc1 >> realShiftAmt) & logicalMask) | 9006479Sgblack@eecs.umich.edu (DoubleBits << (dataBits - realShiftAmt)); 9016479Sgblack@eecs.umich.edu } else { 9026479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 9036479Sgblack@eecs.umich.edu result = ((DoubleBits >> (realShiftAmt - dataBits)) & 9046479Sgblack@eecs.umich.edu logicalMask) | 9056479Sgblack@eecs.umich.edu (psrc1 << (2 * dataBits - realShiftAmt)); 9066479Sgblack@eecs.umich.edu } 9076479Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 9086479Sgblack@eecs.umich.edu ''' 9096479Sgblack@eecs.umich.edu flag_code = ''' 9106479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9116479Sgblack@eecs.umich.edu if (shiftAmt) { 9126479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9136479Sgblack@eecs.umich.edu //worry about setting them. 9146479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 9156479Sgblack@eecs.umich.edu int CFBits = 0; 9166479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9176479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 9186479Sgblack@eecs.umich.edu bits(DoubleBits, dataBits - 1)) || 9196479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 9206479Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) || 9216479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 9226479Sgblack@eecs.umich.edu bits(DoubleBits, realShiftAmt - dataBits - 1))) { 9236479Sgblack@eecs.umich.edu CFBits = 1; 9246479Sgblack@eecs.umich.edu } 9256479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9266479Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 9276479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 9286479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9296479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 9306479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 9316479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 9326479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9336479Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 9346479Sgblack@eecs.umich.edu DestReg, psrc1, op2); 9356479Sgblack@eecs.umich.edu } 9366479Sgblack@eecs.umich.edu ''' 9376479Sgblack@eecs.umich.edu 9386479Sgblack@eecs.umich.edu class Mdb(WrRegOp): 9396479Sgblack@eecs.umich.edu code = 'DoubleBits = psrc1 ^ op2;' 9406479Sgblack@eecs.umich.edu 9415040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 9425246Sgblack@eecs.umich.edu code = 'RIP = psrc1 + sop2 + CSBase' 9435040Sgblack@eecs.umich.edu else_code="RIP = RIP;" 9445040Sgblack@eecs.umich.edu 9455040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 9465040Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 9475040Sgblack@eecs.umich.edu 9485426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 9495426Sgblack@eecs.umich.edu code = ''' 9505426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 9515426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 9525426Sgblack@eecs.umich.edu // Get only the user flags 9535426Sgblack@eecs.umich.edu ccFlagBits = newFlags & userFlagMask; 9545426Sgblack@eecs.umich.edu // Get everything else 9555426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 9565426Sgblack@eecs.umich.edu ''' 9575426Sgblack@eecs.umich.edu 9585040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 9595246Sgblack@eecs.umich.edu code = 'DestReg = RIP - CSBase' 9605040Sgblack@eecs.umich.edu 9615040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 9625040Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 9635040Sgblack@eecs.umich.edu 9645426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 9655426Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits | nccFlagBits' 9665426Sgblack@eecs.umich.edu 9675040Sgblack@eecs.umich.edu class Ruflag(RegOp): 9685040Sgblack@eecs.umich.edu code = ''' 9695116Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8); 9704951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 9715011Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 9725011Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 9735040Sgblack@eecs.umich.edu ''' 9745040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 9755040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 9765040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 9776345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 9784732Sgblack@eecs.umich.edu 9795426Sgblack@eecs.umich.edu class Rflag(RegOp): 9805426Sgblack@eecs.umich.edu code = ''' 9815426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 9825426Sgblack@eecs.umich.edu MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 9835426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 9845426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 9855426Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 9865426Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 9875426Sgblack@eecs.umich.edu ''' 9885426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 9895426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 9905426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 9916345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 9925426Sgblack@eecs.umich.edu 9935040Sgblack@eecs.umich.edu class Sext(RegOp): 9945040Sgblack@eecs.umich.edu code = ''' 9954823Sgblack@eecs.umich.edu IntReg val = psrc1; 9965239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 9975239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 9985239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 9995239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 10005007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 10015007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 10025040Sgblack@eecs.umich.edu ''' 10035239Sgblack@eecs.umich.edu flag_code = ''' 10045239Sgblack@eecs.umich.edu if (!sign_bit) 10055239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & 10065239Sgblack@eecs.umich.edu ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 10075239Sgblack@eecs.umich.edu else 10085239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | 10095239Sgblack@eecs.umich.edu (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 10105239Sgblack@eecs.umich.edu ''' 10114714Sgblack@eecs.umich.edu 10125040Sgblack@eecs.umich.edu class Zext(RegOp): 10135927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 10145241Sgblack@eecs.umich.edu 10155926Sgblack@eecs.umich.edu class Rddr(RegOp): 10165926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10175926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 10186345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10195926Sgblack@eecs.umich.edu code = ''' 10205926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 10215926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 10225926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 10235926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 10245926Sgblack@eecs.umich.edu } else if (dr7.gd) { 10255926Sgblack@eecs.umich.edu fault = new DebugException(); 10265926Sgblack@eecs.umich.edu } else { 10275926Sgblack@eecs.umich.edu DestReg = merge(DestReg, DebugSrc1, dataSize); 10285926Sgblack@eecs.umich.edu } 10295926Sgblack@eecs.umich.edu ''' 10305926Sgblack@eecs.umich.edu 10315926Sgblack@eecs.umich.edu class Wrdr(RegOp): 10325926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10335926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 10346345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10355926Sgblack@eecs.umich.edu code = ''' 10365926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 10375926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 10385926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 10395926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 10406345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 10415926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 10425926Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 10435926Sgblack@eecs.umich.edu } else if (dr7.gd) { 10445926Sgblack@eecs.umich.edu fault = new DebugException(); 10455926Sgblack@eecs.umich.edu } else { 10465926Sgblack@eecs.umich.edu DebugDest = psrc1; 10475926Sgblack@eecs.umich.edu } 10485926Sgblack@eecs.umich.edu ''' 10495926Sgblack@eecs.umich.edu 10505296Sgblack@eecs.umich.edu class Rdcr(RegOp): 10515296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10525296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 10536345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10545296Sgblack@eecs.umich.edu code = ''' 10555924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 10565296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 10575296Sgblack@eecs.umich.edu } else { 10585934Sgblack@eecs.umich.edu DestReg = merge(DestReg, ControlSrc1, dataSize); 10595296Sgblack@eecs.umich.edu } 10605296Sgblack@eecs.umich.edu ''' 10615296Sgblack@eecs.umich.edu 10625241Sgblack@eecs.umich.edu class Wrcr(RegOp): 10635241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10645241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 10656345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10665241Sgblack@eecs.umich.edu code = ''' 10675241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 10685241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 10695241Sgblack@eecs.umich.edu } else { 10705241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 10715241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 10725241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 10735241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 10745241Sgblack@eecs.umich.edu 10755241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 10765241Sgblack@eecs.umich.edu switch(dest) { 10775241Sgblack@eecs.umich.edu case 0: 10785241Sgblack@eecs.umich.edu { 10795241Sgblack@eecs.umich.edu Efer efer = EferOp; 10805241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 10815241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 10825241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 10835241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 10845241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 10855241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 10865241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 10875241Sgblack@eecs.umich.edu } 10885241Sgblack@eecs.umich.edu break; 10895241Sgblack@eecs.umich.edu case 2: 10905241Sgblack@eecs.umich.edu break; 10915241Sgblack@eecs.umich.edu case 3: 10925241Sgblack@eecs.umich.edu break; 10935241Sgblack@eecs.umich.edu case 4: 10945241Sgblack@eecs.umich.edu { 10955241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 10965241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 10975241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 10985241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 10995241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11005241Sgblack@eecs.umich.edu } 11015241Sgblack@eecs.umich.edu break; 11025241Sgblack@eecs.umich.edu case 8: 11035241Sgblack@eecs.umich.edu { 11045241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 11055241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11065241Sgblack@eecs.umich.edu } 11075241Sgblack@eecs.umich.edu default: 11085241Sgblack@eecs.umich.edu panic("Unrecognized control register %d.\\n", dest); 11095241Sgblack@eecs.umich.edu } 11105241Sgblack@eecs.umich.edu ControlDest = newVal; 11115241Sgblack@eecs.umich.edu } 11125241Sgblack@eecs.umich.edu ''' 11135290Sgblack@eecs.umich.edu 11145294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 11155672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 11165294Sgblack@eecs.umich.edu abstract = True 11175290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11185294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 11196345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11205294Sgblack@eecs.umich.edu 11215294Sgblack@eecs.umich.edu class Wrbase(SegOp): 11225290Sgblack@eecs.umich.edu code = ''' 11235294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 11245290Sgblack@eecs.umich.edu ''' 11255290Sgblack@eecs.umich.edu 11265294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 11275290Sgblack@eecs.umich.edu code = ''' 11285294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 11295294Sgblack@eecs.umich.edu ''' 11305294Sgblack@eecs.umich.edu 11315294Sgblack@eecs.umich.edu class Wrsel(SegOp): 11325294Sgblack@eecs.umich.edu code = ''' 11335294Sgblack@eecs.umich.edu SegSelDest = psrc1; 11345294Sgblack@eecs.umich.edu ''' 11355294Sgblack@eecs.umich.edu 11365905Sgblack@eecs.umich.edu class WrAttr(SegOp): 11375905Sgblack@eecs.umich.edu code = ''' 11385905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 11395905Sgblack@eecs.umich.edu ''' 11405905Sgblack@eecs.umich.edu 11415294Sgblack@eecs.umich.edu class Rdbase(SegOp): 11425294Sgblack@eecs.umich.edu code = ''' 11435932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegBaseSrc1, dataSize); 11445294Sgblack@eecs.umich.edu ''' 11455294Sgblack@eecs.umich.edu 11465294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 11475294Sgblack@eecs.umich.edu code = ''' 11485932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegLimitSrc1, dataSize); 11495294Sgblack@eecs.umich.edu ''' 11505294Sgblack@eecs.umich.edu 11515427Sgblack@eecs.umich.edu class RdAttr(SegOp): 11525427Sgblack@eecs.umich.edu code = ''' 11535932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegAttrSrc1, dataSize); 11545427Sgblack@eecs.umich.edu ''' 11555427Sgblack@eecs.umich.edu 11565294Sgblack@eecs.umich.edu class Rdsel(SegOp): 11575294Sgblack@eecs.umich.edu code = ''' 11585932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegSelSrc1, dataSize); 11595294Sgblack@eecs.umich.edu ''' 11605294Sgblack@eecs.umich.edu 11615682Sgblack@eecs.umich.edu class Rdval(RegOp): 11625682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11636345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 11646345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11655682Sgblack@eecs.umich.edu code = ''' 11665682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 11675682Sgblack@eecs.umich.edu ''' 11685682Sgblack@eecs.umich.edu 11695682Sgblack@eecs.umich.edu class Wrval(RegOp): 11705682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11716345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 11726345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11735682Sgblack@eecs.umich.edu code = ''' 11745682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 11755682Sgblack@eecs.umich.edu ''' 11765682Sgblack@eecs.umich.edu 11775428Sgblack@eecs.umich.edu class Chks(RegOp): 11785428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 11795428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 11805428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 11815428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 11825294Sgblack@eecs.umich.edu code = ''' 11835424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 11845433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 11855433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 11865433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 11875294Sgblack@eecs.umich.edu 11885428Sgblack@eecs.umich.edu switch (imm8) 11895428Sgblack@eecs.umich.edu { 11905428Sgblack@eecs.umich.edu case SegNoCheck: 11915428Sgblack@eecs.umich.edu break; 11925428Sgblack@eecs.umich.edu case SegCSCheck: 11936060Sgblack@eecs.umich.edu // Make sure it's the right type 11946060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 11956060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11966060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 11976060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11986060Sgblack@eecs.umich.edu } 11995428Sgblack@eecs.umich.edu break; 12005428Sgblack@eecs.umich.edu case SegCallGateCheck: 12015428Sgblack@eecs.umich.edu panic("CS checks for far calls/jumps through call gates" 12025428Sgblack@eecs.umich.edu "not implemented.\\n"); 12035428Sgblack@eecs.umich.edu break; 12045855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 12055853Sgblack@eecs.umich.edu // Check permissions. 12065674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 12075857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12086058Sgblack@eecs.umich.edu break; 12095674Sgblack@eecs.umich.edu } 12105855Sgblack@eecs.umich.edu // Fall through on purpose 12115855Sgblack@eecs.umich.edu case SegIntGateCheck: 12125853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 12135861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 12145853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 12155853Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12165853Sgblack@eecs.umich.edu } 12175674Sgblack@eecs.umich.edu break; 12185428Sgblack@eecs.umich.edu case SegSSCheck: 12195433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 12205433Sgblack@eecs.umich.edu if (!desc.p) { 12215857Sgblack@eecs.umich.edu fault = new StackFault(selector); 12225433Sgblack@eecs.umich.edu } 12235433Sgblack@eecs.umich.edu } else { 12245673Sgblack@eecs.umich.edu if ((m5reg.submode != SixtyFourBitMode || 12255673Sgblack@eecs.umich.edu m5reg.cpl == 3) || 12265433Sgblack@eecs.umich.edu !(desc.s == 1 && 12275433Sgblack@eecs.umich.edu desc.type.codeOrData == 0 && desc.type.w) || 12285433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 12295433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 12305857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12315433Sgblack@eecs.umich.edu } 12325433Sgblack@eecs.umich.edu } 12335428Sgblack@eecs.umich.edu break; 12345428Sgblack@eecs.umich.edu case SegIretCheck: 12355428Sgblack@eecs.umich.edu { 12365433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 12375433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 12385433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 12395433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 12405679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 12415857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12425679Sgblack@eecs.umich.edu } else if (!desc.p) { 12435857Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 12445679Sgblack@eecs.umich.edu } 12455428Sgblack@eecs.umich.edu break; 12465428Sgblack@eecs.umich.edu } 12475428Sgblack@eecs.umich.edu case SegIntCSCheck: 12485675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 12495675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 12505679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12515675Sgblack@eecs.umich.edu } 12525675Sgblack@eecs.umich.edu } else { 12535675Sgblack@eecs.umich.edu panic("Interrupt CS checks not implemented " 12545675Sgblack@eecs.umich.edu "in legacy mode.\\n"); 12555675Sgblack@eecs.umich.edu } 12565428Sgblack@eecs.umich.edu break; 12575899Sgblack@eecs.umich.edu case SegTRCheck: 12585899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 12595899Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12605899Sgblack@eecs.umich.edu } 12615899Sgblack@eecs.umich.edu break; 12625900Sgblack@eecs.umich.edu case SegTSSCheck: 12635900Sgblack@eecs.umich.edu if (!desc.p) { 12645900Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 12655900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 12665900Sgblack@eecs.umich.edu (desc.type == 1 && 12675900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 12685935Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12695900Sgblack@eecs.umich.edu } 12705900Sgblack@eecs.umich.edu break; 12715936Sgblack@eecs.umich.edu case SegInGDTCheck: 12725936Sgblack@eecs.umich.edu if (selector.ti) { 12735936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12745936Sgblack@eecs.umich.edu } 12755936Sgblack@eecs.umich.edu break; 12765936Sgblack@eecs.umich.edu case SegLDTCheck: 12775936Sgblack@eecs.umich.edu if (!desc.p) { 12785936Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 12795936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 12805936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12815936Sgblack@eecs.umich.edu } 12825936Sgblack@eecs.umich.edu break; 12835428Sgblack@eecs.umich.edu default: 12845428Sgblack@eecs.umich.edu panic("Undefined segment check type.\\n"); 12855428Sgblack@eecs.umich.edu } 12865294Sgblack@eecs.umich.edu ''' 12875294Sgblack@eecs.umich.edu flag_code = ''' 12885294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 12895294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 12905424Sgblack@eecs.umich.edu if (!selector.si && !selector.ti) 12915294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 12925294Sgblack@eecs.umich.edu ''' 12935294Sgblack@eecs.umich.edu 12945294Sgblack@eecs.umich.edu class Wrdh(RegOp): 12955294Sgblack@eecs.umich.edu code = ''' 12965678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 12975294Sgblack@eecs.umich.edu 12985678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 12995678Sgblack@eecs.umich.edu switch(desc.type) { 13005678Sgblack@eecs.umich.edu case LDT64: 13015678Sgblack@eecs.umich.edu case AvailableTSS64: 13025678Sgblack@eecs.umich.edu case BusyTSS64: 13035678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 13045678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 13055678Sgblack@eecs.umich.edu break; 13065678Sgblack@eecs.umich.edu case CallGate64: 13075678Sgblack@eecs.umich.edu case IntGate64: 13085678Sgblack@eecs.umich.edu case TrapGate64: 13095678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 13105678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 13115678Sgblack@eecs.umich.edu break; 13125678Sgblack@eecs.umich.edu default: 13135678Sgblack@eecs.umich.edu panic("Wrdh used with wrong descriptor type!\\n"); 13145678Sgblack@eecs.umich.edu } 13155678Sgblack@eecs.umich.edu DestReg = target; 13165294Sgblack@eecs.umich.edu ''' 13175294Sgblack@eecs.umich.edu 13185409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 13195409Sgblack@eecs.umich.edu code = ''' 13205409Sgblack@eecs.umich.edu TscOp = psrc1; 13215409Sgblack@eecs.umich.edu ''' 13225409Sgblack@eecs.umich.edu 13235409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 13245409Sgblack@eecs.umich.edu code = ''' 13255409Sgblack@eecs.umich.edu DestReg = TscOp; 13265409Sgblack@eecs.umich.edu ''' 13275409Sgblack@eecs.umich.edu 13285429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 13295429Sgblack@eecs.umich.edu code = ''' 13305429Sgblack@eecs.umich.edu DestReg = M5Reg; 13315429Sgblack@eecs.umich.edu ''' 13325429Sgblack@eecs.umich.edu 13335294Sgblack@eecs.umich.edu class Wrdl(RegOp): 13345294Sgblack@eecs.umich.edu code = ''' 13355294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 13365433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 13375433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 13386222Sgblack@eecs.umich.edu if (!desc.p) 13396222Sgblack@eecs.umich.edu panic("Segment not present.\\n"); 13405433Sgblack@eecs.umich.edu SegAttr attr = 0; 13415433Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 13426222Sgblack@eecs.umich.edu attr.unusable = 0; 13435433Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 13446222Sgblack@eecs.umich.edu attr.longMode = desc.l; 13456222Sgblack@eecs.umich.edu attr.avl = desc.avl; 13466222Sgblack@eecs.umich.edu attr.granularity = desc.g; 13476222Sgblack@eecs.umich.edu attr.present = desc.p; 13486222Sgblack@eecs.umich.edu attr.system = desc.s; 13496222Sgblack@eecs.umich.edu attr.type = desc.type; 13505433Sgblack@eecs.umich.edu if (!desc.s) { 13515901Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 13525901Sgblack@eecs.umich.edu if (desc.type.e) { 13535901Sgblack@eecs.umich.edu panic("Gate descriptor encountered.\\n"); 13545901Sgblack@eecs.umich.edu } 13555901Sgblack@eecs.umich.edu attr.readable = 1; 13565901Sgblack@eecs.umich.edu attr.writable = 1; 13576222Sgblack@eecs.umich.edu attr.expandDown = 0; 13585433Sgblack@eecs.umich.edu } else { 13595433Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 13606222Sgblack@eecs.umich.edu attr.expandDown = 0; 13615433Sgblack@eecs.umich.edu attr.readable = desc.type.r; 13626222Sgblack@eecs.umich.edu attr.writable = 0; 13635433Sgblack@eecs.umich.edu } else { 13645433Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 13655433Sgblack@eecs.umich.edu attr.readable = 1; 13665433Sgblack@eecs.umich.edu attr.writable = desc.type.w; 13675433Sgblack@eecs.umich.edu } 13685433Sgblack@eecs.umich.edu } 13695901Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 13705901Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 13715901Sgblack@eecs.umich.edu if (desc.g) 13725901Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 13735901Sgblack@eecs.umich.edu SegBaseDest = base; 13745901Sgblack@eecs.umich.edu SegLimitDest = limit; 13755901Sgblack@eecs.umich.edu SegAttrDest = attr; 13765433Sgblack@eecs.umich.edu } else { 13775295Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 13785295Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 13795295Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 13805294Sgblack@eecs.umich.edu } 13815290Sgblack@eecs.umich.edu ''' 13824519Sgblack@eecs.umich.edu}}; 1383