regop.isa revision 7087
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 124519Sgblack@eecs.umich.edu// 137087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 147087Snate@binkert.org// modification, are permitted provided that the following conditions are 157087Snate@binkert.org// met: redistributions of source code must retain the above copyright 167087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org// documentation and/or other materials provided with the distribution; 207087Snate@binkert.org// neither the name of the copyright holders nor the names of its 214519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227087Snate@binkert.org// this software without specific prior written permission. 234519Sgblack@eecs.umich.edu// 244519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354519Sgblack@eecs.umich.edu// 364519Sgblack@eecs.umich.edu// Authors: Gabe Black 374519Sgblack@eecs.umich.edu 384519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 394519Sgblack@eecs.umich.edu// 404519Sgblack@eecs.umich.edu// RegOp Microop templates 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 434519Sgblack@eecs.umich.edu 444519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 454519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 464519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474519Sgblack@eecs.umich.edu { 484519Sgblack@eecs.umich.edu Fault fault = NoFault; 494519Sgblack@eecs.umich.edu 504809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 514519Sgblack@eecs.umich.edu %(op_decl)s; 524519Sgblack@eecs.umich.edu %(op_rd)s; 534688Sgblack@eecs.umich.edu 544688Sgblack@eecs.umich.edu if(%(cond_check)s) 554688Sgblack@eecs.umich.edu { 564688Sgblack@eecs.umich.edu %(code)s; 574688Sgblack@eecs.umich.edu %(flag_code)s; 584688Sgblack@eecs.umich.edu } 594708Sgblack@eecs.umich.edu else 604708Sgblack@eecs.umich.edu { 614708Sgblack@eecs.umich.edu %(else_code)s; 624708Sgblack@eecs.umich.edu } 634519Sgblack@eecs.umich.edu 644519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 654519Sgblack@eecs.umich.edu if(fault == NoFault) 664519Sgblack@eecs.umich.edu { 674519Sgblack@eecs.umich.edu %(op_wb)s; 684519Sgblack@eecs.umich.edu } 694519Sgblack@eecs.umich.edu return fault; 704519Sgblack@eecs.umich.edu } 714519Sgblack@eecs.umich.edu}}; 724519Sgblack@eecs.umich.edu 734519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 744951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 754519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 764519Sgblack@eecs.umich.edu { 774519Sgblack@eecs.umich.edu Fault fault = NoFault; 784519Sgblack@eecs.umich.edu 794519Sgblack@eecs.umich.edu %(op_decl)s; 804519Sgblack@eecs.umich.edu %(op_rd)s; 814688Sgblack@eecs.umich.edu 824688Sgblack@eecs.umich.edu if(%(cond_check)s) 834688Sgblack@eecs.umich.edu { 844688Sgblack@eecs.umich.edu %(code)s; 854688Sgblack@eecs.umich.edu %(flag_code)s; 864688Sgblack@eecs.umich.edu } 874708Sgblack@eecs.umich.edu else 884708Sgblack@eecs.umich.edu { 894708Sgblack@eecs.umich.edu %(else_code)s; 904708Sgblack@eecs.umich.edu } 914519Sgblack@eecs.umich.edu 924519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 934519Sgblack@eecs.umich.edu if(fault == NoFault) 944519Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu %(op_wb)s; 964519Sgblack@eecs.umich.edu } 974519Sgblack@eecs.umich.edu return fault; 984519Sgblack@eecs.umich.edu } 994519Sgblack@eecs.umich.edu}}; 1004519Sgblack@eecs.umich.edu 1014519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1024519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1034519Sgblack@eecs.umich.edu { 1044519Sgblack@eecs.umich.edu protected: 1054519Sgblack@eecs.umich.edu void buildMe(); 1064519Sgblack@eecs.umich.edu 1074519Sgblack@eecs.umich.edu public: 1084519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1094519Sgblack@eecs.umich.edu const char * instMnem, 1104519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1116345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1124712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1134519Sgblack@eecs.umich.edu 1144519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1154519Sgblack@eecs.umich.edu const char * instMnem, 1166345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1174712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1184519Sgblack@eecs.umich.edu 1194519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1204519Sgblack@eecs.umich.edu }; 1214519Sgblack@eecs.umich.edu}}; 1224519Sgblack@eecs.umich.edu 1234519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1244519Sgblack@eecs.umich.edu 1254951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1264519Sgblack@eecs.umich.edu { 1274519Sgblack@eecs.umich.edu protected: 1284519Sgblack@eecs.umich.edu void buildMe(); 1294519Sgblack@eecs.umich.edu 1304519Sgblack@eecs.umich.edu public: 1314951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1324519Sgblack@eecs.umich.edu const char * instMnem, 1334519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1346646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1354712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1364519Sgblack@eecs.umich.edu 1374951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1384519Sgblack@eecs.umich.edu const char * instMnem, 1396646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1404712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1414519Sgblack@eecs.umich.edu 1424519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1434519Sgblack@eecs.umich.edu }; 1444519Sgblack@eecs.umich.edu}}; 1454519Sgblack@eecs.umich.edu 1464519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1474519Sgblack@eecs.umich.edu 1484519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1494519Sgblack@eecs.umich.edu { 1504519Sgblack@eecs.umich.edu %(constructor)s; 1514519Sgblack@eecs.umich.edu } 1524519Sgblack@eecs.umich.edu 1534519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1544519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1556345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1564712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1574519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1584581Sgblack@eecs.umich.edu false, false, false, false, 1594688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1604581Sgblack@eecs.umich.edu %(op_class)s) 1614519Sgblack@eecs.umich.edu { 1624519Sgblack@eecs.umich.edu buildMe(); 1634519Sgblack@eecs.umich.edu } 1644519Sgblack@eecs.umich.edu 1654519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1664519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1674519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1686345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1694712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1704519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1714581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1724688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1734581Sgblack@eecs.umich.edu %(op_class)s) 1744519Sgblack@eecs.umich.edu { 1754519Sgblack@eecs.umich.edu buildMe(); 1764519Sgblack@eecs.umich.edu } 1774519Sgblack@eecs.umich.edu}}; 1784519Sgblack@eecs.umich.edu 1794519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1804519Sgblack@eecs.umich.edu 1814951Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1824519Sgblack@eecs.umich.edu { 1834519Sgblack@eecs.umich.edu %(constructor)s; 1844519Sgblack@eecs.umich.edu } 1854519Sgblack@eecs.umich.edu 1864951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1874519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1886646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1894712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1904519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1914581Sgblack@eecs.umich.edu false, false, false, false, 1924688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 1934581Sgblack@eecs.umich.edu %(op_class)s) 1944519Sgblack@eecs.umich.edu { 1954519Sgblack@eecs.umich.edu buildMe(); 1964519Sgblack@eecs.umich.edu } 1974519Sgblack@eecs.umich.edu 1984951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1994519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2004519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2016646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 2024712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2034519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2044581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2054688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2064581Sgblack@eecs.umich.edu %(op_class)s) 2074519Sgblack@eecs.umich.edu { 2084519Sgblack@eecs.umich.edu buildMe(); 2094519Sgblack@eecs.umich.edu } 2104519Sgblack@eecs.umich.edu}}; 2114519Sgblack@eecs.umich.edu 2125075Sgblack@eecs.umich.eduoutput header {{ 2135075Sgblack@eecs.umich.edu void 2145075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2155075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 2165428Sgblack@eecs.umich.edu 2175428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 2185674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 2195899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 2205936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 2215428Sgblack@eecs.umich.edu }; 2225678Sgblack@eecs.umich.edu 2235678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 2245678Sgblack@eecs.umich.edu LDT64 = 2, 2255678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 2265678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 2275678Sgblack@eecs.umich.edu CallGate64 = 0xc, 2285678Sgblack@eecs.umich.edu IntGate64 = 0xe, 2295678Sgblack@eecs.umich.edu TrapGate64 = 0xf 2305678Sgblack@eecs.umich.edu }; 2315075Sgblack@eecs.umich.edu}}; 2325075Sgblack@eecs.umich.edu 2335075Sgblack@eecs.umich.eduoutput decoder {{ 2345075Sgblack@eecs.umich.edu void 2355075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2365075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 2375075Sgblack@eecs.umich.edu { 2385075Sgblack@eecs.umich.edu //Check for divide by zero. 2395075Sgblack@eecs.umich.edu if (divisor == 0) 2405075Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 2415075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 2425075Sgblack@eecs.umich.edu if (divisor <= dividend) { 2435075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 2445075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 2455075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 2465075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 2475075Sgblack@eecs.umich.edu divisor <<= shift; 2485075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 2495075Sgblack@eecs.umich.edu //now larger than the dividend. 2505075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 2515075Sgblack@eecs.umich.edu quotientBit <<= shift; 2525075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2535075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2545075Sgblack@eecs.umich.edu //part of one or two bit division. 2555075Sgblack@eecs.umich.edu if (divisor > dividend) { 2565075Sgblack@eecs.umich.edu quotientBit >>= 1; 2575075Sgblack@eecs.umich.edu divisor >>= 1; 2585075Sgblack@eecs.umich.edu } 2595075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2605075Sgblack@eecs.umich.edu quotient += quotientBit; 2615075Sgblack@eecs.umich.edu remainder -= divisor; 2625075Sgblack@eecs.umich.edu } 2635075Sgblack@eecs.umich.edu } 2645075Sgblack@eecs.umich.edu}}; 2655075Sgblack@eecs.umich.edu 2664519Sgblack@eecs.umich.edulet {{ 2675040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2685040Sgblack@eecs.umich.edu # them will always work. 2695040Sgblack@eecs.umich.edu header_output = "" 2705040Sgblack@eecs.umich.edu decoder_output = "" 2715040Sgblack@eecs.umich.edu exec_output = "" 2725040Sgblack@eecs.umich.edu 2735040Sgblack@eecs.umich.edu immTemplates = ( 2745040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2755040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2765040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2775040Sgblack@eecs.umich.edu 2785040Sgblack@eecs.umich.edu regTemplates = ( 2795040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2805040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2815040Sgblack@eecs.umich.edu MicroRegOpExecute) 2825040Sgblack@eecs.umich.edu 2835040Sgblack@eecs.umich.edu class RegOpMeta(type): 2845040Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 2855040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code): 2865040Sgblack@eecs.umich.edu 2875040Sgblack@eecs.umich.edu # Globals to stick the output in 2885040Sgblack@eecs.umich.edu global header_output 2895040Sgblack@eecs.umich.edu global decoder_output 2905040Sgblack@eecs.umich.edu global exec_output 2915040Sgblack@eecs.umich.edu 2925040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2935040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 2945040Sgblack@eecs.umich.edu 2955040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2965040Sgblack@eecs.umich.edu # of this code. 2975062Sgblack@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 2985062Sgblack@eecs.umich.edu match = matcher.search(allCode) 2995062Sgblack@eecs.umich.edu if match: 3005062Sgblack@eecs.umich.edu typeQual = "" 3015062Sgblack@eecs.umich.edu if match.group("typeQual"): 3025062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 3035062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3045040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3055062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 3065062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 3075062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 3085062Sgblack@eecs.umich.edu matcher.sub(src2_name, else_code)) 3096647Sgblack@eecs.umich.edu imm_name = "%simm8" % match.group("prefix") 3105040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 3116647Sgblack@eecs.umich.edu matcher.sub(imm_name, code), 3126647Sgblack@eecs.umich.edu matcher.sub(imm_name, flag_code), 3136647Sgblack@eecs.umich.edu matcher.sub(imm_name, cond_check), 3146647Sgblack@eecs.umich.edu matcher.sub(imm_name, else_code)) 3155040Sgblack@eecs.umich.edu return 3165040Sgblack@eecs.umich.edu 3175040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 3185040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 3195239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 3205040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3215040Sgblack@eecs.umich.edu code, "", "true", else_code) 3225040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 3235040Sgblack@eecs.umich.edu 3245040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 3255040Sgblack@eecs.umich.edu # compute it. 3265040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 3275040Sgblack@eecs.umich.edu if matcher.search(allCode): 3285061Sgblack@eecs.umich.edu code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3295040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 3305040Sgblack@eecs.umich.edu if matcher.search(allCode): 3315061Sgblack@eecs.umich.edu code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3325061Sgblack@eecs.umich.edu # Also make available versions which do sign extension 3335061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3345061Sgblack@eecs.umich.edu if matcher.search(allCode): 3355061Sgblack@eecs.umich.edu code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3365061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3375061Sgblack@eecs.umich.edu if matcher.search(allCode): 3385061Sgblack@eecs.umich.edu code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3396647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)simm8(?!\w)") 3406647Sgblack@eecs.umich.edu if matcher.search(allCode): 3416647Sgblack@eecs.umich.edu code = "int8_t simm8 = imm8;" + code 3425040Sgblack@eecs.umich.edu 3435040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3445040Sgblack@eecs.umich.edu 3455040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3465040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3475040Sgblack@eecs.umich.edu templates = regTemplates 3486647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3495040Sgblack@eecs.umich.edu if matcher.search(allCode): 3505040Sgblack@eecs.umich.edu base += "Imm" 3515040Sgblack@eecs.umich.edu templates = immTemplates 3525040Sgblack@eecs.umich.edu 3535040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3545040Sgblack@eecs.umich.edu iop = InstObjParams(name, Name + suffix, base, 3555040Sgblack@eecs.umich.edu {"code" : code, 3565040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3575040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3585040Sgblack@eecs.umich.edu "else_code" : else_code}) 3595040Sgblack@eecs.umich.edu 3605040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3615040Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3625040Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3635040Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3645040Sgblack@eecs.umich.edu 3655040Sgblack@eecs.umich.edu 3665040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3674688Sgblack@eecs.umich.edu abstract = False 3685040Sgblack@eecs.umich.edu name = Name.lower() 3694688Sgblack@eecs.umich.edu if "abstract" in dict: 3704688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3714688Sgblack@eecs.umich.edu del dict['abstract'] 3724688Sgblack@eecs.umich.edu 3735040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3744688Sgblack@eecs.umich.edu if not abstract: 3755040Sgblack@eecs.umich.edu cls.className = Name 3765040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3775040Sgblack@eecs.umich.edu code = cls.code 3785040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3795040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3805040Sgblack@eecs.umich.edu else_code = cls.else_code 3815040Sgblack@eecs.umich.edu 3825040Sgblack@eecs.umich.edu # Set up the C++ classes 3835040Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", 3845040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code) 3855040Sgblack@eecs.umich.edu 3865040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3875040Sgblack@eecs.umich.edu global microopClasses 3885040Sgblack@eecs.umich.edu microopClasses[name] = cls 3895040Sgblack@eecs.umich.edu 3905040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3915040Sgblack@eecs.umich.edu 3925040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3935040Sgblack@eecs.umich.edu # of this code. 3945040Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3955040Sgblack@eecs.umich.edu if matcher.search(allCode): 3965040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3974688Sgblack@eecs.umich.edu return cls 3984688Sgblack@eecs.umich.edu 3995040Sgblack@eecs.umich.edu 4005040Sgblack@eecs.umich.edu class RegOp(X86Microop): 4015040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 4025040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 4034688Sgblack@eecs.umich.edu abstract = True 4044688Sgblack@eecs.umich.edu 4055040Sgblack@eecs.umich.edu # Default template parameter values 4065040Sgblack@eecs.umich.edu flag_code = "" 4075040Sgblack@eecs.umich.edu cond_check = "true" 4085040Sgblack@eecs.umich.edu else_code = ";" 4095040Sgblack@eecs.umich.edu 4105040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4114519Sgblack@eecs.umich.edu self.dest = dest 4124519Sgblack@eecs.umich.edu self.src1 = src1 4135040Sgblack@eecs.umich.edu self.op2 = op2 4144688Sgblack@eecs.umich.edu self.flags = flags 4154701Sgblack@eecs.umich.edu self.dataSize = dataSize 4164688Sgblack@eecs.umich.edu if flags is None: 4174688Sgblack@eecs.umich.edu self.ext = 0 4184688Sgblack@eecs.umich.edu else: 4194688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4204688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4214688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 4224688Sgblack@eecs.umich.edu self.className += "Flags" 4234519Sgblack@eecs.umich.edu 4244519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 4255040Sgblack@eecs.umich.edu className = self.className 4265040Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4275040Sgblack@eecs.umich.edu className += "Imm" 4285788Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock 4295040Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4304688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4315040Sgblack@eecs.umich.edu "class_name" : className, 4324519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4335040Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4344519Sgblack@eecs.umich.edu "dest" : self.dest, 4354519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4364519Sgblack@eecs.umich.edu "ext" : self.ext} 4374539Sgblack@eecs.umich.edu return allocator 4384519Sgblack@eecs.umich.edu 4395040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4404688Sgblack@eecs.umich.edu abstract = True 4415040Sgblack@eecs.umich.edu flag_code = ''' 4425040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4435115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4445040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4455040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4465040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 4475115Sgblack@eecs.umich.edu ccFlagBits &= ~(ECFBit & ext); 4485040Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 4495040Sgblack@eecs.umich.edu ''' 4504519Sgblack@eecs.umich.edu 4515040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4525040Sgblack@eecs.umich.edu abstract = True 4535040Sgblack@eecs.umich.edu flag_code = \ 4545040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4554519Sgblack@eecs.umich.edu 4565040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4575040Sgblack@eecs.umich.edu abstract = True 4585040Sgblack@eecs.umich.edu flag_code = \ 4595040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4604519Sgblack@eecs.umich.edu 4615040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4625040Sgblack@eecs.umich.edu abstract = True 4635083Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits, ext)" 4644519Sgblack@eecs.umich.edu 4655063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4665063Sgblack@eecs.umich.edu abstract = True 4675063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4685063Sgblack@eecs.umich.edu if not src1: 4695063Sgblack@eecs.umich.edu src1 = dest 4706345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4716345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4725063Sgblack@eecs.umich.edu 4735063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4745063Sgblack@eecs.umich.edu abstract = True 4755063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4766345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4776345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 4785063Sgblack@eecs.umich.edu 4795040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4805040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4814595Sgblack@eecs.umich.edu 4825040Sgblack@eecs.umich.edu class Or(LogicRegOp): 4835040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4844595Sgblack@eecs.umich.edu 4855040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 4865040Sgblack@eecs.umich.edu code = ''' 4874732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4885138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 4895040Sgblack@eecs.umich.edu ''' 4905040Sgblack@eecs.umich.edu 4915040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 4925040Sgblack@eecs.umich.edu code = ''' 4934732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4945138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 4955040Sgblack@eecs.umich.edu ''' 4965040Sgblack@eecs.umich.edu 4975040Sgblack@eecs.umich.edu class And(LogicRegOp): 4985040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 4995040Sgblack@eecs.umich.edu 5005040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5015040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 5025040Sgblack@eecs.umich.edu 5035040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5045040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 5055040Sgblack@eecs.umich.edu 5065063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5075040Sgblack@eecs.umich.edu code = ''' 5085063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5095063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5106742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5116430Sgblack@eecs.umich.edu uint64_t hiResult; 5126430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5136430Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5146461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5156430Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5166430Sgblack@eecs.umich.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5176430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 5186430Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5196462Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 5206430Sgblack@eecs.umich.edu hiResult -= op2; 5216462Sgblack@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 5226430Sgblack@eecs.umich.edu hiResult -= psrc1; 5236430Sgblack@eecs.umich.edu ProdHi = hiResult; 5245040Sgblack@eecs.umich.edu ''' 5256463Sgblack@eecs.umich.edu flag_code = ''' 5266463Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 5276463Sgblack@eecs.umich.edu bits(ProdLow, dataSize * 8 - 1)) { 5286463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5296463Sgblack@eecs.umich.edu } else { 5306463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5316463Sgblack@eecs.umich.edu } 5326463Sgblack@eecs.umich.edu ''' 5335040Sgblack@eecs.umich.edu 5345063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5355040Sgblack@eecs.umich.edu code = ''' 5365063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5374809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5386742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5396430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5405063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5416461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5425063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5435063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5446430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) / shifter) + 5455063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5465040Sgblack@eecs.umich.edu ''' 5476463Sgblack@eecs.umich.edu flag_code = ''' 5486463Sgblack@eecs.umich.edu if (ProdHi) { 5496463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5506463Sgblack@eecs.umich.edu } else { 5516463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5526463Sgblack@eecs.umich.edu } 5536463Sgblack@eecs.umich.edu ''' 5545040Sgblack@eecs.umich.edu 5555063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5565063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5575040Sgblack@eecs.umich.edu 5585063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5595063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5605063Sgblack@eecs.umich.edu if not src1: 5615063Sgblack@eecs.umich.edu src1 = dest 5626345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 5636345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 5645063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5655062Sgblack@eecs.umich.edu 5665075Sgblack@eecs.umich.edu # One or two bit divide 5675075Sgblack@eecs.umich.edu class Div1(WrRegOp): 5685040Sgblack@eecs.umich.edu code = ''' 5695075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 5705075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5715075Sgblack@eecs.umich.edu uint64_t quotient = 0; 5725075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 5735075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 5745075Sgblack@eecs.umich.edu //a source. 5755075Sgblack@eecs.umich.edu uint64_t divisor = op2; 5765075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 5775075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 5785075Sgblack@eecs.umich.edu //Do the division. 5795075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5805075Sgblack@eecs.umich.edu //Record the final results. 5815075Sgblack@eecs.umich.edu Remainder = remainder; 5825075Sgblack@eecs.umich.edu Quotient = quotient; 5835075Sgblack@eecs.umich.edu Divisor = divisor; 5845040Sgblack@eecs.umich.edu ''' 5854823Sgblack@eecs.umich.edu 5865075Sgblack@eecs.umich.edu # Step divide 5875075Sgblack@eecs.umich.edu class Div2(RegOp): 5885075Sgblack@eecs.umich.edu code = ''' 5895075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 5905075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 5915075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 5925075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 5935075Sgblack@eecs.umich.edu int remaining = op2; 5945075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 5955075Sgblack@eecs.umich.edu //little. 5965075Sgblack@eecs.umich.edu if (remaining) { 5977070Sgblack@eecs.umich.edu if (divisor & (ULL(1) << 63)) { 5987070Sgblack@eecs.umich.edu while (remaining && !(dividend & (ULL(1) << 63))) { 5997070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6007070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6017070Sgblack@eecs.umich.edu quotient <<= 1; 6027070Sgblack@eecs.umich.edu remaining--; 6037070Sgblack@eecs.umich.edu } 6047070Sgblack@eecs.umich.edu if (dividend & (ULL(1) << 63)) { 6057080Sgblack@eecs.umich.edu bool highBit = false; 6067070Sgblack@eecs.umich.edu if (dividend < divisor && remaining) { 6077080Sgblack@eecs.umich.edu highBit = true; 6087070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6097070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6107070Sgblack@eecs.umich.edu quotient <<= 1; 6117070Sgblack@eecs.umich.edu remaining--; 6127070Sgblack@eecs.umich.edu } 6137080Sgblack@eecs.umich.edu if (highBit || divisor <= dividend) { 6147080Sgblack@eecs.umich.edu quotient++; 6157080Sgblack@eecs.umich.edu dividend -= divisor; 6167080Sgblack@eecs.umich.edu } 6177070Sgblack@eecs.umich.edu } 6187070Sgblack@eecs.umich.edu remainder = dividend; 6197070Sgblack@eecs.umich.edu } else { 6207070Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 6217070Sgblack@eecs.umich.edu while (dividend < divisor && remaining) { 6227070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6237070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6247070Sgblack@eecs.umich.edu quotient <<= 1; 6257070Sgblack@eecs.umich.edu remaining--; 6267070Sgblack@eecs.umich.edu } 6277070Sgblack@eecs.umich.edu remainder = dividend; 6287070Sgblack@eecs.umich.edu //Do the division. 6297070Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6305075Sgblack@eecs.umich.edu } 6315075Sgblack@eecs.umich.edu } 6325075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 6335075Sgblack@eecs.umich.edu DestReg = merge(DestReg, remaining, dataSize); 6345075Sgblack@eecs.umich.edu //Record the final results 6355075Sgblack@eecs.umich.edu Remainder = remainder; 6365075Sgblack@eecs.umich.edu Quotient = quotient; 6375075Sgblack@eecs.umich.edu ''' 6385075Sgblack@eecs.umich.edu flag_code = ''' 6395075Sgblack@eecs.umich.edu if (DestReg == 0) 6405075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & EZFBit); 6415075Sgblack@eecs.umich.edu else 6425075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6435075Sgblack@eecs.umich.edu ''' 6444732Sgblack@eecs.umich.edu 6455075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6465075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6475075Sgblack@eecs.umich.edu 6485075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6495075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6505040Sgblack@eecs.umich.edu 6515040Sgblack@eecs.umich.edu class Mov(CondRegOp): 6525040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6536482Sgblack@eecs.umich.edu else_code = 'DestReg = DestReg;' 6545040Sgblack@eecs.umich.edu 6554732Sgblack@eecs.umich.edu # Shift instructions 6565040Sgblack@eecs.umich.edu 6575076Sgblack@eecs.umich.edu class Sll(RegOp): 6585040Sgblack@eecs.umich.edu code = ''' 6594756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6604823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6615040Sgblack@eecs.umich.edu ''' 6625076Sgblack@eecs.umich.edu flag_code = ''' 6635076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6645076Sgblack@eecs.umich.edu if (shiftAmt) { 6655076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6665076Sgblack@eecs.umich.edu //worry about setting them. 6675076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6685076Sgblack@eecs.umich.edu int CFBits = 0; 6695076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 6706441Sgblack@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 6716441Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 6725076Sgblack@eecs.umich.edu CFBits = 1; 6736441Sgblack@eecs.umich.edu } 6745076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6755076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 6765076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6775076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6785076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 6795076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6805076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6815076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6825076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6835076Sgblack@eecs.umich.edu } 6845076Sgblack@eecs.umich.edu ''' 6855040Sgblack@eecs.umich.edu 6865076Sgblack@eecs.umich.edu class Srl(RegOp): 6875040Sgblack@eecs.umich.edu code = ''' 6884756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6894732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6904732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 6914732Sgblack@eecs.umich.edu // to be sure they're zero. 6924732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 6934823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 6945040Sgblack@eecs.umich.edu ''' 6955076Sgblack@eecs.umich.edu flag_code = ''' 6965076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6975076Sgblack@eecs.umich.edu if (shiftAmt) { 6985076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6995076Sgblack@eecs.umich.edu //worry about setting them. 7005076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7015076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7026442Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7036442Sgblack@eecs.umich.edu shiftAmt <= dataSize * 8 && 7046442Sgblack@eecs.umich.edu bits(SrcReg1, shiftAmt - 1)) { 7055076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7066442Sgblack@eecs.umich.edu } 7075076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7085076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 7095076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7105076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7115076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7125076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7135076Sgblack@eecs.umich.edu } 7145076Sgblack@eecs.umich.edu ''' 7155040Sgblack@eecs.umich.edu 7165076Sgblack@eecs.umich.edu class Sra(RegOp): 7175040Sgblack@eecs.umich.edu code = ''' 7184756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7194732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 7204732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 7214732Sgblack@eecs.umich.edu // them manually to be sure. 7226443Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 7235032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 7244823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 7255040Sgblack@eecs.umich.edu ''' 7265076Sgblack@eecs.umich.edu flag_code = ''' 7275076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7285076Sgblack@eecs.umich.edu if (shiftAmt) { 7295076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7305076Sgblack@eecs.umich.edu //worry about setting them. 7315076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7325076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7336444Sgblack@eecs.umich.edu uint8_t effectiveShift = 7346444Sgblack@eecs.umich.edu (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 7356444Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7366444Sgblack@eecs.umich.edu bits(SrcReg1, effectiveShift - 1)) { 7375076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7386444Sgblack@eecs.umich.edu } 7395076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7405076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7415076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7425076Sgblack@eecs.umich.edu } 7435076Sgblack@eecs.umich.edu ''' 7445040Sgblack@eecs.umich.edu 7455076Sgblack@eecs.umich.edu class Ror(RegOp): 7465040Sgblack@eecs.umich.edu code = ''' 7474732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7484756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7496449Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 7506449Sgblack@eecs.umich.edu if(realShiftAmt) 7514732Sgblack@eecs.umich.edu { 7526449Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 7536449Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 7544732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7554732Sgblack@eecs.umich.edu } 7564732Sgblack@eecs.umich.edu else 7576447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 7585040Sgblack@eecs.umich.edu ''' 7595076Sgblack@eecs.umich.edu flag_code = ''' 7605076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7615076Sgblack@eecs.umich.edu if (shiftAmt) { 7625076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7635076Sgblack@eecs.umich.edu //worry about setting them. 7645076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7655076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 7665076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7675076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 7685076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7695076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && msb) 7705076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7715076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7725076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 7735076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7745076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7755076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7765076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7775076Sgblack@eecs.umich.edu } 7785076Sgblack@eecs.umich.edu ''' 7795040Sgblack@eecs.umich.edu 7805076Sgblack@eecs.umich.edu class Rcr(RegOp): 7815040Sgblack@eecs.umich.edu code = ''' 7824733Sgblack@eecs.umich.edu uint8_t shiftAmt = 7834756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7846454Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 7856454Sgblack@eecs.umich.edu if(realShiftAmt) 7864733Sgblack@eecs.umich.edu { 7874733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 7886454Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 7896454Sgblack@eecs.umich.edu if (realShiftAmt > 1) 7906454Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 7916454Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 7924733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7934733Sgblack@eecs.umich.edu } 7944733Sgblack@eecs.umich.edu else 7956447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 7965040Sgblack@eecs.umich.edu ''' 7975076Sgblack@eecs.umich.edu flag_code = ''' 7985076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7995076Sgblack@eecs.umich.edu if (shiftAmt) { 8006453Sgblack@eecs.umich.edu int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 8015076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8025076Sgblack@eecs.umich.edu //worry about setting them. 8035076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8045076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8056453Sgblack@eecs.umich.edu if ((ext & OFBit) && (origCFBit ^ 8066453Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) { 8075076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8086453Sgblack@eecs.umich.edu } 8095076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8106454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8116454Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : 8126454Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) { 8135076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8146454Sgblack@eecs.umich.edu } 8155076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8165076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8175076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8185076Sgblack@eecs.umich.edu } 8195076Sgblack@eecs.umich.edu ''' 8205040Sgblack@eecs.umich.edu 8215076Sgblack@eecs.umich.edu class Rol(RegOp): 8225040Sgblack@eecs.umich.edu code = ''' 8234732Sgblack@eecs.umich.edu uint8_t shiftAmt = 8244756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8256446Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 8266446Sgblack@eecs.umich.edu if(realShiftAmt) 8274732Sgblack@eecs.umich.edu { 8286446Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 8294732Sgblack@eecs.umich.edu uint64_t bottom = 8306446Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 8314732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8324732Sgblack@eecs.umich.edu } 8334732Sgblack@eecs.umich.edu else 8346447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8355040Sgblack@eecs.umich.edu ''' 8365076Sgblack@eecs.umich.edu flag_code = ''' 8375076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8385076Sgblack@eecs.umich.edu if (shiftAmt) { 8395076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8405076Sgblack@eecs.umich.edu //worry about setting them. 8415076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8425076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 8435076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 8445076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8455076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8465076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && lsb) 8475076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8485076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8495076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 8505076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8515076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8525076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8535076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8545076Sgblack@eecs.umich.edu } 8555076Sgblack@eecs.umich.edu ''' 8565040Sgblack@eecs.umich.edu 8575076Sgblack@eecs.umich.edu class Rcl(RegOp): 8585040Sgblack@eecs.umich.edu code = ''' 8594733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8604756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8616456Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 8626456Sgblack@eecs.umich.edu if(realShiftAmt) 8634733Sgblack@eecs.umich.edu { 8644733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8656456Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 8666456Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (realShiftAmt - 1); 8674733Sgblack@eecs.umich.edu if(shiftAmt > 1) 8684733Sgblack@eecs.umich.edu bottom |= 8694823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 8706456Sgblack@eecs.umich.edu dataSize * 8 - realShiftAmt + 1); 8714733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8724733Sgblack@eecs.umich.edu } 8734733Sgblack@eecs.umich.edu else 8746447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8755040Sgblack@eecs.umich.edu ''' 8765076Sgblack@eecs.umich.edu flag_code = ''' 8775076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8785076Sgblack@eecs.umich.edu if (shiftAmt) { 8796456Sgblack@eecs.umich.edu int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 8805076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8815076Sgblack@eecs.umich.edu //worry about setting them. 8825076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8835076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8846456Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 8855076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8866456Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8876456Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : CFBits) 8885076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8895076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8905076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 8915076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8925076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8935076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8945076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8955076Sgblack@eecs.umich.edu } 8965076Sgblack@eecs.umich.edu ''' 8974732Sgblack@eecs.umich.edu 8986479Sgblack@eecs.umich.edu class Sld(RegOp): 8996479Sgblack@eecs.umich.edu code = ''' 9006479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9016479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 9026479Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 9036479Sgblack@eecs.umich.edu uint64_t result; 9046479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 9056479Sgblack@eecs.umich.edu result = psrc1; 9066479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 9076479Sgblack@eecs.umich.edu result = (psrc1 << realShiftAmt) | 9086479Sgblack@eecs.umich.edu (DoubleBits >> (dataBits - realShiftAmt)); 9096479Sgblack@eecs.umich.edu } else { 9106479Sgblack@eecs.umich.edu result = (DoubleBits << (realShiftAmt - dataBits)) | 9116479Sgblack@eecs.umich.edu (psrc1 >> (2 * dataBits - realShiftAmt)); 9126479Sgblack@eecs.umich.edu } 9136479Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 9146479Sgblack@eecs.umich.edu ''' 9156479Sgblack@eecs.umich.edu flag_code = ''' 9166479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9176479Sgblack@eecs.umich.edu if (shiftAmt) { 9186479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9196479Sgblack@eecs.umich.edu //worry about setting them. 9206479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 9216479Sgblack@eecs.umich.edu int CFBits = 0; 9226479Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 9236479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 9246479Sgblack@eecs.umich.edu bits(DoubleBits, 0)) || 9256479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 9266479Sgblack@eecs.umich.edu bits(SrcReg1, dataBits - realShiftAmt)) || 9276479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 9286479Sgblack@eecs.umich.edu bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 9296479Sgblack@eecs.umich.edu CFBits = 1; 9306479Sgblack@eecs.umich.edu } 9316479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9326479Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 9336479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 9346479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9356479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 9366479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 9376479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 9386479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9396479Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 9406479Sgblack@eecs.umich.edu DestReg, psrc1, op2); 9416479Sgblack@eecs.umich.edu } 9426479Sgblack@eecs.umich.edu ''' 9436479Sgblack@eecs.umich.edu 9446479Sgblack@eecs.umich.edu class Srd(RegOp): 9456479Sgblack@eecs.umich.edu code = ''' 9466479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9476479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 9486479Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 9496479Sgblack@eecs.umich.edu uint64_t result; 9506479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 9516479Sgblack@eecs.umich.edu result = psrc1; 9526479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 9536479Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right 9546479Sgblack@eecs.umich.edu // shift is not defined in the C/C++ standard, we have to 9556479Sgblack@eecs.umich.edu // mask them out to be sure they're zero. 9566479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataBits - realShiftAmt); 9576479Sgblack@eecs.umich.edu result = ((psrc1 >> realShiftAmt) & logicalMask) | 9586479Sgblack@eecs.umich.edu (DoubleBits << (dataBits - realShiftAmt)); 9596479Sgblack@eecs.umich.edu } else { 9606479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 9616479Sgblack@eecs.umich.edu result = ((DoubleBits >> (realShiftAmt - dataBits)) & 9626479Sgblack@eecs.umich.edu logicalMask) | 9636479Sgblack@eecs.umich.edu (psrc1 << (2 * dataBits - realShiftAmt)); 9646479Sgblack@eecs.umich.edu } 9656479Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 9666479Sgblack@eecs.umich.edu ''' 9676479Sgblack@eecs.umich.edu flag_code = ''' 9686479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9696479Sgblack@eecs.umich.edu if (shiftAmt) { 9706479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9716479Sgblack@eecs.umich.edu //worry about setting them. 9726479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 9736479Sgblack@eecs.umich.edu int CFBits = 0; 9746479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9756479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 9766479Sgblack@eecs.umich.edu bits(DoubleBits, dataBits - 1)) || 9776479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 9786479Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) || 9796479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 9806479Sgblack@eecs.umich.edu bits(DoubleBits, realShiftAmt - dataBits - 1))) { 9816479Sgblack@eecs.umich.edu CFBits = 1; 9826479Sgblack@eecs.umich.edu } 9836479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9846479Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 9856479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 9866479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9876479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 9886479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 9896479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 9906479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9916479Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 9926479Sgblack@eecs.umich.edu DestReg, psrc1, op2); 9936479Sgblack@eecs.umich.edu } 9946479Sgblack@eecs.umich.edu ''' 9956479Sgblack@eecs.umich.edu 9966479Sgblack@eecs.umich.edu class Mdb(WrRegOp): 9976479Sgblack@eecs.umich.edu code = 'DoubleBits = psrc1 ^ op2;' 9986479Sgblack@eecs.umich.edu 9995040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 10005246Sgblack@eecs.umich.edu code = 'RIP = psrc1 + sop2 + CSBase' 10015040Sgblack@eecs.umich.edu else_code="RIP = RIP;" 10025040Sgblack@eecs.umich.edu 10035040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 10045040Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 10055040Sgblack@eecs.umich.edu 10065426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 10075426Sgblack@eecs.umich.edu code = ''' 10085426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 10095426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 10105426Sgblack@eecs.umich.edu // Get only the user flags 10115426Sgblack@eecs.umich.edu ccFlagBits = newFlags & userFlagMask; 10125426Sgblack@eecs.umich.edu // Get everything else 10135426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 10145426Sgblack@eecs.umich.edu ''' 10155426Sgblack@eecs.umich.edu 10165040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 10175246Sgblack@eecs.umich.edu code = 'DestReg = RIP - CSBase' 10185040Sgblack@eecs.umich.edu 10195040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 10205040Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 10215040Sgblack@eecs.umich.edu 10225426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 10235426Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits | nccFlagBits' 10245426Sgblack@eecs.umich.edu 10255040Sgblack@eecs.umich.edu class Ruflag(RegOp): 10265040Sgblack@eecs.umich.edu code = ''' 10275116Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8); 10284951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 10295011Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 10305011Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 10315040Sgblack@eecs.umich.edu ''' 10325040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 10335040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 10345040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 10356345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 10364732Sgblack@eecs.umich.edu 10375426Sgblack@eecs.umich.edu class Rflag(RegOp): 10385426Sgblack@eecs.umich.edu code = ''' 10395426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 10405426Sgblack@eecs.umich.edu MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 10415426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 10425426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 10435426Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 10445426Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 10455426Sgblack@eecs.umich.edu ''' 10465426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 10475426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 10485426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 10496345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 10505426Sgblack@eecs.umich.edu 10515040Sgblack@eecs.umich.edu class Sext(RegOp): 10525040Sgblack@eecs.umich.edu code = ''' 10534823Sgblack@eecs.umich.edu IntReg val = psrc1; 10545239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 10555239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 10565239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 10575239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 10585007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 10595007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 10605040Sgblack@eecs.umich.edu ''' 10615239Sgblack@eecs.umich.edu flag_code = ''' 10625239Sgblack@eecs.umich.edu if (!sign_bit) 10635239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & 10645239Sgblack@eecs.umich.edu ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 10655239Sgblack@eecs.umich.edu else 10665239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | 10675239Sgblack@eecs.umich.edu (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 10685239Sgblack@eecs.umich.edu ''' 10694714Sgblack@eecs.umich.edu 10705040Sgblack@eecs.umich.edu class Zext(RegOp): 10715927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 10725241Sgblack@eecs.umich.edu 10735926Sgblack@eecs.umich.edu class Rddr(RegOp): 10745926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10755926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 10766345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10775926Sgblack@eecs.umich.edu code = ''' 10785926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 10795926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 10805926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 10815926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 10825926Sgblack@eecs.umich.edu } else if (dr7.gd) { 10835926Sgblack@eecs.umich.edu fault = new DebugException(); 10845926Sgblack@eecs.umich.edu } else { 10855926Sgblack@eecs.umich.edu DestReg = merge(DestReg, DebugSrc1, dataSize); 10865926Sgblack@eecs.umich.edu } 10875926Sgblack@eecs.umich.edu ''' 10885926Sgblack@eecs.umich.edu 10895926Sgblack@eecs.umich.edu class Wrdr(RegOp): 10905926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10915926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 10926345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10935926Sgblack@eecs.umich.edu code = ''' 10945926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 10955926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 10965926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 10975926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 10986345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 10995926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 11005926Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11015926Sgblack@eecs.umich.edu } else if (dr7.gd) { 11025926Sgblack@eecs.umich.edu fault = new DebugException(); 11035926Sgblack@eecs.umich.edu } else { 11045926Sgblack@eecs.umich.edu DebugDest = psrc1; 11055926Sgblack@eecs.umich.edu } 11065926Sgblack@eecs.umich.edu ''' 11075926Sgblack@eecs.umich.edu 11085296Sgblack@eecs.umich.edu class Rdcr(RegOp): 11095296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11105296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 11116345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11125296Sgblack@eecs.umich.edu code = ''' 11135924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 11145296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11155296Sgblack@eecs.umich.edu } else { 11165934Sgblack@eecs.umich.edu DestReg = merge(DestReg, ControlSrc1, dataSize); 11175296Sgblack@eecs.umich.edu } 11185296Sgblack@eecs.umich.edu ''' 11195296Sgblack@eecs.umich.edu 11205241Sgblack@eecs.umich.edu class Wrcr(RegOp): 11215241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11225241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 11236345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11245241Sgblack@eecs.umich.edu code = ''' 11255241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 11265241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11275241Sgblack@eecs.umich.edu } else { 11285241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 11295241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 11305241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 11315241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 11325241Sgblack@eecs.umich.edu 11335241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 11345241Sgblack@eecs.umich.edu switch(dest) { 11355241Sgblack@eecs.umich.edu case 0: 11365241Sgblack@eecs.umich.edu { 11375241Sgblack@eecs.umich.edu Efer efer = EferOp; 11385241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 11395241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 11405241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 11415241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 11425241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 11435241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 11445241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11455241Sgblack@eecs.umich.edu } 11465241Sgblack@eecs.umich.edu break; 11475241Sgblack@eecs.umich.edu case 2: 11485241Sgblack@eecs.umich.edu break; 11495241Sgblack@eecs.umich.edu case 3: 11505241Sgblack@eecs.umich.edu break; 11515241Sgblack@eecs.umich.edu case 4: 11525241Sgblack@eecs.umich.edu { 11535241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 11545241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 11555241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 11565241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 11575241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11585241Sgblack@eecs.umich.edu } 11595241Sgblack@eecs.umich.edu break; 11605241Sgblack@eecs.umich.edu case 8: 11615241Sgblack@eecs.umich.edu { 11625241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 11635241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11645241Sgblack@eecs.umich.edu } 11655241Sgblack@eecs.umich.edu default: 11665241Sgblack@eecs.umich.edu panic("Unrecognized control register %d.\\n", dest); 11675241Sgblack@eecs.umich.edu } 11685241Sgblack@eecs.umich.edu ControlDest = newVal; 11695241Sgblack@eecs.umich.edu } 11705241Sgblack@eecs.umich.edu ''' 11715290Sgblack@eecs.umich.edu 11725294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 11735672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 11745294Sgblack@eecs.umich.edu abstract = True 11755290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11765294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 11776345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11785294Sgblack@eecs.umich.edu 11795294Sgblack@eecs.umich.edu class Wrbase(SegOp): 11805290Sgblack@eecs.umich.edu code = ''' 11815294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 11825290Sgblack@eecs.umich.edu ''' 11835290Sgblack@eecs.umich.edu 11845294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 11855290Sgblack@eecs.umich.edu code = ''' 11865294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 11875294Sgblack@eecs.umich.edu ''' 11885294Sgblack@eecs.umich.edu 11895294Sgblack@eecs.umich.edu class Wrsel(SegOp): 11905294Sgblack@eecs.umich.edu code = ''' 11915294Sgblack@eecs.umich.edu SegSelDest = psrc1; 11925294Sgblack@eecs.umich.edu ''' 11935294Sgblack@eecs.umich.edu 11945905Sgblack@eecs.umich.edu class WrAttr(SegOp): 11955905Sgblack@eecs.umich.edu code = ''' 11965905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 11975905Sgblack@eecs.umich.edu ''' 11985905Sgblack@eecs.umich.edu 11995294Sgblack@eecs.umich.edu class Rdbase(SegOp): 12005294Sgblack@eecs.umich.edu code = ''' 12015932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegBaseSrc1, dataSize); 12025294Sgblack@eecs.umich.edu ''' 12035294Sgblack@eecs.umich.edu 12045294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 12055294Sgblack@eecs.umich.edu code = ''' 12065932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegLimitSrc1, dataSize); 12075294Sgblack@eecs.umich.edu ''' 12085294Sgblack@eecs.umich.edu 12095427Sgblack@eecs.umich.edu class RdAttr(SegOp): 12105427Sgblack@eecs.umich.edu code = ''' 12115932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegAttrSrc1, dataSize); 12125427Sgblack@eecs.umich.edu ''' 12135427Sgblack@eecs.umich.edu 12145294Sgblack@eecs.umich.edu class Rdsel(SegOp): 12155294Sgblack@eecs.umich.edu code = ''' 12165932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegSelSrc1, dataSize); 12175294Sgblack@eecs.umich.edu ''' 12185294Sgblack@eecs.umich.edu 12195682Sgblack@eecs.umich.edu class Rdval(RegOp): 12205682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12216345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 12226345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12235682Sgblack@eecs.umich.edu code = ''' 12245682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 12255682Sgblack@eecs.umich.edu ''' 12265682Sgblack@eecs.umich.edu 12275682Sgblack@eecs.umich.edu class Wrval(RegOp): 12285682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12296345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 12306345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12315682Sgblack@eecs.umich.edu code = ''' 12325682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 12335682Sgblack@eecs.umich.edu ''' 12345682Sgblack@eecs.umich.edu 12355428Sgblack@eecs.umich.edu class Chks(RegOp): 12365428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 12375428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 12385428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 12395428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 12405294Sgblack@eecs.umich.edu code = ''' 12415424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 12425433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 12435433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 12445433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 12455294Sgblack@eecs.umich.edu 12465428Sgblack@eecs.umich.edu switch (imm8) 12475428Sgblack@eecs.umich.edu { 12485428Sgblack@eecs.umich.edu case SegNoCheck: 12495428Sgblack@eecs.umich.edu break; 12505428Sgblack@eecs.umich.edu case SegCSCheck: 12516060Sgblack@eecs.umich.edu // Make sure it's the right type 12526060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 12536060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12546060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 12556060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12566060Sgblack@eecs.umich.edu } 12575428Sgblack@eecs.umich.edu break; 12585428Sgblack@eecs.umich.edu case SegCallGateCheck: 12595428Sgblack@eecs.umich.edu panic("CS checks for far calls/jumps through call gates" 12605428Sgblack@eecs.umich.edu "not implemented.\\n"); 12615428Sgblack@eecs.umich.edu break; 12625855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 12635853Sgblack@eecs.umich.edu // Check permissions. 12645674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 12655857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12666058Sgblack@eecs.umich.edu break; 12675674Sgblack@eecs.umich.edu } 12685855Sgblack@eecs.umich.edu // Fall through on purpose 12695855Sgblack@eecs.umich.edu case SegIntGateCheck: 12705853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 12715861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 12725853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 12735853Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12745853Sgblack@eecs.umich.edu } 12755674Sgblack@eecs.umich.edu break; 12765428Sgblack@eecs.umich.edu case SegSSCheck: 12775433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 12785433Sgblack@eecs.umich.edu if (!desc.p) { 12795857Sgblack@eecs.umich.edu fault = new StackFault(selector); 12805433Sgblack@eecs.umich.edu } 12815433Sgblack@eecs.umich.edu } else { 12825673Sgblack@eecs.umich.edu if ((m5reg.submode != SixtyFourBitMode || 12835673Sgblack@eecs.umich.edu m5reg.cpl == 3) || 12845433Sgblack@eecs.umich.edu !(desc.s == 1 && 12855433Sgblack@eecs.umich.edu desc.type.codeOrData == 0 && desc.type.w) || 12865433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 12875433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 12885857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12895433Sgblack@eecs.umich.edu } 12905433Sgblack@eecs.umich.edu } 12915428Sgblack@eecs.umich.edu break; 12925428Sgblack@eecs.umich.edu case SegIretCheck: 12935428Sgblack@eecs.umich.edu { 12945433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 12955433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 12965433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 12975433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 12985679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 12995857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13005679Sgblack@eecs.umich.edu } else if (!desc.p) { 13015857Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 13025679Sgblack@eecs.umich.edu } 13035428Sgblack@eecs.umich.edu break; 13045428Sgblack@eecs.umich.edu } 13055428Sgblack@eecs.umich.edu case SegIntCSCheck: 13065675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 13075675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 13085679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13095675Sgblack@eecs.umich.edu } 13105675Sgblack@eecs.umich.edu } else { 13115675Sgblack@eecs.umich.edu panic("Interrupt CS checks not implemented " 13125675Sgblack@eecs.umich.edu "in legacy mode.\\n"); 13135675Sgblack@eecs.umich.edu } 13145428Sgblack@eecs.umich.edu break; 13155899Sgblack@eecs.umich.edu case SegTRCheck: 13165899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 13175899Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13185899Sgblack@eecs.umich.edu } 13195899Sgblack@eecs.umich.edu break; 13205900Sgblack@eecs.umich.edu case SegTSSCheck: 13215900Sgblack@eecs.umich.edu if (!desc.p) { 13225900Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 13235900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 13245900Sgblack@eecs.umich.edu (desc.type == 1 && 13255900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 13265935Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13275900Sgblack@eecs.umich.edu } 13285900Sgblack@eecs.umich.edu break; 13295936Sgblack@eecs.umich.edu case SegInGDTCheck: 13305936Sgblack@eecs.umich.edu if (selector.ti) { 13315936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13325936Sgblack@eecs.umich.edu } 13335936Sgblack@eecs.umich.edu break; 13345936Sgblack@eecs.umich.edu case SegLDTCheck: 13355936Sgblack@eecs.umich.edu if (!desc.p) { 13365936Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 13375936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 13385936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13395936Sgblack@eecs.umich.edu } 13405936Sgblack@eecs.umich.edu break; 13415428Sgblack@eecs.umich.edu default: 13425428Sgblack@eecs.umich.edu panic("Undefined segment check type.\\n"); 13435428Sgblack@eecs.umich.edu } 13445294Sgblack@eecs.umich.edu ''' 13455294Sgblack@eecs.umich.edu flag_code = ''' 13465294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 13475294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 13485424Sgblack@eecs.umich.edu if (!selector.si && !selector.ti) 13495294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 13505294Sgblack@eecs.umich.edu ''' 13515294Sgblack@eecs.umich.edu 13525294Sgblack@eecs.umich.edu class Wrdh(RegOp): 13535294Sgblack@eecs.umich.edu code = ''' 13545678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 13555294Sgblack@eecs.umich.edu 13565678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 13575678Sgblack@eecs.umich.edu switch(desc.type) { 13585678Sgblack@eecs.umich.edu case LDT64: 13595678Sgblack@eecs.umich.edu case AvailableTSS64: 13605678Sgblack@eecs.umich.edu case BusyTSS64: 13615678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 13625678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 13635678Sgblack@eecs.umich.edu break; 13645678Sgblack@eecs.umich.edu case CallGate64: 13655678Sgblack@eecs.umich.edu case IntGate64: 13665678Sgblack@eecs.umich.edu case TrapGate64: 13675678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 13685678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 13695678Sgblack@eecs.umich.edu break; 13705678Sgblack@eecs.umich.edu default: 13715678Sgblack@eecs.umich.edu panic("Wrdh used with wrong descriptor type!\\n"); 13725678Sgblack@eecs.umich.edu } 13735678Sgblack@eecs.umich.edu DestReg = target; 13745294Sgblack@eecs.umich.edu ''' 13755294Sgblack@eecs.umich.edu 13765409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 13775409Sgblack@eecs.umich.edu code = ''' 13785409Sgblack@eecs.umich.edu TscOp = psrc1; 13795409Sgblack@eecs.umich.edu ''' 13805409Sgblack@eecs.umich.edu 13815409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 13825409Sgblack@eecs.umich.edu code = ''' 13835409Sgblack@eecs.umich.edu DestReg = TscOp; 13845409Sgblack@eecs.umich.edu ''' 13855409Sgblack@eecs.umich.edu 13865429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 13875429Sgblack@eecs.umich.edu code = ''' 13885429Sgblack@eecs.umich.edu DestReg = M5Reg; 13895429Sgblack@eecs.umich.edu ''' 13905429Sgblack@eecs.umich.edu 13915294Sgblack@eecs.umich.edu class Wrdl(RegOp): 13925294Sgblack@eecs.umich.edu code = ''' 13935294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 13945433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 13955433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 13966222Sgblack@eecs.umich.edu if (!desc.p) 13976222Sgblack@eecs.umich.edu panic("Segment not present.\\n"); 13985433Sgblack@eecs.umich.edu SegAttr attr = 0; 13995433Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 14006222Sgblack@eecs.umich.edu attr.unusable = 0; 14015433Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 14026222Sgblack@eecs.umich.edu attr.longMode = desc.l; 14036222Sgblack@eecs.umich.edu attr.avl = desc.avl; 14046222Sgblack@eecs.umich.edu attr.granularity = desc.g; 14056222Sgblack@eecs.umich.edu attr.present = desc.p; 14066222Sgblack@eecs.umich.edu attr.system = desc.s; 14076222Sgblack@eecs.umich.edu attr.type = desc.type; 14085433Sgblack@eecs.umich.edu if (!desc.s) { 14095901Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 14105901Sgblack@eecs.umich.edu if (desc.type.e) { 14115901Sgblack@eecs.umich.edu panic("Gate descriptor encountered.\\n"); 14125901Sgblack@eecs.umich.edu } 14135901Sgblack@eecs.umich.edu attr.readable = 1; 14145901Sgblack@eecs.umich.edu attr.writable = 1; 14156222Sgblack@eecs.umich.edu attr.expandDown = 0; 14165433Sgblack@eecs.umich.edu } else { 14175433Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 14186222Sgblack@eecs.umich.edu attr.expandDown = 0; 14195433Sgblack@eecs.umich.edu attr.readable = desc.type.r; 14206222Sgblack@eecs.umich.edu attr.writable = 0; 14215433Sgblack@eecs.umich.edu } else { 14225433Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 14235433Sgblack@eecs.umich.edu attr.readable = 1; 14245433Sgblack@eecs.umich.edu attr.writable = desc.type.w; 14255433Sgblack@eecs.umich.edu } 14265433Sgblack@eecs.umich.edu } 14275901Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 14285901Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 14295901Sgblack@eecs.umich.edu if (desc.g) 14305901Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 14315901Sgblack@eecs.umich.edu SegBaseDest = base; 14325901Sgblack@eecs.umich.edu SegLimitDest = limit; 14335901Sgblack@eecs.umich.edu SegAttrDest = attr; 14345433Sgblack@eecs.umich.edu } else { 14355295Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 14365295Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 14375295Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 14385294Sgblack@eecs.umich.edu } 14395290Sgblack@eecs.umich.edu ''' 14404519Sgblack@eecs.umich.edu}}; 1441