regop.isa revision 7080
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 44519Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 54519Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 64519Sgblack@eecs.umich.edu// following conditions are met: 74519Sgblack@eecs.umich.edu// 84519Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 94519Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 104519Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 114519Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 134519Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 144519Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 154519Sgblack@eecs.umich.edu// commercial advantage. 164519Sgblack@eecs.umich.edu// 174519Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 184519Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 194519Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 204519Sgblack@eecs.umich.edu// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 224519Sgblack@eecs.umich.edu// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 274519Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 284519Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 294519Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 304519Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 314519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 324519Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 334519Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 344519Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 354519Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534519Sgblack@eecs.umich.edu// 544519Sgblack@eecs.umich.edu// Authors: Gabe Black 554519Sgblack@eecs.umich.edu 564519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574519Sgblack@eecs.umich.edu// 584519Sgblack@eecs.umich.edu// RegOp Microop templates 594519Sgblack@eecs.umich.edu// 604519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614519Sgblack@eecs.umich.edu 624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 694519Sgblack@eecs.umich.edu %(op_decl)s; 704519Sgblack@eecs.umich.edu %(op_rd)s; 714688Sgblack@eecs.umich.edu 724688Sgblack@eecs.umich.edu if(%(cond_check)s) 734688Sgblack@eecs.umich.edu { 744688Sgblack@eecs.umich.edu %(code)s; 754688Sgblack@eecs.umich.edu %(flag_code)s; 764688Sgblack@eecs.umich.edu } 774708Sgblack@eecs.umich.edu else 784708Sgblack@eecs.umich.edu { 794708Sgblack@eecs.umich.edu %(else_code)s; 804708Sgblack@eecs.umich.edu } 814519Sgblack@eecs.umich.edu 824519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 834519Sgblack@eecs.umich.edu if(fault == NoFault) 844519Sgblack@eecs.umich.edu { 854519Sgblack@eecs.umich.edu %(op_wb)s; 864519Sgblack@eecs.umich.edu } 874519Sgblack@eecs.umich.edu return fault; 884519Sgblack@eecs.umich.edu } 894519Sgblack@eecs.umich.edu}}; 904519Sgblack@eecs.umich.edu 914519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 924951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 934519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 944519Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu Fault fault = NoFault; 964519Sgblack@eecs.umich.edu 974519Sgblack@eecs.umich.edu %(op_decl)s; 984519Sgblack@eecs.umich.edu %(op_rd)s; 994688Sgblack@eecs.umich.edu 1004688Sgblack@eecs.umich.edu if(%(cond_check)s) 1014688Sgblack@eecs.umich.edu { 1024688Sgblack@eecs.umich.edu %(code)s; 1034688Sgblack@eecs.umich.edu %(flag_code)s; 1044688Sgblack@eecs.umich.edu } 1054708Sgblack@eecs.umich.edu else 1064708Sgblack@eecs.umich.edu { 1074708Sgblack@eecs.umich.edu %(else_code)s; 1084708Sgblack@eecs.umich.edu } 1094519Sgblack@eecs.umich.edu 1104519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1114519Sgblack@eecs.umich.edu if(fault == NoFault) 1124519Sgblack@eecs.umich.edu { 1134519Sgblack@eecs.umich.edu %(op_wb)s; 1144519Sgblack@eecs.umich.edu } 1154519Sgblack@eecs.umich.edu return fault; 1164519Sgblack@eecs.umich.edu } 1174519Sgblack@eecs.umich.edu}}; 1184519Sgblack@eecs.umich.edu 1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1204519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu protected: 1234519Sgblack@eecs.umich.edu void buildMe(); 1244519Sgblack@eecs.umich.edu 1254519Sgblack@eecs.umich.edu public: 1264519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1274519Sgblack@eecs.umich.edu const char * instMnem, 1284519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1296345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1304712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1334519Sgblack@eecs.umich.edu const char * instMnem, 1346345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1354712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1364519Sgblack@eecs.umich.edu 1374519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1384519Sgblack@eecs.umich.edu }; 1394519Sgblack@eecs.umich.edu}}; 1404519Sgblack@eecs.umich.edu 1414519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1424519Sgblack@eecs.umich.edu 1434951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1444519Sgblack@eecs.umich.edu { 1454519Sgblack@eecs.umich.edu protected: 1464519Sgblack@eecs.umich.edu void buildMe(); 1474519Sgblack@eecs.umich.edu 1484519Sgblack@eecs.umich.edu public: 1494951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1504519Sgblack@eecs.umich.edu const char * instMnem, 1514519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1526646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1534712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1544519Sgblack@eecs.umich.edu 1554951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1564519Sgblack@eecs.umich.edu const char * instMnem, 1576646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1584712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1594519Sgblack@eecs.umich.edu 1604519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1614519Sgblack@eecs.umich.edu }; 1624519Sgblack@eecs.umich.edu}}; 1634519Sgblack@eecs.umich.edu 1644519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1654519Sgblack@eecs.umich.edu 1664519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1674519Sgblack@eecs.umich.edu { 1684519Sgblack@eecs.umich.edu %(constructor)s; 1694519Sgblack@eecs.umich.edu } 1704519Sgblack@eecs.umich.edu 1714519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1724519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1736345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1744712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1754519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1764581Sgblack@eecs.umich.edu false, false, false, false, 1774688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1784581Sgblack@eecs.umich.edu %(op_class)s) 1794519Sgblack@eecs.umich.edu { 1804519Sgblack@eecs.umich.edu buildMe(); 1814519Sgblack@eecs.umich.edu } 1824519Sgblack@eecs.umich.edu 1834519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1844519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1854519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1866345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1874712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1884519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1894581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1904688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1914581Sgblack@eecs.umich.edu %(op_class)s) 1924519Sgblack@eecs.umich.edu { 1934519Sgblack@eecs.umich.edu buildMe(); 1944519Sgblack@eecs.umich.edu } 1954519Sgblack@eecs.umich.edu}}; 1964519Sgblack@eecs.umich.edu 1974519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1984519Sgblack@eecs.umich.edu 1994951Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 2004519Sgblack@eecs.umich.edu { 2014519Sgblack@eecs.umich.edu %(constructor)s; 2024519Sgblack@eecs.umich.edu } 2034519Sgblack@eecs.umich.edu 2044951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2054519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2066646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 2074712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2084519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2094581Sgblack@eecs.umich.edu false, false, false, false, 2104688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2114581Sgblack@eecs.umich.edu %(op_class)s) 2124519Sgblack@eecs.umich.edu { 2134519Sgblack@eecs.umich.edu buildMe(); 2144519Sgblack@eecs.umich.edu } 2154519Sgblack@eecs.umich.edu 2164951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2174519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2184519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2196646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 2204712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2214519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2224581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2234688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2244581Sgblack@eecs.umich.edu %(op_class)s) 2254519Sgblack@eecs.umich.edu { 2264519Sgblack@eecs.umich.edu buildMe(); 2274519Sgblack@eecs.umich.edu } 2284519Sgblack@eecs.umich.edu}}; 2294519Sgblack@eecs.umich.edu 2305075Sgblack@eecs.umich.eduoutput header {{ 2315075Sgblack@eecs.umich.edu void 2325075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2335075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 2345428Sgblack@eecs.umich.edu 2355428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 2365674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 2375899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 2385936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 2395428Sgblack@eecs.umich.edu }; 2405678Sgblack@eecs.umich.edu 2415678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 2425678Sgblack@eecs.umich.edu LDT64 = 2, 2435678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 2445678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 2455678Sgblack@eecs.umich.edu CallGate64 = 0xc, 2465678Sgblack@eecs.umich.edu IntGate64 = 0xe, 2475678Sgblack@eecs.umich.edu TrapGate64 = 0xf 2485678Sgblack@eecs.umich.edu }; 2495075Sgblack@eecs.umich.edu}}; 2505075Sgblack@eecs.umich.edu 2515075Sgblack@eecs.umich.eduoutput decoder {{ 2525075Sgblack@eecs.umich.edu void 2535075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2545075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 2555075Sgblack@eecs.umich.edu { 2565075Sgblack@eecs.umich.edu //Check for divide by zero. 2575075Sgblack@eecs.umich.edu if (divisor == 0) 2585075Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 2595075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 2605075Sgblack@eecs.umich.edu if (divisor <= dividend) { 2615075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 2625075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 2635075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 2645075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 2655075Sgblack@eecs.umich.edu divisor <<= shift; 2665075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 2675075Sgblack@eecs.umich.edu //now larger than the dividend. 2685075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 2695075Sgblack@eecs.umich.edu quotientBit <<= shift; 2705075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2715075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2725075Sgblack@eecs.umich.edu //part of one or two bit division. 2735075Sgblack@eecs.umich.edu if (divisor > dividend) { 2745075Sgblack@eecs.umich.edu quotientBit >>= 1; 2755075Sgblack@eecs.umich.edu divisor >>= 1; 2765075Sgblack@eecs.umich.edu } 2775075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2785075Sgblack@eecs.umich.edu quotient += quotientBit; 2795075Sgblack@eecs.umich.edu remainder -= divisor; 2805075Sgblack@eecs.umich.edu } 2815075Sgblack@eecs.umich.edu } 2825075Sgblack@eecs.umich.edu}}; 2835075Sgblack@eecs.umich.edu 2844519Sgblack@eecs.umich.edulet {{ 2855040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2865040Sgblack@eecs.umich.edu # them will always work. 2875040Sgblack@eecs.umich.edu header_output = "" 2885040Sgblack@eecs.umich.edu decoder_output = "" 2895040Sgblack@eecs.umich.edu exec_output = "" 2905040Sgblack@eecs.umich.edu 2915040Sgblack@eecs.umich.edu immTemplates = ( 2925040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2935040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2945040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2955040Sgblack@eecs.umich.edu 2965040Sgblack@eecs.umich.edu regTemplates = ( 2975040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2985040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2995040Sgblack@eecs.umich.edu MicroRegOpExecute) 3005040Sgblack@eecs.umich.edu 3015040Sgblack@eecs.umich.edu class RegOpMeta(type): 3025040Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 3035040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code): 3045040Sgblack@eecs.umich.edu 3055040Sgblack@eecs.umich.edu # Globals to stick the output in 3065040Sgblack@eecs.umich.edu global header_output 3075040Sgblack@eecs.umich.edu global decoder_output 3085040Sgblack@eecs.umich.edu global exec_output 3095040Sgblack@eecs.umich.edu 3105040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 3115040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3125040Sgblack@eecs.umich.edu 3135040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3145040Sgblack@eecs.umich.edu # of this code. 3155062Sgblack@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 3165062Sgblack@eecs.umich.edu match = matcher.search(allCode) 3175062Sgblack@eecs.umich.edu if match: 3185062Sgblack@eecs.umich.edu typeQual = "" 3195062Sgblack@eecs.umich.edu if match.group("typeQual"): 3205062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 3215062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3225040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3235062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 3245062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 3255062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 3265062Sgblack@eecs.umich.edu matcher.sub(src2_name, else_code)) 3276647Sgblack@eecs.umich.edu imm_name = "%simm8" % match.group("prefix") 3285040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 3296647Sgblack@eecs.umich.edu matcher.sub(imm_name, code), 3306647Sgblack@eecs.umich.edu matcher.sub(imm_name, flag_code), 3316647Sgblack@eecs.umich.edu matcher.sub(imm_name, cond_check), 3326647Sgblack@eecs.umich.edu matcher.sub(imm_name, else_code)) 3335040Sgblack@eecs.umich.edu return 3345040Sgblack@eecs.umich.edu 3355040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 3365040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 3375239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 3385040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3395040Sgblack@eecs.umich.edu code, "", "true", else_code) 3405040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 3415040Sgblack@eecs.umich.edu 3425040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 3435040Sgblack@eecs.umich.edu # compute it. 3445040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 3455040Sgblack@eecs.umich.edu if matcher.search(allCode): 3465061Sgblack@eecs.umich.edu code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3475040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 3485040Sgblack@eecs.umich.edu if matcher.search(allCode): 3495061Sgblack@eecs.umich.edu code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3505061Sgblack@eecs.umich.edu # Also make available versions which do sign extension 3515061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3525061Sgblack@eecs.umich.edu if matcher.search(allCode): 3535061Sgblack@eecs.umich.edu code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3545061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3555061Sgblack@eecs.umich.edu if matcher.search(allCode): 3565061Sgblack@eecs.umich.edu code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3576647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)simm8(?!\w)") 3586647Sgblack@eecs.umich.edu if matcher.search(allCode): 3596647Sgblack@eecs.umich.edu code = "int8_t simm8 = imm8;" + code 3605040Sgblack@eecs.umich.edu 3615040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3625040Sgblack@eecs.umich.edu 3635040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3645040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3655040Sgblack@eecs.umich.edu templates = regTemplates 3666647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3675040Sgblack@eecs.umich.edu if matcher.search(allCode): 3685040Sgblack@eecs.umich.edu base += "Imm" 3695040Sgblack@eecs.umich.edu templates = immTemplates 3705040Sgblack@eecs.umich.edu 3715040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3725040Sgblack@eecs.umich.edu iop = InstObjParams(name, Name + suffix, base, 3735040Sgblack@eecs.umich.edu {"code" : code, 3745040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3755040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3765040Sgblack@eecs.umich.edu "else_code" : else_code}) 3775040Sgblack@eecs.umich.edu 3785040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3795040Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3805040Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3815040Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3825040Sgblack@eecs.umich.edu 3835040Sgblack@eecs.umich.edu 3845040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3854688Sgblack@eecs.umich.edu abstract = False 3865040Sgblack@eecs.umich.edu name = Name.lower() 3874688Sgblack@eecs.umich.edu if "abstract" in dict: 3884688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3894688Sgblack@eecs.umich.edu del dict['abstract'] 3904688Sgblack@eecs.umich.edu 3915040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3924688Sgblack@eecs.umich.edu if not abstract: 3935040Sgblack@eecs.umich.edu cls.className = Name 3945040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3955040Sgblack@eecs.umich.edu code = cls.code 3965040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3975040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3985040Sgblack@eecs.umich.edu else_code = cls.else_code 3995040Sgblack@eecs.umich.edu 4005040Sgblack@eecs.umich.edu # Set up the C++ classes 4015040Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", 4025040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code) 4035040Sgblack@eecs.umich.edu 4045040Sgblack@eecs.umich.edu # Hook into the microassembler dict 4055040Sgblack@eecs.umich.edu global microopClasses 4065040Sgblack@eecs.umich.edu microopClasses[name] = cls 4075040Sgblack@eecs.umich.edu 4085040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 4095040Sgblack@eecs.umich.edu 4105040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 4115040Sgblack@eecs.umich.edu # of this code. 4125040Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 4135040Sgblack@eecs.umich.edu if matcher.search(allCode): 4145040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 4154688Sgblack@eecs.umich.edu return cls 4164688Sgblack@eecs.umich.edu 4175040Sgblack@eecs.umich.edu 4185040Sgblack@eecs.umich.edu class RegOp(X86Microop): 4195040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 4205040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 4214688Sgblack@eecs.umich.edu abstract = True 4224688Sgblack@eecs.umich.edu 4235040Sgblack@eecs.umich.edu # Default template parameter values 4245040Sgblack@eecs.umich.edu flag_code = "" 4255040Sgblack@eecs.umich.edu cond_check = "true" 4265040Sgblack@eecs.umich.edu else_code = ";" 4275040Sgblack@eecs.umich.edu 4285040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4294519Sgblack@eecs.umich.edu self.dest = dest 4304519Sgblack@eecs.umich.edu self.src1 = src1 4315040Sgblack@eecs.umich.edu self.op2 = op2 4324688Sgblack@eecs.umich.edu self.flags = flags 4334701Sgblack@eecs.umich.edu self.dataSize = dataSize 4344688Sgblack@eecs.umich.edu if flags is None: 4354688Sgblack@eecs.umich.edu self.ext = 0 4364688Sgblack@eecs.umich.edu else: 4374688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4384688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4394688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 4404688Sgblack@eecs.umich.edu self.className += "Flags" 4414519Sgblack@eecs.umich.edu 4424519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 4435040Sgblack@eecs.umich.edu className = self.className 4445040Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4455040Sgblack@eecs.umich.edu className += "Imm" 4465788Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock 4475040Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4484688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4495040Sgblack@eecs.umich.edu "class_name" : className, 4504519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4515040Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4524519Sgblack@eecs.umich.edu "dest" : self.dest, 4534519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4544519Sgblack@eecs.umich.edu "ext" : self.ext} 4554539Sgblack@eecs.umich.edu return allocator 4564519Sgblack@eecs.umich.edu 4575040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4584688Sgblack@eecs.umich.edu abstract = True 4595040Sgblack@eecs.umich.edu flag_code = ''' 4605040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4615115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4625040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4635040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4645040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 4655115Sgblack@eecs.umich.edu ccFlagBits &= ~(ECFBit & ext); 4665040Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 4675040Sgblack@eecs.umich.edu ''' 4684519Sgblack@eecs.umich.edu 4695040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4705040Sgblack@eecs.umich.edu abstract = True 4715040Sgblack@eecs.umich.edu flag_code = \ 4725040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4734519Sgblack@eecs.umich.edu 4745040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4755040Sgblack@eecs.umich.edu abstract = True 4765040Sgblack@eecs.umich.edu flag_code = \ 4775040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4784519Sgblack@eecs.umich.edu 4795040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4805040Sgblack@eecs.umich.edu abstract = True 4815083Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits, ext)" 4824519Sgblack@eecs.umich.edu 4835063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4845063Sgblack@eecs.umich.edu abstract = True 4855063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4865063Sgblack@eecs.umich.edu if not src1: 4875063Sgblack@eecs.umich.edu src1 = dest 4886345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4896345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4905063Sgblack@eecs.umich.edu 4915063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4925063Sgblack@eecs.umich.edu abstract = True 4935063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4946345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4956345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 4965063Sgblack@eecs.umich.edu 4975040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4985040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4994595Sgblack@eecs.umich.edu 5005040Sgblack@eecs.umich.edu class Or(LogicRegOp): 5015040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 5024595Sgblack@eecs.umich.edu 5035040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 5045040Sgblack@eecs.umich.edu code = ''' 5054732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5065138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 5075040Sgblack@eecs.umich.edu ''' 5085040Sgblack@eecs.umich.edu 5095040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 5105040Sgblack@eecs.umich.edu code = ''' 5114732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5125138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 5135040Sgblack@eecs.umich.edu ''' 5145040Sgblack@eecs.umich.edu 5155040Sgblack@eecs.umich.edu class And(LogicRegOp): 5165040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 5175040Sgblack@eecs.umich.edu 5185040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5195040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 5205040Sgblack@eecs.umich.edu 5215040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5225040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 5235040Sgblack@eecs.umich.edu 5245063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5255040Sgblack@eecs.umich.edu code = ''' 5265063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5275063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5286742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5296430Sgblack@eecs.umich.edu uint64_t hiResult; 5306430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5316430Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5326461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5336430Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5346430Sgblack@eecs.umich.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5356430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 5366430Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5376462Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 5386430Sgblack@eecs.umich.edu hiResult -= op2; 5396462Sgblack@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 5406430Sgblack@eecs.umich.edu hiResult -= psrc1; 5416430Sgblack@eecs.umich.edu ProdHi = hiResult; 5425040Sgblack@eecs.umich.edu ''' 5436463Sgblack@eecs.umich.edu flag_code = ''' 5446463Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 5456463Sgblack@eecs.umich.edu bits(ProdLow, dataSize * 8 - 1)) { 5466463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5476463Sgblack@eecs.umich.edu } else { 5486463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5496463Sgblack@eecs.umich.edu } 5506463Sgblack@eecs.umich.edu ''' 5515040Sgblack@eecs.umich.edu 5525063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5535040Sgblack@eecs.umich.edu code = ''' 5545063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5554809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5566742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5576430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5585063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5596461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5605063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5615063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5626430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) / shifter) + 5635063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5645040Sgblack@eecs.umich.edu ''' 5656463Sgblack@eecs.umich.edu flag_code = ''' 5666463Sgblack@eecs.umich.edu if (ProdHi) { 5676463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5686463Sgblack@eecs.umich.edu } else { 5696463Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5706463Sgblack@eecs.umich.edu } 5716463Sgblack@eecs.umich.edu ''' 5725040Sgblack@eecs.umich.edu 5735063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5745063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5755040Sgblack@eecs.umich.edu 5765063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5775063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5785063Sgblack@eecs.umich.edu if not src1: 5795063Sgblack@eecs.umich.edu src1 = dest 5806345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 5816345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 5825063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5835062Sgblack@eecs.umich.edu 5845075Sgblack@eecs.umich.edu # One or two bit divide 5855075Sgblack@eecs.umich.edu class Div1(WrRegOp): 5865040Sgblack@eecs.umich.edu code = ''' 5875075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 5885075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5895075Sgblack@eecs.umich.edu uint64_t quotient = 0; 5905075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 5915075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 5925075Sgblack@eecs.umich.edu //a source. 5935075Sgblack@eecs.umich.edu uint64_t divisor = op2; 5945075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 5955075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 5965075Sgblack@eecs.umich.edu //Do the division. 5975075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5985075Sgblack@eecs.umich.edu //Record the final results. 5995075Sgblack@eecs.umich.edu Remainder = remainder; 6005075Sgblack@eecs.umich.edu Quotient = quotient; 6015075Sgblack@eecs.umich.edu Divisor = divisor; 6025040Sgblack@eecs.umich.edu ''' 6034823Sgblack@eecs.umich.edu 6045075Sgblack@eecs.umich.edu # Step divide 6055075Sgblack@eecs.umich.edu class Div2(RegOp): 6065075Sgblack@eecs.umich.edu code = ''' 6075075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 6085075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 6095075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 6105075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 6115075Sgblack@eecs.umich.edu int remaining = op2; 6125075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 6135075Sgblack@eecs.umich.edu //little. 6145075Sgblack@eecs.umich.edu if (remaining) { 6157070Sgblack@eecs.umich.edu if (divisor & (ULL(1) << 63)) { 6167070Sgblack@eecs.umich.edu while (remaining && !(dividend & (ULL(1) << 63))) { 6177070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6187070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6197070Sgblack@eecs.umich.edu quotient <<= 1; 6207070Sgblack@eecs.umich.edu remaining--; 6217070Sgblack@eecs.umich.edu } 6227070Sgblack@eecs.umich.edu if (dividend & (ULL(1) << 63)) { 6237080Sgblack@eecs.umich.edu bool highBit = false; 6247070Sgblack@eecs.umich.edu if (dividend < divisor && remaining) { 6257080Sgblack@eecs.umich.edu highBit = true; 6267070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6277070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6287070Sgblack@eecs.umich.edu quotient <<= 1; 6297070Sgblack@eecs.umich.edu remaining--; 6307070Sgblack@eecs.umich.edu } 6317080Sgblack@eecs.umich.edu if (highBit || divisor <= dividend) { 6327080Sgblack@eecs.umich.edu quotient++; 6337080Sgblack@eecs.umich.edu dividend -= divisor; 6347080Sgblack@eecs.umich.edu } 6357070Sgblack@eecs.umich.edu } 6367070Sgblack@eecs.umich.edu remainder = dividend; 6377070Sgblack@eecs.umich.edu } else { 6387070Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 6397070Sgblack@eecs.umich.edu while (dividend < divisor && remaining) { 6407070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6417070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6427070Sgblack@eecs.umich.edu quotient <<= 1; 6437070Sgblack@eecs.umich.edu remaining--; 6447070Sgblack@eecs.umich.edu } 6457070Sgblack@eecs.umich.edu remainder = dividend; 6467070Sgblack@eecs.umich.edu //Do the division. 6477070Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6485075Sgblack@eecs.umich.edu } 6495075Sgblack@eecs.umich.edu } 6505075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 6515075Sgblack@eecs.umich.edu DestReg = merge(DestReg, remaining, dataSize); 6525075Sgblack@eecs.umich.edu //Record the final results 6535075Sgblack@eecs.umich.edu Remainder = remainder; 6545075Sgblack@eecs.umich.edu Quotient = quotient; 6555075Sgblack@eecs.umich.edu ''' 6565075Sgblack@eecs.umich.edu flag_code = ''' 6575075Sgblack@eecs.umich.edu if (DestReg == 0) 6585075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & EZFBit); 6595075Sgblack@eecs.umich.edu else 6605075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6615075Sgblack@eecs.umich.edu ''' 6624732Sgblack@eecs.umich.edu 6635075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6645075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6655075Sgblack@eecs.umich.edu 6665075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6675075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6685040Sgblack@eecs.umich.edu 6695040Sgblack@eecs.umich.edu class Mov(CondRegOp): 6705040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6716482Sgblack@eecs.umich.edu else_code = 'DestReg = DestReg;' 6725040Sgblack@eecs.umich.edu 6734732Sgblack@eecs.umich.edu # Shift instructions 6745040Sgblack@eecs.umich.edu 6755076Sgblack@eecs.umich.edu class Sll(RegOp): 6765040Sgblack@eecs.umich.edu code = ''' 6774756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6784823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6795040Sgblack@eecs.umich.edu ''' 6805076Sgblack@eecs.umich.edu flag_code = ''' 6815076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6825076Sgblack@eecs.umich.edu if (shiftAmt) { 6835076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6845076Sgblack@eecs.umich.edu //worry about setting them. 6855076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6865076Sgblack@eecs.umich.edu int CFBits = 0; 6875076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 6886441Sgblack@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 6896441Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 6905076Sgblack@eecs.umich.edu CFBits = 1; 6916441Sgblack@eecs.umich.edu } 6925076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6935076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 6945076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6955076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6965076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 6975076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6985076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6995076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7005076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7015076Sgblack@eecs.umich.edu } 7025076Sgblack@eecs.umich.edu ''' 7035040Sgblack@eecs.umich.edu 7045076Sgblack@eecs.umich.edu class Srl(RegOp): 7055040Sgblack@eecs.umich.edu code = ''' 7064756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7074732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 7084732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 7094732Sgblack@eecs.umich.edu // to be sure they're zero. 7104732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7114823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 7125040Sgblack@eecs.umich.edu ''' 7135076Sgblack@eecs.umich.edu flag_code = ''' 7145076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7155076Sgblack@eecs.umich.edu if (shiftAmt) { 7165076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7175076Sgblack@eecs.umich.edu //worry about setting them. 7185076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7195076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7206442Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7216442Sgblack@eecs.umich.edu shiftAmt <= dataSize * 8 && 7226442Sgblack@eecs.umich.edu bits(SrcReg1, shiftAmt - 1)) { 7235076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7246442Sgblack@eecs.umich.edu } 7255076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7265076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 7275076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7285076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7295076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7305076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7315076Sgblack@eecs.umich.edu } 7325076Sgblack@eecs.umich.edu ''' 7335040Sgblack@eecs.umich.edu 7345076Sgblack@eecs.umich.edu class Sra(RegOp): 7355040Sgblack@eecs.umich.edu code = ''' 7364756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7374732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 7384732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 7394732Sgblack@eecs.umich.edu // them manually to be sure. 7406443Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 7415032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 7424823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 7435040Sgblack@eecs.umich.edu ''' 7445076Sgblack@eecs.umich.edu flag_code = ''' 7455076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7465076Sgblack@eecs.umich.edu if (shiftAmt) { 7475076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7485076Sgblack@eecs.umich.edu //worry about setting them. 7495076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7505076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7516444Sgblack@eecs.umich.edu uint8_t effectiveShift = 7526444Sgblack@eecs.umich.edu (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 7536444Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7546444Sgblack@eecs.umich.edu bits(SrcReg1, effectiveShift - 1)) { 7555076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7566444Sgblack@eecs.umich.edu } 7575076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7585076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7595076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7605076Sgblack@eecs.umich.edu } 7615076Sgblack@eecs.umich.edu ''' 7625040Sgblack@eecs.umich.edu 7635076Sgblack@eecs.umich.edu class Ror(RegOp): 7645040Sgblack@eecs.umich.edu code = ''' 7654732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7664756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7676449Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 7686449Sgblack@eecs.umich.edu if(realShiftAmt) 7694732Sgblack@eecs.umich.edu { 7706449Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 7716449Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 7724732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7734732Sgblack@eecs.umich.edu } 7744732Sgblack@eecs.umich.edu else 7756447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 7765040Sgblack@eecs.umich.edu ''' 7775076Sgblack@eecs.umich.edu flag_code = ''' 7785076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7795076Sgblack@eecs.umich.edu if (shiftAmt) { 7805076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7815076Sgblack@eecs.umich.edu //worry about setting them. 7825076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7835076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 7845076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7855076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 7865076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7875076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && msb) 7885076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7895076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7905076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 7915076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7925076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7935076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7945076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7955076Sgblack@eecs.umich.edu } 7965076Sgblack@eecs.umich.edu ''' 7975040Sgblack@eecs.umich.edu 7985076Sgblack@eecs.umich.edu class Rcr(RegOp): 7995040Sgblack@eecs.umich.edu code = ''' 8004733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8014756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8026454Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 8036454Sgblack@eecs.umich.edu if(realShiftAmt) 8044733Sgblack@eecs.umich.edu { 8054733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8066454Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 8076454Sgblack@eecs.umich.edu if (realShiftAmt > 1) 8086454Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 8096454Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 8104733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8114733Sgblack@eecs.umich.edu } 8124733Sgblack@eecs.umich.edu else 8136447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8145040Sgblack@eecs.umich.edu ''' 8155076Sgblack@eecs.umich.edu flag_code = ''' 8165076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8175076Sgblack@eecs.umich.edu if (shiftAmt) { 8186453Sgblack@eecs.umich.edu int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 8195076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8205076Sgblack@eecs.umich.edu //worry about setting them. 8215076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8225076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8236453Sgblack@eecs.umich.edu if ((ext & OFBit) && (origCFBit ^ 8246453Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) { 8255076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8266453Sgblack@eecs.umich.edu } 8275076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8286454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8296454Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : 8306454Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) { 8315076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8326454Sgblack@eecs.umich.edu } 8335076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8345076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8355076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8365076Sgblack@eecs.umich.edu } 8375076Sgblack@eecs.umich.edu ''' 8385040Sgblack@eecs.umich.edu 8395076Sgblack@eecs.umich.edu class Rol(RegOp): 8405040Sgblack@eecs.umich.edu code = ''' 8414732Sgblack@eecs.umich.edu uint8_t shiftAmt = 8424756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8436446Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 8446446Sgblack@eecs.umich.edu if(realShiftAmt) 8454732Sgblack@eecs.umich.edu { 8466446Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 8474732Sgblack@eecs.umich.edu uint64_t bottom = 8486446Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 8494732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8504732Sgblack@eecs.umich.edu } 8514732Sgblack@eecs.umich.edu else 8526447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8535040Sgblack@eecs.umich.edu ''' 8545076Sgblack@eecs.umich.edu flag_code = ''' 8555076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8565076Sgblack@eecs.umich.edu if (shiftAmt) { 8575076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8585076Sgblack@eecs.umich.edu //worry about setting them. 8595076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8605076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 8615076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 8625076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8635076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8645076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && lsb) 8655076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8665076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8675076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 8685076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8695076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8705076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8715076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8725076Sgblack@eecs.umich.edu } 8735076Sgblack@eecs.umich.edu ''' 8745040Sgblack@eecs.umich.edu 8755076Sgblack@eecs.umich.edu class Rcl(RegOp): 8765040Sgblack@eecs.umich.edu code = ''' 8774733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8784756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8796456Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 8806456Sgblack@eecs.umich.edu if(realShiftAmt) 8814733Sgblack@eecs.umich.edu { 8824733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8836456Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 8846456Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (realShiftAmt - 1); 8854733Sgblack@eecs.umich.edu if(shiftAmt > 1) 8864733Sgblack@eecs.umich.edu bottom |= 8874823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 8886456Sgblack@eecs.umich.edu dataSize * 8 - realShiftAmt + 1); 8894733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8904733Sgblack@eecs.umich.edu } 8914733Sgblack@eecs.umich.edu else 8926447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8935040Sgblack@eecs.umich.edu ''' 8945076Sgblack@eecs.umich.edu flag_code = ''' 8955076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8965076Sgblack@eecs.umich.edu if (shiftAmt) { 8976456Sgblack@eecs.umich.edu int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 8985076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8995076Sgblack@eecs.umich.edu //worry about setting them. 9005076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 9015076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 9026456Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 9035076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9046456Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 9056456Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : CFBits) 9065076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 9075076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9085076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 9095076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 9105076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9115076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 9125076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 9135076Sgblack@eecs.umich.edu } 9145076Sgblack@eecs.umich.edu ''' 9154732Sgblack@eecs.umich.edu 9166479Sgblack@eecs.umich.edu class Sld(RegOp): 9176479Sgblack@eecs.umich.edu code = ''' 9186479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9196479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 9206479Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 9216479Sgblack@eecs.umich.edu uint64_t result; 9226479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 9236479Sgblack@eecs.umich.edu result = psrc1; 9246479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 9256479Sgblack@eecs.umich.edu result = (psrc1 << realShiftAmt) | 9266479Sgblack@eecs.umich.edu (DoubleBits >> (dataBits - realShiftAmt)); 9276479Sgblack@eecs.umich.edu } else { 9286479Sgblack@eecs.umich.edu result = (DoubleBits << (realShiftAmt - dataBits)) | 9296479Sgblack@eecs.umich.edu (psrc1 >> (2 * dataBits - realShiftAmt)); 9306479Sgblack@eecs.umich.edu } 9316479Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 9326479Sgblack@eecs.umich.edu ''' 9336479Sgblack@eecs.umich.edu flag_code = ''' 9346479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9356479Sgblack@eecs.umich.edu if (shiftAmt) { 9366479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9376479Sgblack@eecs.umich.edu //worry about setting them. 9386479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 9396479Sgblack@eecs.umich.edu int CFBits = 0; 9406479Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 9416479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 9426479Sgblack@eecs.umich.edu bits(DoubleBits, 0)) || 9436479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 9446479Sgblack@eecs.umich.edu bits(SrcReg1, dataBits - realShiftAmt)) || 9456479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 9466479Sgblack@eecs.umich.edu bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 9476479Sgblack@eecs.umich.edu CFBits = 1; 9486479Sgblack@eecs.umich.edu } 9496479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9506479Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 9516479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 9526479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9536479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 9546479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 9556479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 9566479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9576479Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 9586479Sgblack@eecs.umich.edu DestReg, psrc1, op2); 9596479Sgblack@eecs.umich.edu } 9606479Sgblack@eecs.umich.edu ''' 9616479Sgblack@eecs.umich.edu 9626479Sgblack@eecs.umich.edu class Srd(RegOp): 9636479Sgblack@eecs.umich.edu code = ''' 9646479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9656479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 9666479Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 9676479Sgblack@eecs.umich.edu uint64_t result; 9686479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 9696479Sgblack@eecs.umich.edu result = psrc1; 9706479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 9716479Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right 9726479Sgblack@eecs.umich.edu // shift is not defined in the C/C++ standard, we have to 9736479Sgblack@eecs.umich.edu // mask them out to be sure they're zero. 9746479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataBits - realShiftAmt); 9756479Sgblack@eecs.umich.edu result = ((psrc1 >> realShiftAmt) & logicalMask) | 9766479Sgblack@eecs.umich.edu (DoubleBits << (dataBits - realShiftAmt)); 9776479Sgblack@eecs.umich.edu } else { 9786479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 9796479Sgblack@eecs.umich.edu result = ((DoubleBits >> (realShiftAmt - dataBits)) & 9806479Sgblack@eecs.umich.edu logicalMask) | 9816479Sgblack@eecs.umich.edu (psrc1 << (2 * dataBits - realShiftAmt)); 9826479Sgblack@eecs.umich.edu } 9836479Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 9846479Sgblack@eecs.umich.edu ''' 9856479Sgblack@eecs.umich.edu flag_code = ''' 9866479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9876479Sgblack@eecs.umich.edu if (shiftAmt) { 9886479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9896479Sgblack@eecs.umich.edu //worry about setting them. 9906479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 9916479Sgblack@eecs.umich.edu int CFBits = 0; 9926479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9936479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 9946479Sgblack@eecs.umich.edu bits(DoubleBits, dataBits - 1)) || 9956479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 9966479Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) || 9976479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 9986479Sgblack@eecs.umich.edu bits(DoubleBits, realShiftAmt - dataBits - 1))) { 9996479Sgblack@eecs.umich.edu CFBits = 1; 10006479Sgblack@eecs.umich.edu } 10016479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10026479Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 10036479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 10046479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10056479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 10066479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 10076479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 10086479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10096479Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 10106479Sgblack@eecs.umich.edu DestReg, psrc1, op2); 10116479Sgblack@eecs.umich.edu } 10126479Sgblack@eecs.umich.edu ''' 10136479Sgblack@eecs.umich.edu 10146479Sgblack@eecs.umich.edu class Mdb(WrRegOp): 10156479Sgblack@eecs.umich.edu code = 'DoubleBits = psrc1 ^ op2;' 10166479Sgblack@eecs.umich.edu 10175040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 10185246Sgblack@eecs.umich.edu code = 'RIP = psrc1 + sop2 + CSBase' 10195040Sgblack@eecs.umich.edu else_code="RIP = RIP;" 10205040Sgblack@eecs.umich.edu 10215040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 10225040Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 10235040Sgblack@eecs.umich.edu 10245426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 10255426Sgblack@eecs.umich.edu code = ''' 10265426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 10275426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 10285426Sgblack@eecs.umich.edu // Get only the user flags 10295426Sgblack@eecs.umich.edu ccFlagBits = newFlags & userFlagMask; 10305426Sgblack@eecs.umich.edu // Get everything else 10315426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 10325426Sgblack@eecs.umich.edu ''' 10335426Sgblack@eecs.umich.edu 10345040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 10355246Sgblack@eecs.umich.edu code = 'DestReg = RIP - CSBase' 10365040Sgblack@eecs.umich.edu 10375040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 10385040Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 10395040Sgblack@eecs.umich.edu 10405426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 10415426Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits | nccFlagBits' 10425426Sgblack@eecs.umich.edu 10435040Sgblack@eecs.umich.edu class Ruflag(RegOp): 10445040Sgblack@eecs.umich.edu code = ''' 10455116Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8); 10464951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 10475011Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 10485011Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 10495040Sgblack@eecs.umich.edu ''' 10505040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 10515040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 10525040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 10536345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 10544732Sgblack@eecs.umich.edu 10555426Sgblack@eecs.umich.edu class Rflag(RegOp): 10565426Sgblack@eecs.umich.edu code = ''' 10575426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 10585426Sgblack@eecs.umich.edu MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 10595426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 10605426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 10615426Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 10625426Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 10635426Sgblack@eecs.umich.edu ''' 10645426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 10655426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 10665426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 10676345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 10685426Sgblack@eecs.umich.edu 10695040Sgblack@eecs.umich.edu class Sext(RegOp): 10705040Sgblack@eecs.umich.edu code = ''' 10714823Sgblack@eecs.umich.edu IntReg val = psrc1; 10725239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 10735239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 10745239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 10755239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 10765007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 10775007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 10785040Sgblack@eecs.umich.edu ''' 10795239Sgblack@eecs.umich.edu flag_code = ''' 10805239Sgblack@eecs.umich.edu if (!sign_bit) 10815239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & 10825239Sgblack@eecs.umich.edu ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 10835239Sgblack@eecs.umich.edu else 10845239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | 10855239Sgblack@eecs.umich.edu (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 10865239Sgblack@eecs.umich.edu ''' 10874714Sgblack@eecs.umich.edu 10885040Sgblack@eecs.umich.edu class Zext(RegOp): 10895927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 10905241Sgblack@eecs.umich.edu 10915926Sgblack@eecs.umich.edu class Rddr(RegOp): 10925926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10935926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 10946345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10955926Sgblack@eecs.umich.edu code = ''' 10965926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 10975926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 10985926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 10995926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11005926Sgblack@eecs.umich.edu } else if (dr7.gd) { 11015926Sgblack@eecs.umich.edu fault = new DebugException(); 11025926Sgblack@eecs.umich.edu } else { 11035926Sgblack@eecs.umich.edu DestReg = merge(DestReg, DebugSrc1, dataSize); 11045926Sgblack@eecs.umich.edu } 11055926Sgblack@eecs.umich.edu ''' 11065926Sgblack@eecs.umich.edu 11075926Sgblack@eecs.umich.edu class Wrdr(RegOp): 11085926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11095926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 11106345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11115926Sgblack@eecs.umich.edu code = ''' 11125926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 11135926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 11145926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 11155926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11166345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 11175926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 11185926Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11195926Sgblack@eecs.umich.edu } else if (dr7.gd) { 11205926Sgblack@eecs.umich.edu fault = new DebugException(); 11215926Sgblack@eecs.umich.edu } else { 11225926Sgblack@eecs.umich.edu DebugDest = psrc1; 11235926Sgblack@eecs.umich.edu } 11245926Sgblack@eecs.umich.edu ''' 11255926Sgblack@eecs.umich.edu 11265296Sgblack@eecs.umich.edu class Rdcr(RegOp): 11275296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11285296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 11296345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11305296Sgblack@eecs.umich.edu code = ''' 11315924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 11325296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11335296Sgblack@eecs.umich.edu } else { 11345934Sgblack@eecs.umich.edu DestReg = merge(DestReg, ControlSrc1, dataSize); 11355296Sgblack@eecs.umich.edu } 11365296Sgblack@eecs.umich.edu ''' 11375296Sgblack@eecs.umich.edu 11385241Sgblack@eecs.umich.edu class Wrcr(RegOp): 11395241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11405241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 11416345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11425241Sgblack@eecs.umich.edu code = ''' 11435241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 11445241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 11455241Sgblack@eecs.umich.edu } else { 11465241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 11475241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 11485241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 11495241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 11505241Sgblack@eecs.umich.edu 11515241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 11525241Sgblack@eecs.umich.edu switch(dest) { 11535241Sgblack@eecs.umich.edu case 0: 11545241Sgblack@eecs.umich.edu { 11555241Sgblack@eecs.umich.edu Efer efer = EferOp; 11565241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 11575241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 11585241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 11595241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 11605241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 11615241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 11625241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11635241Sgblack@eecs.umich.edu } 11645241Sgblack@eecs.umich.edu break; 11655241Sgblack@eecs.umich.edu case 2: 11665241Sgblack@eecs.umich.edu break; 11675241Sgblack@eecs.umich.edu case 3: 11685241Sgblack@eecs.umich.edu break; 11695241Sgblack@eecs.umich.edu case 4: 11705241Sgblack@eecs.umich.edu { 11715241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 11725241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 11735241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 11745241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 11755241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11765241Sgblack@eecs.umich.edu } 11775241Sgblack@eecs.umich.edu break; 11785241Sgblack@eecs.umich.edu case 8: 11795241Sgblack@eecs.umich.edu { 11805241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 11815241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11825241Sgblack@eecs.umich.edu } 11835241Sgblack@eecs.umich.edu default: 11845241Sgblack@eecs.umich.edu panic("Unrecognized control register %d.\\n", dest); 11855241Sgblack@eecs.umich.edu } 11865241Sgblack@eecs.umich.edu ControlDest = newVal; 11875241Sgblack@eecs.umich.edu } 11885241Sgblack@eecs.umich.edu ''' 11895290Sgblack@eecs.umich.edu 11905294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 11915672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 11925294Sgblack@eecs.umich.edu abstract = True 11935290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 11945294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 11956345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 11965294Sgblack@eecs.umich.edu 11975294Sgblack@eecs.umich.edu class Wrbase(SegOp): 11985290Sgblack@eecs.umich.edu code = ''' 11995294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 12005290Sgblack@eecs.umich.edu ''' 12015290Sgblack@eecs.umich.edu 12025294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 12035290Sgblack@eecs.umich.edu code = ''' 12045294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 12055294Sgblack@eecs.umich.edu ''' 12065294Sgblack@eecs.umich.edu 12075294Sgblack@eecs.umich.edu class Wrsel(SegOp): 12085294Sgblack@eecs.umich.edu code = ''' 12095294Sgblack@eecs.umich.edu SegSelDest = psrc1; 12105294Sgblack@eecs.umich.edu ''' 12115294Sgblack@eecs.umich.edu 12125905Sgblack@eecs.umich.edu class WrAttr(SegOp): 12135905Sgblack@eecs.umich.edu code = ''' 12145905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 12155905Sgblack@eecs.umich.edu ''' 12165905Sgblack@eecs.umich.edu 12175294Sgblack@eecs.umich.edu class Rdbase(SegOp): 12185294Sgblack@eecs.umich.edu code = ''' 12195932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegBaseSrc1, dataSize); 12205294Sgblack@eecs.umich.edu ''' 12215294Sgblack@eecs.umich.edu 12225294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 12235294Sgblack@eecs.umich.edu code = ''' 12245932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegLimitSrc1, dataSize); 12255294Sgblack@eecs.umich.edu ''' 12265294Sgblack@eecs.umich.edu 12275427Sgblack@eecs.umich.edu class RdAttr(SegOp): 12285427Sgblack@eecs.umich.edu code = ''' 12295932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegAttrSrc1, dataSize); 12305427Sgblack@eecs.umich.edu ''' 12315427Sgblack@eecs.umich.edu 12325294Sgblack@eecs.umich.edu class Rdsel(SegOp): 12335294Sgblack@eecs.umich.edu code = ''' 12345932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegSelSrc1, dataSize); 12355294Sgblack@eecs.umich.edu ''' 12365294Sgblack@eecs.umich.edu 12375682Sgblack@eecs.umich.edu class Rdval(RegOp): 12385682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12396345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 12406345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12415682Sgblack@eecs.umich.edu code = ''' 12425682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 12435682Sgblack@eecs.umich.edu ''' 12445682Sgblack@eecs.umich.edu 12455682Sgblack@eecs.umich.edu class Wrval(RegOp): 12465682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 12476345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 12486345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 12495682Sgblack@eecs.umich.edu code = ''' 12505682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 12515682Sgblack@eecs.umich.edu ''' 12525682Sgblack@eecs.umich.edu 12535428Sgblack@eecs.umich.edu class Chks(RegOp): 12545428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 12555428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 12565428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 12575428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 12585294Sgblack@eecs.umich.edu code = ''' 12595424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 12605433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 12615433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 12625433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 12635294Sgblack@eecs.umich.edu 12645428Sgblack@eecs.umich.edu switch (imm8) 12655428Sgblack@eecs.umich.edu { 12665428Sgblack@eecs.umich.edu case SegNoCheck: 12675428Sgblack@eecs.umich.edu break; 12685428Sgblack@eecs.umich.edu case SegCSCheck: 12696060Sgblack@eecs.umich.edu // Make sure it's the right type 12706060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 12716060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12726060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 12736060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12746060Sgblack@eecs.umich.edu } 12755428Sgblack@eecs.umich.edu break; 12765428Sgblack@eecs.umich.edu case SegCallGateCheck: 12775428Sgblack@eecs.umich.edu panic("CS checks for far calls/jumps through call gates" 12785428Sgblack@eecs.umich.edu "not implemented.\\n"); 12795428Sgblack@eecs.umich.edu break; 12805855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 12815853Sgblack@eecs.umich.edu // Check permissions. 12825674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 12835857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 12846058Sgblack@eecs.umich.edu break; 12855674Sgblack@eecs.umich.edu } 12865855Sgblack@eecs.umich.edu // Fall through on purpose 12875855Sgblack@eecs.umich.edu case SegIntGateCheck: 12885853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 12895861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 12905853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 12915853Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 12925853Sgblack@eecs.umich.edu } 12935674Sgblack@eecs.umich.edu break; 12945428Sgblack@eecs.umich.edu case SegSSCheck: 12955433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 12965433Sgblack@eecs.umich.edu if (!desc.p) { 12975857Sgblack@eecs.umich.edu fault = new StackFault(selector); 12985433Sgblack@eecs.umich.edu } 12995433Sgblack@eecs.umich.edu } else { 13005673Sgblack@eecs.umich.edu if ((m5reg.submode != SixtyFourBitMode || 13015673Sgblack@eecs.umich.edu m5reg.cpl == 3) || 13025433Sgblack@eecs.umich.edu !(desc.s == 1 && 13035433Sgblack@eecs.umich.edu desc.type.codeOrData == 0 && desc.type.w) || 13045433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 13055433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 13065857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13075433Sgblack@eecs.umich.edu } 13085433Sgblack@eecs.umich.edu } 13095428Sgblack@eecs.umich.edu break; 13105428Sgblack@eecs.umich.edu case SegIretCheck: 13115428Sgblack@eecs.umich.edu { 13125433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 13135433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 13145433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 13155433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 13165679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 13175857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13185679Sgblack@eecs.umich.edu } else if (!desc.p) { 13195857Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 13205679Sgblack@eecs.umich.edu } 13215428Sgblack@eecs.umich.edu break; 13225428Sgblack@eecs.umich.edu } 13235428Sgblack@eecs.umich.edu case SegIntCSCheck: 13245675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 13255675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 13265679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13275675Sgblack@eecs.umich.edu } 13285675Sgblack@eecs.umich.edu } else { 13295675Sgblack@eecs.umich.edu panic("Interrupt CS checks not implemented " 13305675Sgblack@eecs.umich.edu "in legacy mode.\\n"); 13315675Sgblack@eecs.umich.edu } 13325428Sgblack@eecs.umich.edu break; 13335899Sgblack@eecs.umich.edu case SegTRCheck: 13345899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 13355899Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13365899Sgblack@eecs.umich.edu } 13375899Sgblack@eecs.umich.edu break; 13385900Sgblack@eecs.umich.edu case SegTSSCheck: 13395900Sgblack@eecs.umich.edu if (!desc.p) { 13405900Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 13415900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 13425900Sgblack@eecs.umich.edu (desc.type == 1 && 13435900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 13445935Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13455900Sgblack@eecs.umich.edu } 13465900Sgblack@eecs.umich.edu break; 13475936Sgblack@eecs.umich.edu case SegInGDTCheck: 13485936Sgblack@eecs.umich.edu if (selector.ti) { 13495936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13505936Sgblack@eecs.umich.edu } 13515936Sgblack@eecs.umich.edu break; 13525936Sgblack@eecs.umich.edu case SegLDTCheck: 13535936Sgblack@eecs.umich.edu if (!desc.p) { 13545936Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 13555936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 13565936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 13575936Sgblack@eecs.umich.edu } 13585936Sgblack@eecs.umich.edu break; 13595428Sgblack@eecs.umich.edu default: 13605428Sgblack@eecs.umich.edu panic("Undefined segment check type.\\n"); 13615428Sgblack@eecs.umich.edu } 13625294Sgblack@eecs.umich.edu ''' 13635294Sgblack@eecs.umich.edu flag_code = ''' 13645294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 13655294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 13665424Sgblack@eecs.umich.edu if (!selector.si && !selector.ti) 13675294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 13685294Sgblack@eecs.umich.edu ''' 13695294Sgblack@eecs.umich.edu 13705294Sgblack@eecs.umich.edu class Wrdh(RegOp): 13715294Sgblack@eecs.umich.edu code = ''' 13725678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 13735294Sgblack@eecs.umich.edu 13745678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 13755678Sgblack@eecs.umich.edu switch(desc.type) { 13765678Sgblack@eecs.umich.edu case LDT64: 13775678Sgblack@eecs.umich.edu case AvailableTSS64: 13785678Sgblack@eecs.umich.edu case BusyTSS64: 13795678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 13805678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 13815678Sgblack@eecs.umich.edu break; 13825678Sgblack@eecs.umich.edu case CallGate64: 13835678Sgblack@eecs.umich.edu case IntGate64: 13845678Sgblack@eecs.umich.edu case TrapGate64: 13855678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 13865678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 13875678Sgblack@eecs.umich.edu break; 13885678Sgblack@eecs.umich.edu default: 13895678Sgblack@eecs.umich.edu panic("Wrdh used with wrong descriptor type!\\n"); 13905678Sgblack@eecs.umich.edu } 13915678Sgblack@eecs.umich.edu DestReg = target; 13925294Sgblack@eecs.umich.edu ''' 13935294Sgblack@eecs.umich.edu 13945409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 13955409Sgblack@eecs.umich.edu code = ''' 13965409Sgblack@eecs.umich.edu TscOp = psrc1; 13975409Sgblack@eecs.umich.edu ''' 13985409Sgblack@eecs.umich.edu 13995409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 14005409Sgblack@eecs.umich.edu code = ''' 14015409Sgblack@eecs.umich.edu DestReg = TscOp; 14025409Sgblack@eecs.umich.edu ''' 14035409Sgblack@eecs.umich.edu 14045429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 14055429Sgblack@eecs.umich.edu code = ''' 14065429Sgblack@eecs.umich.edu DestReg = M5Reg; 14075429Sgblack@eecs.umich.edu ''' 14085429Sgblack@eecs.umich.edu 14095294Sgblack@eecs.umich.edu class Wrdl(RegOp): 14105294Sgblack@eecs.umich.edu code = ''' 14115294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 14125433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 14135433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 14146222Sgblack@eecs.umich.edu if (!desc.p) 14156222Sgblack@eecs.umich.edu panic("Segment not present.\\n"); 14165433Sgblack@eecs.umich.edu SegAttr attr = 0; 14175433Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 14186222Sgblack@eecs.umich.edu attr.unusable = 0; 14195433Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 14206222Sgblack@eecs.umich.edu attr.longMode = desc.l; 14216222Sgblack@eecs.umich.edu attr.avl = desc.avl; 14226222Sgblack@eecs.umich.edu attr.granularity = desc.g; 14236222Sgblack@eecs.umich.edu attr.present = desc.p; 14246222Sgblack@eecs.umich.edu attr.system = desc.s; 14256222Sgblack@eecs.umich.edu attr.type = desc.type; 14265433Sgblack@eecs.umich.edu if (!desc.s) { 14275901Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 14285901Sgblack@eecs.umich.edu if (desc.type.e) { 14295901Sgblack@eecs.umich.edu panic("Gate descriptor encountered.\\n"); 14305901Sgblack@eecs.umich.edu } 14315901Sgblack@eecs.umich.edu attr.readable = 1; 14325901Sgblack@eecs.umich.edu attr.writable = 1; 14336222Sgblack@eecs.umich.edu attr.expandDown = 0; 14345433Sgblack@eecs.umich.edu } else { 14355433Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 14366222Sgblack@eecs.umich.edu attr.expandDown = 0; 14375433Sgblack@eecs.umich.edu attr.readable = desc.type.r; 14386222Sgblack@eecs.umich.edu attr.writable = 0; 14395433Sgblack@eecs.umich.edu } else { 14405433Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 14415433Sgblack@eecs.umich.edu attr.readable = 1; 14425433Sgblack@eecs.umich.edu attr.writable = desc.type.w; 14435433Sgblack@eecs.umich.edu } 14445433Sgblack@eecs.umich.edu } 14455901Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 14465901Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 14475901Sgblack@eecs.umich.edu if (desc.g) 14485901Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 14495901Sgblack@eecs.umich.edu SegBaseDest = base; 14505901Sgblack@eecs.umich.edu SegLimitDest = limit; 14515901Sgblack@eecs.umich.edu SegAttrDest = attr; 14525433Sgblack@eecs.umich.edu } else { 14535295Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 14545295Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 14555295Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 14565294Sgblack@eecs.umich.edu } 14575290Sgblack@eecs.umich.edu ''' 14584519Sgblack@eecs.umich.edu}}; 1459