regop.isa revision 6345
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 44519Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 54519Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 64519Sgblack@eecs.umich.edu// following conditions are met: 74519Sgblack@eecs.umich.edu// 84519Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 94519Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 104519Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 114519Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 134519Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 144519Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 154519Sgblack@eecs.umich.edu// commercial advantage. 164519Sgblack@eecs.umich.edu// 174519Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 184519Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 194519Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 204519Sgblack@eecs.umich.edu// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 224519Sgblack@eecs.umich.edu// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 274519Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 284519Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 294519Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 304519Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 314519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 324519Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 334519Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 344519Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 354519Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534519Sgblack@eecs.umich.edu// 544519Sgblack@eecs.umich.edu// Authors: Gabe Black 554519Sgblack@eecs.umich.edu 564519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574519Sgblack@eecs.umich.edu// 584519Sgblack@eecs.umich.edu// RegOp Microop templates 594519Sgblack@eecs.umich.edu// 604519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614519Sgblack@eecs.umich.edu 624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 694519Sgblack@eecs.umich.edu %(op_decl)s; 704519Sgblack@eecs.umich.edu %(op_rd)s; 714688Sgblack@eecs.umich.edu 724688Sgblack@eecs.umich.edu if(%(cond_check)s) 734688Sgblack@eecs.umich.edu { 744688Sgblack@eecs.umich.edu %(code)s; 754688Sgblack@eecs.umich.edu %(flag_code)s; 764688Sgblack@eecs.umich.edu } 774708Sgblack@eecs.umich.edu else 784708Sgblack@eecs.umich.edu { 794708Sgblack@eecs.umich.edu %(else_code)s; 804708Sgblack@eecs.umich.edu } 814519Sgblack@eecs.umich.edu 824519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 834519Sgblack@eecs.umich.edu if(fault == NoFault) 844519Sgblack@eecs.umich.edu { 854519Sgblack@eecs.umich.edu %(op_wb)s; 864519Sgblack@eecs.umich.edu } 874519Sgblack@eecs.umich.edu return fault; 884519Sgblack@eecs.umich.edu } 894519Sgblack@eecs.umich.edu}}; 904519Sgblack@eecs.umich.edu 914519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 924951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 934519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 944519Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu Fault fault = NoFault; 964519Sgblack@eecs.umich.edu 974519Sgblack@eecs.umich.edu %(op_decl)s; 984519Sgblack@eecs.umich.edu %(op_rd)s; 994688Sgblack@eecs.umich.edu 1004688Sgblack@eecs.umich.edu if(%(cond_check)s) 1014688Sgblack@eecs.umich.edu { 1024688Sgblack@eecs.umich.edu %(code)s; 1034688Sgblack@eecs.umich.edu %(flag_code)s; 1044688Sgblack@eecs.umich.edu } 1054708Sgblack@eecs.umich.edu else 1064708Sgblack@eecs.umich.edu { 1074708Sgblack@eecs.umich.edu %(else_code)s; 1084708Sgblack@eecs.umich.edu } 1094519Sgblack@eecs.umich.edu 1104519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1114519Sgblack@eecs.umich.edu if(fault == NoFault) 1124519Sgblack@eecs.umich.edu { 1134519Sgblack@eecs.umich.edu %(op_wb)s; 1144519Sgblack@eecs.umich.edu } 1154519Sgblack@eecs.umich.edu return fault; 1164519Sgblack@eecs.umich.edu } 1174519Sgblack@eecs.umich.edu}}; 1184519Sgblack@eecs.umich.edu 1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1204519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu protected: 1234519Sgblack@eecs.umich.edu void buildMe(); 1244519Sgblack@eecs.umich.edu 1254519Sgblack@eecs.umich.edu public: 1264519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1274519Sgblack@eecs.umich.edu const char * instMnem, 1284519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1296345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1304712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1334519Sgblack@eecs.umich.edu const char * instMnem, 1346345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1354712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1364519Sgblack@eecs.umich.edu 1374519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1384519Sgblack@eecs.umich.edu }; 1394519Sgblack@eecs.umich.edu}}; 1404519Sgblack@eecs.umich.edu 1414519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1424519Sgblack@eecs.umich.edu 1434951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1444519Sgblack@eecs.umich.edu { 1454519Sgblack@eecs.umich.edu protected: 1464519Sgblack@eecs.umich.edu void buildMe(); 1474519Sgblack@eecs.umich.edu 1484519Sgblack@eecs.umich.edu public: 1494951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1504519Sgblack@eecs.umich.edu const char * instMnem, 1514519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1526345Sgblack@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 1534712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1544519Sgblack@eecs.umich.edu 1554951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1564519Sgblack@eecs.umich.edu const char * instMnem, 1576345Sgblack@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 1584712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1594519Sgblack@eecs.umich.edu 1604519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1614519Sgblack@eecs.umich.edu }; 1624519Sgblack@eecs.umich.edu}}; 1634519Sgblack@eecs.umich.edu 1644519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1654519Sgblack@eecs.umich.edu 1664519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1674519Sgblack@eecs.umich.edu { 1684519Sgblack@eecs.umich.edu %(constructor)s; 1694519Sgblack@eecs.umich.edu } 1704519Sgblack@eecs.umich.edu 1714519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1724519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1736345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1744712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1754519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1764581Sgblack@eecs.umich.edu false, false, false, false, 1774688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1784581Sgblack@eecs.umich.edu %(op_class)s) 1794519Sgblack@eecs.umich.edu { 1804519Sgblack@eecs.umich.edu buildMe(); 1814519Sgblack@eecs.umich.edu } 1824519Sgblack@eecs.umich.edu 1834519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1844519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1854519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1866345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1874712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1884519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1894581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1904688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1914581Sgblack@eecs.umich.edu %(op_class)s) 1924519Sgblack@eecs.umich.edu { 1934519Sgblack@eecs.umich.edu buildMe(); 1944519Sgblack@eecs.umich.edu } 1954519Sgblack@eecs.umich.edu}}; 1964519Sgblack@eecs.umich.edu 1974519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1984519Sgblack@eecs.umich.edu 1994951Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 2004519Sgblack@eecs.umich.edu { 2014519Sgblack@eecs.umich.edu %(constructor)s; 2024519Sgblack@eecs.umich.edu } 2034519Sgblack@eecs.umich.edu 2044951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2054519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2066345Sgblack@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 2074712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2084519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2094581Sgblack@eecs.umich.edu false, false, false, false, 2104688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2114581Sgblack@eecs.umich.edu %(op_class)s) 2124519Sgblack@eecs.umich.edu { 2134519Sgblack@eecs.umich.edu buildMe(); 2144519Sgblack@eecs.umich.edu } 2154519Sgblack@eecs.umich.edu 2164951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2174519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2184519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2196345Sgblack@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 2204712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2214519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2224581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2234688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2244581Sgblack@eecs.umich.edu %(op_class)s) 2254519Sgblack@eecs.umich.edu { 2264519Sgblack@eecs.umich.edu buildMe(); 2274519Sgblack@eecs.umich.edu } 2284519Sgblack@eecs.umich.edu}}; 2294519Sgblack@eecs.umich.edu 2305075Sgblack@eecs.umich.eduoutput header {{ 2315075Sgblack@eecs.umich.edu void 2325075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2335075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 2345428Sgblack@eecs.umich.edu 2355428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 2365674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 2375899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 2385936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 2395428Sgblack@eecs.umich.edu }; 2405678Sgblack@eecs.umich.edu 2415678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 2425678Sgblack@eecs.umich.edu LDT64 = 2, 2435678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 2445678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 2455678Sgblack@eecs.umich.edu CallGate64 = 0xc, 2465678Sgblack@eecs.umich.edu IntGate64 = 0xe, 2475678Sgblack@eecs.umich.edu TrapGate64 = 0xf 2485678Sgblack@eecs.umich.edu }; 2495075Sgblack@eecs.umich.edu}}; 2505075Sgblack@eecs.umich.edu 2515075Sgblack@eecs.umich.eduoutput decoder {{ 2525075Sgblack@eecs.umich.edu void 2535075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2545075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 2555075Sgblack@eecs.umich.edu { 2565075Sgblack@eecs.umich.edu //Check for divide by zero. 2575075Sgblack@eecs.umich.edu if (divisor == 0) 2585075Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 2595075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 2605075Sgblack@eecs.umich.edu if (divisor <= dividend) { 2615075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 2625075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 2635075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 2645075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 2655075Sgblack@eecs.umich.edu divisor <<= shift; 2665075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 2675075Sgblack@eecs.umich.edu //now larger than the dividend. 2685075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 2695075Sgblack@eecs.umich.edu quotientBit <<= shift; 2705075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2715075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2725075Sgblack@eecs.umich.edu //part of one or two bit division. 2735075Sgblack@eecs.umich.edu if (divisor > dividend) { 2745075Sgblack@eecs.umich.edu quotientBit >>= 1; 2755075Sgblack@eecs.umich.edu divisor >>= 1; 2765075Sgblack@eecs.umich.edu } 2775075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2785075Sgblack@eecs.umich.edu quotient += quotientBit; 2795075Sgblack@eecs.umich.edu remainder -= divisor; 2805075Sgblack@eecs.umich.edu } 2815075Sgblack@eecs.umich.edu } 2825075Sgblack@eecs.umich.edu}}; 2835075Sgblack@eecs.umich.edu 2844519Sgblack@eecs.umich.edulet {{ 2855040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2865040Sgblack@eecs.umich.edu # them will always work. 2875040Sgblack@eecs.umich.edu header_output = "" 2885040Sgblack@eecs.umich.edu decoder_output = "" 2895040Sgblack@eecs.umich.edu exec_output = "" 2905040Sgblack@eecs.umich.edu 2915040Sgblack@eecs.umich.edu immTemplates = ( 2925040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2935040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2945040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2955040Sgblack@eecs.umich.edu 2965040Sgblack@eecs.umich.edu regTemplates = ( 2975040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2985040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2995040Sgblack@eecs.umich.edu MicroRegOpExecute) 3005040Sgblack@eecs.umich.edu 3015040Sgblack@eecs.umich.edu class RegOpMeta(type): 3025040Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 3035040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code): 3045040Sgblack@eecs.umich.edu 3055040Sgblack@eecs.umich.edu # Globals to stick the output in 3065040Sgblack@eecs.umich.edu global header_output 3075040Sgblack@eecs.umich.edu global decoder_output 3085040Sgblack@eecs.umich.edu global exec_output 3095040Sgblack@eecs.umich.edu 3105040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 3115040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3125040Sgblack@eecs.umich.edu 3135040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3145040Sgblack@eecs.umich.edu # of this code. 3155062Sgblack@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 3165062Sgblack@eecs.umich.edu match = matcher.search(allCode) 3175062Sgblack@eecs.umich.edu if match: 3185062Sgblack@eecs.umich.edu typeQual = "" 3195062Sgblack@eecs.umich.edu if match.group("typeQual"): 3205062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 3215062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3225040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3235062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 3245062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 3255062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 3265062Sgblack@eecs.umich.edu matcher.sub(src2_name, else_code)) 3275040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 3285040Sgblack@eecs.umich.edu matcher.sub("imm8", code), 3295040Sgblack@eecs.umich.edu matcher.sub("imm8", flag_code), 3305040Sgblack@eecs.umich.edu matcher.sub("imm8", cond_check), 3315040Sgblack@eecs.umich.edu matcher.sub("imm8", else_code)) 3325040Sgblack@eecs.umich.edu return 3335040Sgblack@eecs.umich.edu 3345040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 3355040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 3365239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 3375040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3385040Sgblack@eecs.umich.edu code, "", "true", else_code) 3395040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 3405040Sgblack@eecs.umich.edu 3415040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 3425040Sgblack@eecs.umich.edu # compute it. 3435040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 3445040Sgblack@eecs.umich.edu if matcher.search(allCode): 3455061Sgblack@eecs.umich.edu code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3465040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 3475040Sgblack@eecs.umich.edu if matcher.search(allCode): 3485061Sgblack@eecs.umich.edu code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3495061Sgblack@eecs.umich.edu # Also make available versions which do sign extension 3505061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3515061Sgblack@eecs.umich.edu if matcher.search(allCode): 3525061Sgblack@eecs.umich.edu code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3535061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3545061Sgblack@eecs.umich.edu if matcher.search(allCode): 3555061Sgblack@eecs.umich.edu code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3565040Sgblack@eecs.umich.edu 3575040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3585040Sgblack@eecs.umich.edu 3595040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3605040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3615040Sgblack@eecs.umich.edu templates = regTemplates 3625040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)imm8(?!\w)") 3635040Sgblack@eecs.umich.edu if matcher.search(allCode): 3645040Sgblack@eecs.umich.edu base += "Imm" 3655040Sgblack@eecs.umich.edu templates = immTemplates 3665040Sgblack@eecs.umich.edu 3675040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3685040Sgblack@eecs.umich.edu iop = InstObjParams(name, Name + suffix, base, 3695040Sgblack@eecs.umich.edu {"code" : code, 3705040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3715040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3725040Sgblack@eecs.umich.edu "else_code" : else_code}) 3735040Sgblack@eecs.umich.edu 3745040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3755040Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3765040Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3775040Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3785040Sgblack@eecs.umich.edu 3795040Sgblack@eecs.umich.edu 3805040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3814688Sgblack@eecs.umich.edu abstract = False 3825040Sgblack@eecs.umich.edu name = Name.lower() 3834688Sgblack@eecs.umich.edu if "abstract" in dict: 3844688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3854688Sgblack@eecs.umich.edu del dict['abstract'] 3864688Sgblack@eecs.umich.edu 3875040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3884688Sgblack@eecs.umich.edu if not abstract: 3895040Sgblack@eecs.umich.edu cls.className = Name 3905040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3915040Sgblack@eecs.umich.edu code = cls.code 3925040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3935040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3945040Sgblack@eecs.umich.edu else_code = cls.else_code 3955040Sgblack@eecs.umich.edu 3965040Sgblack@eecs.umich.edu # Set up the C++ classes 3975040Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", 3985040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code) 3995040Sgblack@eecs.umich.edu 4005040Sgblack@eecs.umich.edu # Hook into the microassembler dict 4015040Sgblack@eecs.umich.edu global microopClasses 4025040Sgblack@eecs.umich.edu microopClasses[name] = cls 4035040Sgblack@eecs.umich.edu 4045040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 4055040Sgblack@eecs.umich.edu 4065040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 4075040Sgblack@eecs.umich.edu # of this code. 4085040Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 4095040Sgblack@eecs.umich.edu if matcher.search(allCode): 4105040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 4114688Sgblack@eecs.umich.edu return cls 4124688Sgblack@eecs.umich.edu 4135040Sgblack@eecs.umich.edu 4145040Sgblack@eecs.umich.edu class RegOp(X86Microop): 4155040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 4165040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 4174688Sgblack@eecs.umich.edu abstract = True 4184688Sgblack@eecs.umich.edu 4195040Sgblack@eecs.umich.edu # Default template parameter values 4205040Sgblack@eecs.umich.edu flag_code = "" 4215040Sgblack@eecs.umich.edu cond_check = "true" 4225040Sgblack@eecs.umich.edu else_code = ";" 4235040Sgblack@eecs.umich.edu 4245040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4254519Sgblack@eecs.umich.edu self.dest = dest 4264519Sgblack@eecs.umich.edu self.src1 = src1 4275040Sgblack@eecs.umich.edu self.op2 = op2 4284688Sgblack@eecs.umich.edu self.flags = flags 4294701Sgblack@eecs.umich.edu self.dataSize = dataSize 4304688Sgblack@eecs.umich.edu if flags is None: 4314688Sgblack@eecs.umich.edu self.ext = 0 4324688Sgblack@eecs.umich.edu else: 4334688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4344688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4354688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 4364688Sgblack@eecs.umich.edu self.className += "Flags" 4374519Sgblack@eecs.umich.edu 4384519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 4395040Sgblack@eecs.umich.edu className = self.className 4405040Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4415040Sgblack@eecs.umich.edu className += "Imm" 4425788Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock 4435040Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4444688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4455040Sgblack@eecs.umich.edu "class_name" : className, 4464519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4475040Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4484519Sgblack@eecs.umich.edu "dest" : self.dest, 4494519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4504519Sgblack@eecs.umich.edu "ext" : self.ext} 4514539Sgblack@eecs.umich.edu return allocator 4524519Sgblack@eecs.umich.edu 4535040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4544688Sgblack@eecs.umich.edu abstract = True 4555040Sgblack@eecs.umich.edu flag_code = ''' 4565040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4575115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4585040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4595040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4605040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 4615115Sgblack@eecs.umich.edu ccFlagBits &= ~(ECFBit & ext); 4625040Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 4635040Sgblack@eecs.umich.edu ''' 4644519Sgblack@eecs.umich.edu 4655040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4665040Sgblack@eecs.umich.edu abstract = True 4675040Sgblack@eecs.umich.edu flag_code = \ 4685040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4694519Sgblack@eecs.umich.edu 4705040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4715040Sgblack@eecs.umich.edu abstract = True 4725040Sgblack@eecs.umich.edu flag_code = \ 4735040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4744519Sgblack@eecs.umich.edu 4755040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4765040Sgblack@eecs.umich.edu abstract = True 4775083Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits, ext)" 4784519Sgblack@eecs.umich.edu 4795063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4805063Sgblack@eecs.umich.edu abstract = True 4815063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4825063Sgblack@eecs.umich.edu if not src1: 4835063Sgblack@eecs.umich.edu src1 = dest 4846345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4856345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4865063Sgblack@eecs.umich.edu 4875063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4885063Sgblack@eecs.umich.edu abstract = True 4895063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4906345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4916345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 4925063Sgblack@eecs.umich.edu 4935040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4945040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4954595Sgblack@eecs.umich.edu 4965040Sgblack@eecs.umich.edu class Or(LogicRegOp): 4975040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4984595Sgblack@eecs.umich.edu 4995040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 5005040Sgblack@eecs.umich.edu code = ''' 5014732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5025138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 5035040Sgblack@eecs.umich.edu ''' 5045040Sgblack@eecs.umich.edu 5055040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 5065040Sgblack@eecs.umich.edu code = ''' 5074732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5085138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 5095040Sgblack@eecs.umich.edu ''' 5105040Sgblack@eecs.umich.edu 5115040Sgblack@eecs.umich.edu class And(LogicRegOp): 5125040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 5135040Sgblack@eecs.umich.edu 5145040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5155040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 5165040Sgblack@eecs.umich.edu 5175040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5185040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 5195040Sgblack@eecs.umich.edu 5205065Sgblack@eecs.umich.edu # Neither of these is quite correct because it assumes that right shifting 5215065Sgblack@eecs.umich.edu # a signed or unsigned value does sign or zero extension respectively. 5225065Sgblack@eecs.umich.edu # The C standard says that what happens on a right shift with a 1 in the 5235065Sgblack@eecs.umich.edu # MSB position is undefined. On x86 and under likely most compilers the 5245065Sgblack@eecs.umich.edu # "right thing" happens, but this isn't a guarantee. 5255063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5265040Sgblack@eecs.umich.edu code = ''' 5275063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5285063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5295063Sgblack@eecs.umich.edu int64_t spsrc1_h = spsrc1 >> halfSize; 5305063Sgblack@eecs.umich.edu int64_t spsrc1_l = spsrc1 & mask(halfSize); 5315063Sgblack@eecs.umich.edu int64_t spsrc2_h = sop2 >> halfSize; 5325063Sgblack@eecs.umich.edu int64_t spsrc2_l = sop2 & mask(halfSize); 5335063Sgblack@eecs.umich.edu ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l + 5345063Sgblack@eecs.umich.edu ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) + 5355063Sgblack@eecs.umich.edu spsrc1_h * spsrc2_h; 5365040Sgblack@eecs.umich.edu ''' 5375040Sgblack@eecs.umich.edu 5385063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5395040Sgblack@eecs.umich.edu code = ''' 5405063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5414809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5425063Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 >> halfSize; 5435063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5445063Sgblack@eecs.umich.edu uint64_t psrc2_h = op2 >> halfSize; 5455063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5465063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5475063Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) + 5485063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5495040Sgblack@eecs.umich.edu ''' 5505040Sgblack@eecs.umich.edu 5515063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5525063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5535040Sgblack@eecs.umich.edu 5545063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5555063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5565063Sgblack@eecs.umich.edu if not src1: 5575063Sgblack@eecs.umich.edu src1 = dest 5586345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 5596345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 5605063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5615063Sgblack@eecs.umich.edu flag_code = ''' 5625063Sgblack@eecs.umich.edu if (ProdHi) 5635063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5645063Sgblack@eecs.umich.edu else 5655063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5665063Sgblack@eecs.umich.edu ''' 5675062Sgblack@eecs.umich.edu 5685075Sgblack@eecs.umich.edu # One or two bit divide 5695075Sgblack@eecs.umich.edu class Div1(WrRegOp): 5705040Sgblack@eecs.umich.edu code = ''' 5715075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 5725075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5735075Sgblack@eecs.umich.edu uint64_t quotient = 0; 5745075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 5755075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 5765075Sgblack@eecs.umich.edu //a source. 5775075Sgblack@eecs.umich.edu uint64_t divisor = op2; 5785075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 5795075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 5805075Sgblack@eecs.umich.edu //Do the division. 5815075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5825075Sgblack@eecs.umich.edu //Record the final results. 5835075Sgblack@eecs.umich.edu Remainder = remainder; 5845075Sgblack@eecs.umich.edu Quotient = quotient; 5855075Sgblack@eecs.umich.edu Divisor = divisor; 5865040Sgblack@eecs.umich.edu ''' 5874823Sgblack@eecs.umich.edu 5885075Sgblack@eecs.umich.edu # Step divide 5895075Sgblack@eecs.umich.edu class Div2(RegOp): 5905075Sgblack@eecs.umich.edu code = ''' 5915075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 5925075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 5935075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 5945075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 5955075Sgblack@eecs.umich.edu int remaining = op2; 5965075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 5975075Sgblack@eecs.umich.edu //little. 5985075Sgblack@eecs.umich.edu if (remaining) { 5995075Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 6005075Sgblack@eecs.umich.edu while(dividend < divisor && remaining) { 6015075Sgblack@eecs.umich.edu dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 6025075Sgblack@eecs.umich.edu quotient <<= 1; 6035075Sgblack@eecs.umich.edu remaining--; 6045075Sgblack@eecs.umich.edu } 6055075Sgblack@eecs.umich.edu remainder = dividend; 6065075Sgblack@eecs.umich.edu //Do the division. 6075075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6085075Sgblack@eecs.umich.edu } 6095075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 6105075Sgblack@eecs.umich.edu DestReg = merge(DestReg, remaining, dataSize); 6115075Sgblack@eecs.umich.edu //Record the final results 6125075Sgblack@eecs.umich.edu Remainder = remainder; 6135075Sgblack@eecs.umich.edu Quotient = quotient; 6145075Sgblack@eecs.umich.edu ''' 6155075Sgblack@eecs.umich.edu flag_code = ''' 6165075Sgblack@eecs.umich.edu if (DestReg == 0) 6175075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & EZFBit); 6185075Sgblack@eecs.umich.edu else 6195075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6205075Sgblack@eecs.umich.edu ''' 6214732Sgblack@eecs.umich.edu 6225075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6235075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6245075Sgblack@eecs.umich.edu 6255075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6265075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6275040Sgblack@eecs.umich.edu 6285040Sgblack@eecs.umich.edu class Mov(CondRegOp): 6295040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6305040Sgblack@eecs.umich.edu else_code = 'DestReg=DestReg;' 6315040Sgblack@eecs.umich.edu 6324732Sgblack@eecs.umich.edu # Shift instructions 6335040Sgblack@eecs.umich.edu 6345076Sgblack@eecs.umich.edu class Sll(RegOp): 6355040Sgblack@eecs.umich.edu code = ''' 6364756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6374823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6385040Sgblack@eecs.umich.edu ''' 6395076Sgblack@eecs.umich.edu flag_code = ''' 6405076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6415076Sgblack@eecs.umich.edu if (shiftAmt) { 6425076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6435076Sgblack@eecs.umich.edu //worry about setting them. 6445076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6455076Sgblack@eecs.umich.edu int CFBits = 0; 6465076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 6475076Sgblack@eecs.umich.edu if (bits(SrcReg1, dataSize * 8 - shiftAmt)) 6485076Sgblack@eecs.umich.edu CFBits = 1; 6495076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6505076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 6515076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6525076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6535076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 6545076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6555076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6565076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6575076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6585076Sgblack@eecs.umich.edu } 6595076Sgblack@eecs.umich.edu ''' 6605040Sgblack@eecs.umich.edu 6615076Sgblack@eecs.umich.edu class Srl(RegOp): 6625040Sgblack@eecs.umich.edu code = ''' 6634756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6644732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6654732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 6664732Sgblack@eecs.umich.edu // to be sure they're zero. 6674732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 6684823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 6695040Sgblack@eecs.umich.edu ''' 6705076Sgblack@eecs.umich.edu flag_code = ''' 6715076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6725076Sgblack@eecs.umich.edu if (shiftAmt) { 6735076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6745076Sgblack@eecs.umich.edu //worry about setting them. 6755076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6765076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6775076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 6785076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6795076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6805076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 6815076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6825076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6835076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6845076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6855076Sgblack@eecs.umich.edu } 6865076Sgblack@eecs.umich.edu ''' 6875040Sgblack@eecs.umich.edu 6885076Sgblack@eecs.umich.edu class Sra(RegOp): 6895040Sgblack@eecs.umich.edu code = ''' 6904756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6914732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6924732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 6934732Sgblack@eecs.umich.edu // them manually to be sure. 6944732Sgblack@eecs.umich.edu uint64_t arithMask = 6955032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 6964823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 6975040Sgblack@eecs.umich.edu ''' 6985076Sgblack@eecs.umich.edu flag_code = ''' 6995076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7005076Sgblack@eecs.umich.edu if (shiftAmt) { 7015076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7025076Sgblack@eecs.umich.edu //worry about setting them. 7035076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7045076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7055076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 7065076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7075076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7085076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7095076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7105076Sgblack@eecs.umich.edu } 7115076Sgblack@eecs.umich.edu ''' 7125040Sgblack@eecs.umich.edu 7135076Sgblack@eecs.umich.edu class Ror(RegOp): 7145040Sgblack@eecs.umich.edu code = ''' 7154732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7164756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7174732Sgblack@eecs.umich.edu if(shiftAmt) 7184732Sgblack@eecs.umich.edu { 7194823Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 7204823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 7214732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7224732Sgblack@eecs.umich.edu } 7234732Sgblack@eecs.umich.edu else 7244732Sgblack@eecs.umich.edu DestReg = DestReg; 7255040Sgblack@eecs.umich.edu ''' 7265076Sgblack@eecs.umich.edu flag_code = ''' 7275076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7285076Sgblack@eecs.umich.edu if (shiftAmt) { 7295076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7305076Sgblack@eecs.umich.edu //worry about setting them. 7315076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7325076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 7335076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7345076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 7355076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7365076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && msb) 7375076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7385076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7395076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 7405076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7415076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7425076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7435076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7445076Sgblack@eecs.umich.edu } 7455076Sgblack@eecs.umich.edu ''' 7465040Sgblack@eecs.umich.edu 7475076Sgblack@eecs.umich.edu class Rcr(RegOp): 7485040Sgblack@eecs.umich.edu code = ''' 7494733Sgblack@eecs.umich.edu uint8_t shiftAmt = 7504756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7514733Sgblack@eecs.umich.edu if(shiftAmt) 7524733Sgblack@eecs.umich.edu { 7534733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 7545138Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - shiftAmt); 7554733Sgblack@eecs.umich.edu if(shiftAmt > 1) 7564823Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 7574823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 7584733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7594733Sgblack@eecs.umich.edu } 7604733Sgblack@eecs.umich.edu else 7614733Sgblack@eecs.umich.edu DestReg = DestReg; 7625040Sgblack@eecs.umich.edu ''' 7635076Sgblack@eecs.umich.edu flag_code = ''' 7645076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7655076Sgblack@eecs.umich.edu if (shiftAmt) { 7665076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7675076Sgblack@eecs.umich.edu //worry about setting them. 7685076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7695076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7705076Sgblack@eecs.umich.edu if ((ext & OFBit) && ((ccFlagBits & CFBit) ^ 7715076Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) 7725076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7735076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7745076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 7755076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7765076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7775076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7785076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7795076Sgblack@eecs.umich.edu } 7805076Sgblack@eecs.umich.edu ''' 7815040Sgblack@eecs.umich.edu 7825076Sgblack@eecs.umich.edu class Rol(RegOp): 7835040Sgblack@eecs.umich.edu code = ''' 7844732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7854756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7864732Sgblack@eecs.umich.edu if(shiftAmt) 7874732Sgblack@eecs.umich.edu { 7884823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 7894732Sgblack@eecs.umich.edu uint64_t bottom = 7904823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 7914732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7924732Sgblack@eecs.umich.edu } 7934732Sgblack@eecs.umich.edu else 7944732Sgblack@eecs.umich.edu DestReg = DestReg; 7955040Sgblack@eecs.umich.edu ''' 7965076Sgblack@eecs.umich.edu flag_code = ''' 7975076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7985076Sgblack@eecs.umich.edu if (shiftAmt) { 7995076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8005076Sgblack@eecs.umich.edu //worry about setting them. 8015076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8025076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 8035076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 8045076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8055076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8065076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && lsb) 8075076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8085076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8095076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 8105076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8115076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8125076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8135076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8145076Sgblack@eecs.umich.edu } 8155076Sgblack@eecs.umich.edu ''' 8165040Sgblack@eecs.umich.edu 8175076Sgblack@eecs.umich.edu class Rcl(RegOp): 8185040Sgblack@eecs.umich.edu code = ''' 8194733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8204756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8214733Sgblack@eecs.umich.edu if(shiftAmt) 8224733Sgblack@eecs.umich.edu { 8234733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8244823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 8255138Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (shiftAmt - 1); 8264733Sgblack@eecs.umich.edu if(shiftAmt > 1) 8274733Sgblack@eecs.umich.edu bottom |= 8284823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 8294809Sgblack@eecs.umich.edu dataSize * 8 - shiftAmt + 1); 8304733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8314733Sgblack@eecs.umich.edu } 8324733Sgblack@eecs.umich.edu else 8334733Sgblack@eecs.umich.edu DestReg = DestReg; 8345040Sgblack@eecs.umich.edu ''' 8355076Sgblack@eecs.umich.edu flag_code = ''' 8365076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8375076Sgblack@eecs.umich.edu if (shiftAmt) { 8385076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8395076Sgblack@eecs.umich.edu //worry about setting them. 8405076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8415076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8425076Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt); 8435076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8445076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 8455076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8465076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8475076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 8485076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8495076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8505076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8515076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8525076Sgblack@eecs.umich.edu } 8535076Sgblack@eecs.umich.edu ''' 8544732Sgblack@eecs.umich.edu 8555040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 8565246Sgblack@eecs.umich.edu code = 'RIP = psrc1 + sop2 + CSBase' 8575040Sgblack@eecs.umich.edu else_code="RIP = RIP;" 8585040Sgblack@eecs.umich.edu 8595040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 8605040Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 8615040Sgblack@eecs.umich.edu 8625426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 8635426Sgblack@eecs.umich.edu code = ''' 8645426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 8655426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 8665426Sgblack@eecs.umich.edu // Get only the user flags 8675426Sgblack@eecs.umich.edu ccFlagBits = newFlags & userFlagMask; 8685426Sgblack@eecs.umich.edu // Get everything else 8695426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 8705426Sgblack@eecs.umich.edu ''' 8715426Sgblack@eecs.umich.edu 8725040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 8735246Sgblack@eecs.umich.edu code = 'DestReg = RIP - CSBase' 8745040Sgblack@eecs.umich.edu 8755040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 8765040Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 8775040Sgblack@eecs.umich.edu 8785426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 8795426Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits | nccFlagBits' 8805426Sgblack@eecs.umich.edu 8815040Sgblack@eecs.umich.edu class Ruflag(RegOp): 8825040Sgblack@eecs.umich.edu code = ''' 8835116Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8); 8844951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 8855011Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 8865011Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 8875040Sgblack@eecs.umich.edu ''' 8885040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 8895040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 8905040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 8916345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 8924732Sgblack@eecs.umich.edu 8935426Sgblack@eecs.umich.edu class Rflag(RegOp): 8945426Sgblack@eecs.umich.edu code = ''' 8955426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 8965426Sgblack@eecs.umich.edu MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 8975426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 8985426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 8995426Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 9005426Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 9015426Sgblack@eecs.umich.edu ''' 9025426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 9035426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 9045426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 9056345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 9065426Sgblack@eecs.umich.edu 9075040Sgblack@eecs.umich.edu class Sext(RegOp): 9085040Sgblack@eecs.umich.edu code = ''' 9094823Sgblack@eecs.umich.edu IntReg val = psrc1; 9105239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 9115239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 9125239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 9135239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 9145007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 9155007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 9165040Sgblack@eecs.umich.edu ''' 9175239Sgblack@eecs.umich.edu flag_code = ''' 9185239Sgblack@eecs.umich.edu if (!sign_bit) 9195239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & 9205239Sgblack@eecs.umich.edu ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 9215239Sgblack@eecs.umich.edu else 9225239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | 9235239Sgblack@eecs.umich.edu (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 9245239Sgblack@eecs.umich.edu ''' 9254714Sgblack@eecs.umich.edu 9265040Sgblack@eecs.umich.edu class Zext(RegOp): 9275927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 9285241Sgblack@eecs.umich.edu 9295926Sgblack@eecs.umich.edu class Rddr(RegOp): 9305926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9315926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 9326345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 9335926Sgblack@eecs.umich.edu code = ''' 9345926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 9355926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 9365926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 9375926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 9385926Sgblack@eecs.umich.edu } else if (dr7.gd) { 9395926Sgblack@eecs.umich.edu fault = new DebugException(); 9405926Sgblack@eecs.umich.edu } else { 9415926Sgblack@eecs.umich.edu DestReg = merge(DestReg, DebugSrc1, dataSize); 9425926Sgblack@eecs.umich.edu } 9435926Sgblack@eecs.umich.edu ''' 9445926Sgblack@eecs.umich.edu 9455926Sgblack@eecs.umich.edu class Wrdr(RegOp): 9465926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9475926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 9486345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 9495926Sgblack@eecs.umich.edu code = ''' 9505926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 9515926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 9525926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 9535926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 9546345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 9555926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 9565926Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9575926Sgblack@eecs.umich.edu } else if (dr7.gd) { 9585926Sgblack@eecs.umich.edu fault = new DebugException(); 9595926Sgblack@eecs.umich.edu } else { 9605926Sgblack@eecs.umich.edu DebugDest = psrc1; 9615926Sgblack@eecs.umich.edu } 9625926Sgblack@eecs.umich.edu ''' 9635926Sgblack@eecs.umich.edu 9645296Sgblack@eecs.umich.edu class Rdcr(RegOp): 9655296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9665296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 9676345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 9685296Sgblack@eecs.umich.edu code = ''' 9695924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 9705296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 9715296Sgblack@eecs.umich.edu } else { 9725934Sgblack@eecs.umich.edu DestReg = merge(DestReg, ControlSrc1, dataSize); 9735296Sgblack@eecs.umich.edu } 9745296Sgblack@eecs.umich.edu ''' 9755296Sgblack@eecs.umich.edu 9765241Sgblack@eecs.umich.edu class Wrcr(RegOp): 9775241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9785241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 9796345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 9805241Sgblack@eecs.umich.edu code = ''' 9815241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 9825241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 9835241Sgblack@eecs.umich.edu } else { 9845241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 9855241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 9865241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 9875241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 9885241Sgblack@eecs.umich.edu 9895241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 9905241Sgblack@eecs.umich.edu switch(dest) { 9915241Sgblack@eecs.umich.edu case 0: 9925241Sgblack@eecs.umich.edu { 9935241Sgblack@eecs.umich.edu Efer efer = EferOp; 9945241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 9955241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 9965241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 9975241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 9985241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 9995241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 10005241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 10015241Sgblack@eecs.umich.edu } 10025241Sgblack@eecs.umich.edu break; 10035241Sgblack@eecs.umich.edu case 2: 10045241Sgblack@eecs.umich.edu break; 10055241Sgblack@eecs.umich.edu case 3: 10065241Sgblack@eecs.umich.edu break; 10075241Sgblack@eecs.umich.edu case 4: 10085241Sgblack@eecs.umich.edu { 10095241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 10105241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 10115241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 10125241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 10135241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 10145241Sgblack@eecs.umich.edu } 10155241Sgblack@eecs.umich.edu break; 10165241Sgblack@eecs.umich.edu case 8: 10175241Sgblack@eecs.umich.edu { 10185241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 10195241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 10205241Sgblack@eecs.umich.edu } 10215241Sgblack@eecs.umich.edu default: 10225241Sgblack@eecs.umich.edu panic("Unrecognized control register %d.\\n", dest); 10235241Sgblack@eecs.umich.edu } 10245241Sgblack@eecs.umich.edu ControlDest = newVal; 10255241Sgblack@eecs.umich.edu } 10265241Sgblack@eecs.umich.edu ''' 10275290Sgblack@eecs.umich.edu 10285294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 10295672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 10305294Sgblack@eecs.umich.edu abstract = True 10315290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10325294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 10336345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10345294Sgblack@eecs.umich.edu 10355294Sgblack@eecs.umich.edu class Wrbase(SegOp): 10365290Sgblack@eecs.umich.edu code = ''' 10375294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 10385290Sgblack@eecs.umich.edu ''' 10395290Sgblack@eecs.umich.edu 10405294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 10415290Sgblack@eecs.umich.edu code = ''' 10425294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 10435294Sgblack@eecs.umich.edu ''' 10445294Sgblack@eecs.umich.edu 10455294Sgblack@eecs.umich.edu class Wrsel(SegOp): 10465294Sgblack@eecs.umich.edu code = ''' 10475294Sgblack@eecs.umich.edu SegSelDest = psrc1; 10485294Sgblack@eecs.umich.edu ''' 10495294Sgblack@eecs.umich.edu 10505905Sgblack@eecs.umich.edu class WrAttr(SegOp): 10515905Sgblack@eecs.umich.edu code = ''' 10525905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 10535905Sgblack@eecs.umich.edu ''' 10545905Sgblack@eecs.umich.edu 10555294Sgblack@eecs.umich.edu class Rdbase(SegOp): 10565294Sgblack@eecs.umich.edu code = ''' 10575932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegBaseSrc1, dataSize); 10585294Sgblack@eecs.umich.edu ''' 10595294Sgblack@eecs.umich.edu 10605294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 10615294Sgblack@eecs.umich.edu code = ''' 10625932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegLimitSrc1, dataSize); 10635294Sgblack@eecs.umich.edu ''' 10645294Sgblack@eecs.umich.edu 10655427Sgblack@eecs.umich.edu class RdAttr(SegOp): 10665427Sgblack@eecs.umich.edu code = ''' 10675932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegAttrSrc1, dataSize); 10685427Sgblack@eecs.umich.edu ''' 10695427Sgblack@eecs.umich.edu 10705294Sgblack@eecs.umich.edu class Rdsel(SegOp): 10715294Sgblack@eecs.umich.edu code = ''' 10725932Sgblack@eecs.umich.edu DestReg = merge(DestReg, SegSelSrc1, dataSize); 10735294Sgblack@eecs.umich.edu ''' 10745294Sgblack@eecs.umich.edu 10755682Sgblack@eecs.umich.edu class Rdval(RegOp): 10765682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10776345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 10786345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10795682Sgblack@eecs.umich.edu code = ''' 10805682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 10815682Sgblack@eecs.umich.edu ''' 10825682Sgblack@eecs.umich.edu 10835682Sgblack@eecs.umich.edu class Wrval(RegOp): 10845682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10856345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 10866345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 10875682Sgblack@eecs.umich.edu code = ''' 10885682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 10895682Sgblack@eecs.umich.edu ''' 10905682Sgblack@eecs.umich.edu 10915428Sgblack@eecs.umich.edu class Chks(RegOp): 10925428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 10935428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 10945428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 10955428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 10965294Sgblack@eecs.umich.edu code = ''' 10975424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 10985433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 10995433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 11005433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 11015294Sgblack@eecs.umich.edu 11025428Sgblack@eecs.umich.edu switch (imm8) 11035428Sgblack@eecs.umich.edu { 11045428Sgblack@eecs.umich.edu case SegNoCheck: 11055428Sgblack@eecs.umich.edu break; 11065428Sgblack@eecs.umich.edu case SegCSCheck: 11076060Sgblack@eecs.umich.edu // Make sure it's the right type 11086060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 11096060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11106060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 11116060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11126060Sgblack@eecs.umich.edu } 11135428Sgblack@eecs.umich.edu break; 11145428Sgblack@eecs.umich.edu case SegCallGateCheck: 11155428Sgblack@eecs.umich.edu panic("CS checks for far calls/jumps through call gates" 11165428Sgblack@eecs.umich.edu "not implemented.\\n"); 11175428Sgblack@eecs.umich.edu break; 11185855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 11195853Sgblack@eecs.umich.edu // Check permissions. 11205674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 11215857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 11226058Sgblack@eecs.umich.edu break; 11235674Sgblack@eecs.umich.edu } 11245855Sgblack@eecs.umich.edu // Fall through on purpose 11255855Sgblack@eecs.umich.edu case SegIntGateCheck: 11265853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 11275861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 11285853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 11295853Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 11305853Sgblack@eecs.umich.edu } 11315674Sgblack@eecs.umich.edu break; 11325428Sgblack@eecs.umich.edu case SegSSCheck: 11335433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 11345433Sgblack@eecs.umich.edu if (!desc.p) { 11355857Sgblack@eecs.umich.edu fault = new StackFault(selector); 11365433Sgblack@eecs.umich.edu } 11375433Sgblack@eecs.umich.edu } else { 11385673Sgblack@eecs.umich.edu if ((m5reg.submode != SixtyFourBitMode || 11395673Sgblack@eecs.umich.edu m5reg.cpl == 3) || 11405433Sgblack@eecs.umich.edu !(desc.s == 1 && 11415433Sgblack@eecs.umich.edu desc.type.codeOrData == 0 && desc.type.w) || 11425433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 11435433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 11445857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 11455433Sgblack@eecs.umich.edu } 11465433Sgblack@eecs.umich.edu } 11475428Sgblack@eecs.umich.edu break; 11485428Sgblack@eecs.umich.edu case SegIretCheck: 11495428Sgblack@eecs.umich.edu { 11505433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 11515433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 11525433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 11535433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 11545679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 11555857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 11565679Sgblack@eecs.umich.edu } else if (!desc.p) { 11575857Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 11585679Sgblack@eecs.umich.edu } 11595428Sgblack@eecs.umich.edu break; 11605428Sgblack@eecs.umich.edu } 11615428Sgblack@eecs.umich.edu case SegIntCSCheck: 11625675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 11635675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 11645679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 11655675Sgblack@eecs.umich.edu } 11665675Sgblack@eecs.umich.edu } else { 11675675Sgblack@eecs.umich.edu panic("Interrupt CS checks not implemented " 11685675Sgblack@eecs.umich.edu "in legacy mode.\\n"); 11695675Sgblack@eecs.umich.edu } 11705428Sgblack@eecs.umich.edu break; 11715899Sgblack@eecs.umich.edu case SegTRCheck: 11725899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 11735899Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 11745899Sgblack@eecs.umich.edu } 11755899Sgblack@eecs.umich.edu break; 11765900Sgblack@eecs.umich.edu case SegTSSCheck: 11775900Sgblack@eecs.umich.edu if (!desc.p) { 11785900Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 11795900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 11805900Sgblack@eecs.umich.edu (desc.type == 1 && 11815900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 11825935Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 11835900Sgblack@eecs.umich.edu } 11845900Sgblack@eecs.umich.edu break; 11855936Sgblack@eecs.umich.edu case SegInGDTCheck: 11865936Sgblack@eecs.umich.edu if (selector.ti) { 11875936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 11885936Sgblack@eecs.umich.edu } 11895936Sgblack@eecs.umich.edu break; 11905936Sgblack@eecs.umich.edu case SegLDTCheck: 11915936Sgblack@eecs.umich.edu if (!desc.p) { 11925936Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 11935936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 11945936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 11955936Sgblack@eecs.umich.edu } 11965936Sgblack@eecs.umich.edu break; 11975428Sgblack@eecs.umich.edu default: 11985428Sgblack@eecs.umich.edu panic("Undefined segment check type.\\n"); 11995428Sgblack@eecs.umich.edu } 12005294Sgblack@eecs.umich.edu ''' 12015294Sgblack@eecs.umich.edu flag_code = ''' 12025294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 12035294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 12045424Sgblack@eecs.umich.edu if (!selector.si && !selector.ti) 12055294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 12065294Sgblack@eecs.umich.edu ''' 12075294Sgblack@eecs.umich.edu 12085294Sgblack@eecs.umich.edu class Wrdh(RegOp): 12095294Sgblack@eecs.umich.edu code = ''' 12105678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 12115294Sgblack@eecs.umich.edu 12125678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 12135678Sgblack@eecs.umich.edu switch(desc.type) { 12145678Sgblack@eecs.umich.edu case LDT64: 12155678Sgblack@eecs.umich.edu case AvailableTSS64: 12165678Sgblack@eecs.umich.edu case BusyTSS64: 12175678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 12185678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 12195678Sgblack@eecs.umich.edu break; 12205678Sgblack@eecs.umich.edu case CallGate64: 12215678Sgblack@eecs.umich.edu case IntGate64: 12225678Sgblack@eecs.umich.edu case TrapGate64: 12235678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 12245678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 12255678Sgblack@eecs.umich.edu break; 12265678Sgblack@eecs.umich.edu default: 12275678Sgblack@eecs.umich.edu panic("Wrdh used with wrong descriptor type!\\n"); 12285678Sgblack@eecs.umich.edu } 12295678Sgblack@eecs.umich.edu DestReg = target; 12305294Sgblack@eecs.umich.edu ''' 12315294Sgblack@eecs.umich.edu 12325409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 12335409Sgblack@eecs.umich.edu code = ''' 12345409Sgblack@eecs.umich.edu TscOp = psrc1; 12355409Sgblack@eecs.umich.edu ''' 12365409Sgblack@eecs.umich.edu 12375409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 12385409Sgblack@eecs.umich.edu code = ''' 12395409Sgblack@eecs.umich.edu DestReg = TscOp; 12405409Sgblack@eecs.umich.edu ''' 12415409Sgblack@eecs.umich.edu 12425429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 12435429Sgblack@eecs.umich.edu code = ''' 12445429Sgblack@eecs.umich.edu DestReg = M5Reg; 12455429Sgblack@eecs.umich.edu ''' 12465429Sgblack@eecs.umich.edu 12475294Sgblack@eecs.umich.edu class Wrdl(RegOp): 12485294Sgblack@eecs.umich.edu code = ''' 12495294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 12505433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 12515433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 12526222Sgblack@eecs.umich.edu if (!desc.p) 12536222Sgblack@eecs.umich.edu panic("Segment not present.\\n"); 12545433Sgblack@eecs.umich.edu SegAttr attr = 0; 12555433Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 12566222Sgblack@eecs.umich.edu attr.unusable = 0; 12575433Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 12586222Sgblack@eecs.umich.edu attr.longMode = desc.l; 12596222Sgblack@eecs.umich.edu attr.avl = desc.avl; 12606222Sgblack@eecs.umich.edu attr.granularity = desc.g; 12616222Sgblack@eecs.umich.edu attr.present = desc.p; 12626222Sgblack@eecs.umich.edu attr.system = desc.s; 12636222Sgblack@eecs.umich.edu attr.type = desc.type; 12645433Sgblack@eecs.umich.edu if (!desc.s) { 12655901Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 12665901Sgblack@eecs.umich.edu if (desc.type.e) { 12675901Sgblack@eecs.umich.edu panic("Gate descriptor encountered.\\n"); 12685901Sgblack@eecs.umich.edu } 12695901Sgblack@eecs.umich.edu attr.readable = 1; 12705901Sgblack@eecs.umich.edu attr.writable = 1; 12716222Sgblack@eecs.umich.edu attr.expandDown = 0; 12725433Sgblack@eecs.umich.edu } else { 12735433Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 12746222Sgblack@eecs.umich.edu attr.expandDown = 0; 12755433Sgblack@eecs.umich.edu attr.readable = desc.type.r; 12766222Sgblack@eecs.umich.edu attr.writable = 0; 12775433Sgblack@eecs.umich.edu } else { 12785433Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 12795433Sgblack@eecs.umich.edu attr.readable = 1; 12805433Sgblack@eecs.umich.edu attr.writable = desc.type.w; 12815433Sgblack@eecs.umich.edu } 12825433Sgblack@eecs.umich.edu } 12835901Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 12845901Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 12855901Sgblack@eecs.umich.edu if (desc.g) 12865901Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 12875901Sgblack@eecs.umich.edu SegBaseDest = base; 12885901Sgblack@eecs.umich.edu SegLimitDest = limit; 12895901Sgblack@eecs.umich.edu SegAttrDest = attr; 12905433Sgblack@eecs.umich.edu } else { 12915295Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 12925295Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 12935295Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 12945294Sgblack@eecs.umich.edu } 12955290Sgblack@eecs.umich.edu ''' 12964519Sgblack@eecs.umich.edu}}; 1297