regop.isa revision 6058
17202Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 212504Snikos.nikoleris@arm.com// All rights reserved. 37202Sgblack@eecs.umich.edu// 47202Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 57202Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 67202Sgblack@eecs.umich.edu// following conditions are met: 77202Sgblack@eecs.umich.edu// 87202Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 97202Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 107202Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 117202Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 127202Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 137202Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 147202Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 157202Sgblack@eecs.umich.edu// commercial advantage. 167202Sgblack@eecs.umich.edu// 177202Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 187202Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 197202Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 207202Sgblack@eecs.umich.edu// Office of Strategy and Technology 217202Sgblack@eecs.umich.edu// Hewlett-Packard Company 227202Sgblack@eecs.umich.edu// 1501 Page Mill Road 237202Sgblack@eecs.umich.edu// Palo Alto, California 94304 247202Sgblack@eecs.umich.edu// 257202Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 267202Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 277202Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 287202Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 297202Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 307202Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 317202Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 327202Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 337202Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 347202Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 357202Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 367202Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 377202Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 387202Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 397202Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 407202Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 417202Sgblack@eecs.umich.edu// 427202Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 437202Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 447202Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 457202Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 467202Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 477202Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 487202Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 497202Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 507202Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 517202Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 527202Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 537202Sgblack@eecs.umich.edu// 547202Sgblack@eecs.umich.edu// Authors: Gabe Black 557202Sgblack@eecs.umich.edu 567202Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 577202Sgblack@eecs.umich.edu// 587202Sgblack@eecs.umich.edu// RegOp Microop templates 597202Sgblack@eecs.umich.edu// 607202Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 617202Sgblack@eecs.umich.edu 627202Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 637202Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 647202Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 657202Sgblack@eecs.umich.edu { 667202Sgblack@eecs.umich.edu Fault fault = NoFault; 677202Sgblack@eecs.umich.edu 687202Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 697202Sgblack@eecs.umich.edu %(op_decl)s; 707202Sgblack@eecs.umich.edu %(op_rd)s; 717202Sgblack@eecs.umich.edu 727202Sgblack@eecs.umich.edu if(%(cond_check)s) 737202Sgblack@eecs.umich.edu { 747202Sgblack@eecs.umich.edu %(code)s; 757202Sgblack@eecs.umich.edu %(flag_code)s; 767202Sgblack@eecs.umich.edu } 777202Sgblack@eecs.umich.edu else 787202Sgblack@eecs.umich.edu { 797202Sgblack@eecs.umich.edu %(else_code)s; 807202Sgblack@eecs.umich.edu } 817202Sgblack@eecs.umich.edu 827202Sgblack@eecs.umich.edu //Write the resulting state to the execution context 837202Sgblack@eecs.umich.edu if(fault == NoFault) 847202Sgblack@eecs.umich.edu { 857202Sgblack@eecs.umich.edu %(op_wb)s; 867202Sgblack@eecs.umich.edu } 877202Sgblack@eecs.umich.edu return fault; 887202Sgblack@eecs.umich.edu } 897202Sgblack@eecs.umich.edu}}; 907202Sgblack@eecs.umich.edu 917202Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 927202Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 937202Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 947202Sgblack@eecs.umich.edu { 957202Sgblack@eecs.umich.edu Fault fault = NoFault; 967202Sgblack@eecs.umich.edu 9710037SARM gem5 Developers %(op_decl)s; 9810037SARM gem5 Developers %(op_rd)s; 9910037SARM gem5 Developers 10010420Sandreas.hansson@arm.com if(%(cond_check)s) 10110037SARM gem5 Developers { 10210037SARM gem5 Developers %(code)s; 10310037SARM gem5 Developers %(flag_code)s; 10410037SARM gem5 Developers } 10510037SARM gem5 Developers else 10610420Sandreas.hansson@arm.com { 10710037SARM gem5 Developers %(else_code)s; 10810037SARM gem5 Developers } 10910037SARM gem5 Developers 11010037SARM gem5 Developers //Write the resulting state to the execution context 11110037SARM gem5 Developers if(fault == NoFault) 11210037SARM gem5 Developers { 11310037SARM gem5 Developers %(op_wb)s; 11410037SARM gem5 Developers } 11510037SARM gem5 Developers return fault; 11610037SARM gem5 Developers } 11710037SARM gem5 Developers}}; 11810037SARM gem5 Developers 11910037SARM gem5 Developersdef template MicroRegOpDeclare {{ 12010420Sandreas.hansson@arm.com class %(class_name)s : public %(base_class)s 12110037SARM gem5 Developers { 12210037SARM gem5 Developers protected: 12310037SARM gem5 Developers void buildMe(); 12410420Sandreas.hansson@arm.com 12510037SARM gem5 Developers public: 12610037SARM gem5 Developers %(class_name)s(ExtMachInst _machInst, 12710037SARM gem5 Developers const char * instMnem, 12810037SARM gem5 Developers bool isMicro, bool isDelayed, bool isFirst, bool isLast, 12910037SARM gem5 Developers RegIndex _src1, RegIndex _src2, RegIndex _dest, 13010037SARM gem5 Developers uint8_t _dataSize, uint16_t _ext); 13110037SARM gem5 Developers 13210037SARM gem5 Developers %(class_name)s(ExtMachInst _machInst, 1337306Sgblack@eecs.umich.edu const char * instMnem, 1347306Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1357306Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1367330Sgblack@eecs.umich.edu 1377306Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1387306Sgblack@eecs.umich.edu }; 1397330Sgblack@eecs.umich.edu}}; 1407306Sgblack@eecs.umich.edu 1417306Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1427306Sgblack@eecs.umich.edu 1437306Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1447306Sgblack@eecs.umich.edu { 1457306Sgblack@eecs.umich.edu protected: 1467332Sgblack@eecs.umich.edu void buildMe(); 1477332Sgblack@eecs.umich.edu 1487332Sgblack@eecs.umich.edu public: 1497332Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1507332Sgblack@eecs.umich.edu const char * instMnem, 1517332Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1527332Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1537332Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1547332Sgblack@eecs.umich.edu 1557332Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1567332Sgblack@eecs.umich.edu const char * instMnem, 1577332Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1587332Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1597332Sgblack@eecs.umich.edu 1607261Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1617208Sgblack@eecs.umich.edu }; 1627208Sgblack@eecs.umich.edu}}; 1637208Sgblack@eecs.umich.edu 1647208Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1657208Sgblack@eecs.umich.edu 1667261Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1677261Sgblack@eecs.umich.edu { 1687208Sgblack@eecs.umich.edu %(constructor)s; 1697208Sgblack@eecs.umich.edu } 1707208Sgblack@eecs.umich.edu 1717208Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1727208Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1737208Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1747232Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1757225Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1767225Sgblack@eecs.umich.edu false, false, false, false, 1777225Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1787330Sgblack@eecs.umich.edu %(op_class)s) 1797225Sgblack@eecs.umich.edu { 1807225Sgblack@eecs.umich.edu buildMe(); 1817232Sgblack@eecs.umich.edu } 1827330Sgblack@eecs.umich.edu 1837225Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1847232Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1857225Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1867225Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1877225Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1887225Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1897225Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1907233Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1917233Sgblack@eecs.umich.edu %(op_class)s) 1927233Sgblack@eecs.umich.edu { 1937233Sgblack@eecs.umich.edu buildMe(); 1947233Sgblack@eecs.umich.edu } 1957233Sgblack@eecs.umich.edu}}; 1967330Sgblack@eecs.umich.edu 1977233Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1987233Sgblack@eecs.umich.edu 1997233Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 2007330Sgblack@eecs.umich.edu { 2017233Sgblack@eecs.umich.edu %(constructor)s; 2027233Sgblack@eecs.umich.edu } 2037233Sgblack@eecs.umich.edu 2047233Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2057233Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2067233Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2077233Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2087241Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2097241Sgblack@eecs.umich.edu false, false, false, false, 2107241Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2117241Sgblack@eecs.umich.edu %(op_class)s) 2127241Sgblack@eecs.umich.edu { 2137241Sgblack@eecs.umich.edu buildMe(); 2147241Sgblack@eecs.umich.edu } 2157241Sgblack@eecs.umich.edu 2167241Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2177241Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2187241Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2197241Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2207241Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2217241Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2227241Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2237241Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2247241Sgblack@eecs.umich.edu %(op_class)s) 2257241Sgblack@eecs.umich.edu { 2267238Sgblack@eecs.umich.edu buildMe(); 2277238Sgblack@eecs.umich.edu } 2287238Sgblack@eecs.umich.edu}}; 2297238Sgblack@eecs.umich.edu 2307238Sgblack@eecs.umich.eduoutput header {{ 2317238Sgblack@eecs.umich.edu void 2327238Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2337238Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 2347238Sgblack@eecs.umich.edu 2357238Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 2367238Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 2377238Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 2387238Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 2397238Sgblack@eecs.umich.edu }; 2407238Sgblack@eecs.umich.edu 2417238Sgblack@eecs.umich.edu enum LongModeDescriptorType { 2427331Sgblack@eecs.umich.edu LDT64 = 2, 2437331Sgblack@eecs.umich.edu AvailableTSS64 = 9, 2447331Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 2457331Sgblack@eecs.umich.edu CallGate64 = 0xc, 2467331Sgblack@eecs.umich.edu IntGate64 = 0xe, 2477331Sgblack@eecs.umich.edu TrapGate64 = 0xf 2487331Sgblack@eecs.umich.edu }; 2497331Sgblack@eecs.umich.edu}}; 2507331Sgblack@eecs.umich.edu 2517331Sgblack@eecs.umich.eduoutput decoder {{ 2527331Sgblack@eecs.umich.edu void 2537331Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2547331Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 2557331Sgblack@eecs.umich.edu { 2567331Sgblack@eecs.umich.edu //Check for divide by zero. 2577331Sgblack@eecs.umich.edu if (divisor == 0) 2587331Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 25910418Sandreas.hansson@arm.com //If the divisor is bigger than the dividend, don't do anything. 26010418Sandreas.hansson@arm.com if (divisor <= dividend) { 26110418Sandreas.hansson@arm.com //Shift the divisor so it's msb lines up with the dividend. 26210418Sandreas.hansson@arm.com int dividendMsb = findMsbSet(dividend); 26310418Sandreas.hansson@arm.com int divisorMsb = findMsbSet(divisor); 26410418Sandreas.hansson@arm.com int shift = dividendMsb - divisorMsb; 26510418Sandreas.hansson@arm.com divisor <<= shift; 26610418Sandreas.hansson@arm.com //Compute what we'll add to the quotient if the divisor isn't 26710418Sandreas.hansson@arm.com //now larger than the dividend. 26810418Sandreas.hansson@arm.com uint64_t quotientBit = 1; 26910418Sandreas.hansson@arm.com quotientBit <<= shift; 27010418Sandreas.hansson@arm.com //If we need to step back a bit (no pun intended) because the 27110418Sandreas.hansson@arm.com //divisor got too to large, do that here. This is the "or two" 27210418Sandreas.hansson@arm.com //part of one or two bit division. 27310418Sandreas.hansson@arm.com if (divisor > dividend) { 27410418Sandreas.hansson@arm.com quotientBit >>= 1; 27510418Sandreas.hansson@arm.com divisor >>= 1; 27610418Sandreas.hansson@arm.com } 27710418Sandreas.hansson@arm.com //Decrement the remainder and increment the quotient. 27810418Sandreas.hansson@arm.com quotient += quotientBit; 27910418Sandreas.hansson@arm.com remainder -= divisor; 28010418Sandreas.hansson@arm.com } 28110418Sandreas.hansson@arm.com } 28210418Sandreas.hansson@arm.com}}; 28310418Sandreas.hansson@arm.com 28410418Sandreas.hansson@arm.comlet {{ 28510418Sandreas.hansson@arm.com # Make these empty strings so that concatenating onto 28610418Sandreas.hansson@arm.com # them will always work. 28710418Sandreas.hansson@arm.com header_output = "" 28810418Sandreas.hansson@arm.com decoder_output = "" 28910418Sandreas.hansson@arm.com exec_output = "" 29010418Sandreas.hansson@arm.com 29110418Sandreas.hansson@arm.com immTemplates = ( 29210418Sandreas.hansson@arm.com MicroRegOpImmDeclare, 29310037SARM gem5 Developers MicroRegOpImmConstructor, 29410037SARM gem5 Developers MicroRegOpImmExecute) 29510037SARM gem5 Developers 29610037SARM gem5 Developers regTemplates = ( 29710037SARM gem5 Developers MicroRegOpDeclare, 29810037SARM gem5 Developers MicroRegOpConstructor, 29910037SARM gem5 Developers MicroRegOpExecute) 30010037SARM gem5 Developers 30110037SARM gem5 Developers class RegOpMeta(type): 30210037SARM gem5 Developers def buildCppClasses(self, name, Name, suffix, \ 30310037SARM gem5 Developers code, flag_code, cond_check, else_code): 30410037SARM gem5 Developers 30510037SARM gem5 Developers # Globals to stick the output in 30610037SARM gem5 Developers global header_output 30710037SARM gem5 Developers global decoder_output 30810037SARM gem5 Developers global exec_output 3097253Sgblack@eecs.umich.edu 3107253Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 3117253Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3127253Sgblack@eecs.umich.edu 3137253Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3147330Sgblack@eecs.umich.edu # of this code. 3157330Sgblack@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 3167253Sgblack@eecs.umich.edu match = matcher.search(allCode) 3177253Sgblack@eecs.umich.edu if match: 3187253Sgblack@eecs.umich.edu typeQual = "" 3197330Sgblack@eecs.umich.edu if match.group("typeQual"): 3207253Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 3217253Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3227253Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3237253Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 3247253Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 3257253Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 3267253Sgblack@eecs.umich.edu matcher.sub(src2_name, else_code)) 3277232Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 3287225Sgblack@eecs.umich.edu matcher.sub("imm8", code), 3297225Sgblack@eecs.umich.edu matcher.sub("imm8", flag_code), 3307225Sgblack@eecs.umich.edu matcher.sub("imm8", cond_check), 3317330Sgblack@eecs.umich.edu matcher.sub("imm8", else_code)) 3327225Sgblack@eecs.umich.edu return 3337225Sgblack@eecs.umich.edu 3347225Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 3357225Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 3367232Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 3377330Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3387232Sgblack@eecs.umich.edu code, "", "true", else_code) 3397225Sgblack@eecs.umich.edu suffix = "Flags" + suffix 3407232Sgblack@eecs.umich.edu 3417225Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 3427225Sgblack@eecs.umich.edu # compute it. 3437225Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 3447225Sgblack@eecs.umich.edu if matcher.search(allCode): 3457225Sgblack@eecs.umich.edu code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3467225Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 3477409Sgblack@eecs.umich.edu if matcher.search(allCode): 3487409Sgblack@eecs.umich.edu code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3497409Sgblack@eecs.umich.edu # Also make available versions which do sign extension 3507409Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3517409Sgblack@eecs.umich.edu if matcher.search(allCode): 3527409Sgblack@eecs.umich.edu code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3537409Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3547409Sgblack@eecs.umich.edu if matcher.search(allCode): 3557409Sgblack@eecs.umich.edu code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3567409Sgblack@eecs.umich.edu 3577409Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3587202Sgblack@eecs.umich.edu 359 # If imm8 shows up in the code, use the immediate templates, if 360 # not, hopefully the register ones will be correct. 361 templates = regTemplates 362 matcher = re.compile("(?<!\w)imm8(?!\w)") 363 if matcher.search(allCode): 364 base += "Imm" 365 templates = immTemplates 366 367 # Get everything ready for the substitution 368 iop = InstObjParams(name, Name + suffix, base, 369 {"code" : code, 370 "flag_code" : flag_code, 371 "cond_check" : cond_check, 372 "else_code" : else_code}) 373 374 # Generate the actual code (finally!) 375 header_output += templates[0].subst(iop) 376 decoder_output += templates[1].subst(iop) 377 exec_output += templates[2].subst(iop) 378 379 380 def __new__(mcls, Name, bases, dict): 381 abstract = False 382 name = Name.lower() 383 if "abstract" in dict: 384 abstract = dict['abstract'] 385 del dict['abstract'] 386 387 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 388 if not abstract: 389 cls.className = Name 390 cls.base_mnemonic = name 391 code = cls.code 392 flag_code = cls.flag_code 393 cond_check = cls.cond_check 394 else_code = cls.else_code 395 396 # Set up the C++ classes 397 mcls.buildCppClasses(cls, name, Name, "", 398 code, flag_code, cond_check, else_code) 399 400 # Hook into the microassembler dict 401 global microopClasses 402 microopClasses[name] = cls 403 404 allCode = "|".join((code, flag_code, cond_check, else_code)) 405 406 # If op2 is used anywhere, make register and immediate versions 407 # of this code. 408 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 409 if matcher.search(allCode): 410 microopClasses[name + 'i'] = cls 411 return cls 412 413 414 class RegOp(X86Microop): 415 __metaclass__ = RegOpMeta 416 # This class itself doesn't act as a microop 417 abstract = True 418 419 # Default template parameter values 420 flag_code = "" 421 cond_check = "true" 422 else_code = ";" 423 424 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 425 self.dest = dest 426 self.src1 = src1 427 self.op2 = op2 428 self.flags = flags 429 self.dataSize = dataSize 430 if flags is None: 431 self.ext = 0 432 else: 433 if not isinstance(flags, (list, tuple)): 434 raise Exception, "flags must be a list or tuple of flags" 435 self.ext = " | ".join(flags) 436 self.className += "Flags" 437 438 def getAllocator(self, *microFlags): 439 className = self.className 440 if self.mnemonic == self.base_mnemonic + 'i': 441 className += "Imm" 442 allocator = '''new %(class_name)s(machInst, macrocodeBlock 443 %(flags)s, %(src1)s, %(op2)s, %(dest)s, 444 %(dataSize)s, %(ext)s)''' % { 445 "class_name" : className, 446 "flags" : self.microFlagsText(microFlags), 447 "src1" : self.src1, "op2" : self.op2, 448 "dest" : self.dest, 449 "dataSize" : self.dataSize, 450 "ext" : self.ext} 451 return allocator 452 453 class LogicRegOp(RegOp): 454 abstract = True 455 flag_code = ''' 456 //Don't have genFlags handle the OF or CF bits 457 uint64_t mask = CFBit | ECFBit | OFBit; 458 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 459 //If a logic microop wants to set these, it wants to set them to 0. 460 ccFlagBits &= ~(CFBit & ext); 461 ccFlagBits &= ~(ECFBit & ext); 462 ccFlagBits &= ~(OFBit & ext); 463 ''' 464 465 class FlagRegOp(RegOp): 466 abstract = True 467 flag_code = \ 468 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 469 470 class SubRegOp(RegOp): 471 abstract = True 472 flag_code = \ 473 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 474 475 class CondRegOp(RegOp): 476 abstract = True 477 cond_check = "checkCondition(ccFlagBits, ext)" 478 479 class RdRegOp(RegOp): 480 abstract = True 481 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 482 if not src1: 483 src1 = dest 484 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 485 486 class WrRegOp(RegOp): 487 abstract = True 488 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 489 super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 490 491 class Add(FlagRegOp): 492 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 493 494 class Or(LogicRegOp): 495 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 496 497 class Adc(FlagRegOp): 498 code = ''' 499 CCFlagBits flags = ccFlagBits; 500 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 501 ''' 502 503 class Sbb(SubRegOp): 504 code = ''' 505 CCFlagBits flags = ccFlagBits; 506 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 507 ''' 508 509 class And(LogicRegOp): 510 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 511 512 class Sub(SubRegOp): 513 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 514 515 class Xor(LogicRegOp): 516 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 517 518 # Neither of these is quite correct because it assumes that right shifting 519 # a signed or unsigned value does sign or zero extension respectively. 520 # The C standard says that what happens on a right shift with a 1 in the 521 # MSB position is undefined. On x86 and under likely most compilers the 522 # "right thing" happens, but this isn't a guarantee. 523 class Mul1s(WrRegOp): 524 code = ''' 525 ProdLow = psrc1 * op2; 526 int halfSize = (dataSize * 8) / 2; 527 int64_t spsrc1_h = spsrc1 >> halfSize; 528 int64_t spsrc1_l = spsrc1 & mask(halfSize); 529 int64_t spsrc2_h = sop2 >> halfSize; 530 int64_t spsrc2_l = sop2 & mask(halfSize); 531 ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l + 532 ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) + 533 spsrc1_h * spsrc2_h; 534 ''' 535 536 class Mul1u(WrRegOp): 537 code = ''' 538 ProdLow = psrc1 * op2; 539 int halfSize = (dataSize * 8) / 2; 540 uint64_t psrc1_h = psrc1 >> halfSize; 541 uint64_t psrc1_l = psrc1 & mask(halfSize); 542 uint64_t psrc2_h = op2 >> halfSize; 543 uint64_t psrc2_l = op2 & mask(halfSize); 544 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 545 ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) + 546 psrc1_h * psrc2_h; 547 ''' 548 549 class Mulel(RdRegOp): 550 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 551 552 class Muleh(RdRegOp): 553 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 554 if not src1: 555 src1 = dest 556 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize) 557 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 558 flag_code = ''' 559 if (ProdHi) 560 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 561 else 562 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 563 ''' 564 565 # One or two bit divide 566 class Div1(WrRegOp): 567 code = ''' 568 //These are temporaries so that modifying them later won't make 569 //the ISA parser think they're also sources. 570 uint64_t quotient = 0; 571 uint64_t remainder = psrc1; 572 //Similarly, this is a temporary so changing it doesn't make it 573 //a source. 574 uint64_t divisor = op2; 575 //This is a temporary just for consistency and clarity. 576 uint64_t dividend = remainder; 577 //Do the division. 578 divide(dividend, divisor, quotient, remainder); 579 //Record the final results. 580 Remainder = remainder; 581 Quotient = quotient; 582 Divisor = divisor; 583 ''' 584 585 # Step divide 586 class Div2(RegOp): 587 code = ''' 588 uint64_t dividend = Remainder; 589 uint64_t divisor = Divisor; 590 uint64_t quotient = Quotient; 591 uint64_t remainder = dividend; 592 int remaining = op2; 593 //If we overshot, do nothing. This lets us unrool division loops a 594 //little. 595 if (remaining) { 596 //Shift in bits from the low order portion of the dividend 597 while(dividend < divisor && remaining) { 598 dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 599 quotient <<= 1; 600 remaining--; 601 } 602 remainder = dividend; 603 //Do the division. 604 divide(dividend, divisor, quotient, remainder); 605 } 606 //Keep track of how many bits there are still to pull in. 607 DestReg = merge(DestReg, remaining, dataSize); 608 //Record the final results 609 Remainder = remainder; 610 Quotient = quotient; 611 ''' 612 flag_code = ''' 613 if (DestReg == 0) 614 ccFlagBits = ccFlagBits | (ext & EZFBit); 615 else 616 ccFlagBits = ccFlagBits & ~(ext & EZFBit); 617 ''' 618 619 class Divq(RdRegOp): 620 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 621 622 class Divr(RdRegOp): 623 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 624 625 class Mov(CondRegOp): 626 code = 'DestReg = merge(SrcReg1, op2, dataSize)' 627 else_code = 'DestReg=DestReg;' 628 629 # Shift instructions 630 631 class Sll(RegOp): 632 code = ''' 633 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 634 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 635 ''' 636 flag_code = ''' 637 // If the shift amount is zero, no flags should be modified. 638 if (shiftAmt) { 639 //Zero out any flags we might modify. This way we only have to 640 //worry about setting them. 641 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 642 int CFBits = 0; 643 //Figure out if we -would- set the CF bits if requested. 644 if (bits(SrcReg1, dataSize * 8 - shiftAmt)) 645 CFBits = 1; 646 //If some combination of the CF bits need to be set, set them. 647 if ((ext & (CFBit | ECFBit)) && CFBits) 648 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 649 //Figure out what the OF bit should be. 650 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 651 ccFlagBits = ccFlagBits | OFBit; 652 //Use the regular mechanisms to calculate the other flags. 653 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 654 DestReg, psrc1, op2); 655 } 656 ''' 657 658 class Srl(RegOp): 659 code = ''' 660 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 661 // Because what happens to the bits shift -in- on a right shift 662 // is not defined in the C/C++ standard, we have to mask them out 663 // to be sure they're zero. 664 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 665 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 666 ''' 667 flag_code = ''' 668 // If the shift amount is zero, no flags should be modified. 669 if (shiftAmt) { 670 //Zero out any flags we might modify. This way we only have to 671 //worry about setting them. 672 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 673 //If some combination of the CF bits need to be set, set them. 674 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 675 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 676 //Figure out what the OF bit should be. 677 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 678 ccFlagBits = ccFlagBits | OFBit; 679 //Use the regular mechanisms to calculate the other flags. 680 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 681 DestReg, psrc1, op2); 682 } 683 ''' 684 685 class Sra(RegOp): 686 code = ''' 687 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 688 // Because what happens to the bits shift -in- on a right shift 689 // is not defined in the C/C++ standard, we have to sign extend 690 // them manually to be sure. 691 uint64_t arithMask = 692 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 693 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 694 ''' 695 flag_code = ''' 696 // If the shift amount is zero, no flags should be modified. 697 if (shiftAmt) { 698 //Zero out any flags we might modify. This way we only have to 699 //worry about setting them. 700 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 701 //If some combination of the CF bits need to be set, set them. 702 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 703 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 704 //Use the regular mechanisms to calculate the other flags. 705 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 706 DestReg, psrc1, op2); 707 } 708 ''' 709 710 class Ror(RegOp): 711 code = ''' 712 uint8_t shiftAmt = 713 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 714 if(shiftAmt) 715 { 716 uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 717 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 718 DestReg = merge(DestReg, top | bottom, dataSize); 719 } 720 else 721 DestReg = DestReg; 722 ''' 723 flag_code = ''' 724 // If the shift amount is zero, no flags should be modified. 725 if (shiftAmt) { 726 //Zero out any flags we might modify. This way we only have to 727 //worry about setting them. 728 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 729 //Find the most and second most significant bits of the result. 730 int msb = bits(DestReg, dataSize * 8 - 1); 731 int smsb = bits(DestReg, dataSize * 8 - 2); 732 //If some combination of the CF bits need to be set, set them. 733 if ((ext & (CFBit | ECFBit)) && msb) 734 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 735 //Figure out what the OF bit should be. 736 if ((ext & OFBit) && (msb ^ smsb)) 737 ccFlagBits = ccFlagBits | OFBit; 738 //Use the regular mechanisms to calculate the other flags. 739 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 740 DestReg, psrc1, op2); 741 } 742 ''' 743 744 class Rcr(RegOp): 745 code = ''' 746 uint8_t shiftAmt = 747 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 748 if(shiftAmt) 749 { 750 CCFlagBits flags = ccFlagBits; 751 uint64_t top = flags.cf << (dataSize * 8 - shiftAmt); 752 if(shiftAmt > 1) 753 top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 754 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 755 DestReg = merge(DestReg, top | bottom, dataSize); 756 } 757 else 758 DestReg = DestReg; 759 ''' 760 flag_code = ''' 761 // If the shift amount is zero, no flags should be modified. 762 if (shiftAmt) { 763 //Zero out any flags we might modify. This way we only have to 764 //worry about setting them. 765 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 766 //Figure out what the OF bit should be. 767 if ((ext & OFBit) && ((ccFlagBits & CFBit) ^ 768 bits(SrcReg1, dataSize * 8 - 1))) 769 ccFlagBits = ccFlagBits | OFBit; 770 //If some combination of the CF bits need to be set, set them. 771 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 772 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 773 //Use the regular mechanisms to calculate the other flags. 774 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 775 DestReg, psrc1, op2); 776 } 777 ''' 778 779 class Rol(RegOp): 780 code = ''' 781 uint8_t shiftAmt = 782 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 783 if(shiftAmt) 784 { 785 uint64_t top = psrc1 << shiftAmt; 786 uint64_t bottom = 787 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 788 DestReg = merge(DestReg, top | bottom, dataSize); 789 } 790 else 791 DestReg = DestReg; 792 ''' 793 flag_code = ''' 794 // If the shift amount is zero, no flags should be modified. 795 if (shiftAmt) { 796 //Zero out any flags we might modify. This way we only have to 797 //worry about setting them. 798 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 799 //The CF bits, if set, would be set to the lsb of the result. 800 int lsb = DestReg & 0x1; 801 int msb = bits(DestReg, dataSize * 8 - 1); 802 //If some combination of the CF bits need to be set, set them. 803 if ((ext & (CFBit | ECFBit)) && lsb) 804 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 805 //Figure out what the OF bit should be. 806 if ((ext & OFBit) && (msb ^ lsb)) 807 ccFlagBits = ccFlagBits | OFBit; 808 //Use the regular mechanisms to calculate the other flags. 809 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 810 DestReg, psrc1, op2); 811 } 812 ''' 813 814 class Rcl(RegOp): 815 code = ''' 816 uint8_t shiftAmt = 817 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 818 if(shiftAmt) 819 { 820 CCFlagBits flags = ccFlagBits; 821 uint64_t top = psrc1 << shiftAmt; 822 uint64_t bottom = flags.cf << (shiftAmt - 1); 823 if(shiftAmt > 1) 824 bottom |= 825 bits(psrc1, dataSize * 8 - 1, 826 dataSize * 8 - shiftAmt + 1); 827 DestReg = merge(DestReg, top | bottom, dataSize); 828 } 829 else 830 DestReg = DestReg; 831 ''' 832 flag_code = ''' 833 // If the shift amount is zero, no flags should be modified. 834 if (shiftAmt) { 835 //Zero out any flags we might modify. This way we only have to 836 //worry about setting them. 837 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 838 int msb = bits(DestReg, dataSize * 8 - 1); 839 int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt); 840 //If some combination of the CF bits need to be set, set them. 841 if ((ext & (CFBit | ECFBit)) && CFBits) 842 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 843 //Figure out what the OF bit should be. 844 if ((ext & OFBit) && (msb ^ CFBits)) 845 ccFlagBits = ccFlagBits | OFBit; 846 //Use the regular mechanisms to calculate the other flags. 847 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 848 DestReg, psrc1, op2); 849 } 850 ''' 851 852 class Wrip(WrRegOp, CondRegOp): 853 code = 'RIP = psrc1 + sop2 + CSBase' 854 else_code="RIP = RIP;" 855 856 class Wruflags(WrRegOp): 857 code = 'ccFlagBits = psrc1 ^ op2' 858 859 class Wrflags(WrRegOp): 860 code = ''' 861 MiscReg newFlags = psrc1 ^ op2; 862 MiscReg userFlagMask = 0xDD5; 863 // Get only the user flags 864 ccFlagBits = newFlags & userFlagMask; 865 // Get everything else 866 nccFlagBits = newFlags & ~userFlagMask; 867 ''' 868 869 class Rdip(RdRegOp): 870 code = 'DestReg = RIP - CSBase' 871 872 class Ruflags(RdRegOp): 873 code = 'DestReg = ccFlagBits' 874 875 class Rflags(RdRegOp): 876 code = 'DestReg = ccFlagBits | nccFlagBits' 877 878 class Ruflag(RegOp): 879 code = ''' 880 int flag = bits(ccFlagBits, imm8); 881 DestReg = merge(DestReg, flag, dataSize); 882 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 883 (ccFlagBits & ~EZFBit); 884 ''' 885 def __init__(self, dest, imm, flags=None, \ 886 dataSize="env.dataSize"): 887 super(Ruflag, self).__init__(dest, \ 888 "NUM_INTREGS", imm, flags, dataSize) 889 890 class Rflag(RegOp): 891 code = ''' 892 MiscReg flagMask = 0x3F7FDD5; 893 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 894 int flag = bits(flags, imm8); 895 DestReg = merge(DestReg, flag, dataSize); 896 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 897 (ccFlagBits & ~EZFBit); 898 ''' 899 def __init__(self, dest, imm, flags=None, \ 900 dataSize="env.dataSize"): 901 super(Rflag, self).__init__(dest, \ 902 "NUM_INTREGS", imm, flags, dataSize) 903 904 class Sext(RegOp): 905 code = ''' 906 IntReg val = psrc1; 907 // Mask the bit position so that it wraps. 908 int bitPos = op2 & (dataSize * 8 - 1); 909 int sign_bit = bits(val, bitPos, bitPos); 910 uint64_t maskVal = mask(bitPos+1); 911 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 912 DestReg = merge(DestReg, val, dataSize); 913 ''' 914 flag_code = ''' 915 if (!sign_bit) 916 ccFlagBits = ccFlagBits & 917 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 918 else 919 ccFlagBits = ccFlagBits | 920 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 921 ''' 922 923 class Zext(RegOp): 924 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 925 926 class Rddr(RegOp): 927 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 928 super(Rddr, self).__init__(dest, \ 929 src1, "NUM_INTREGS", flags, dataSize) 930 code = ''' 931 CR4 cr4 = CR4Op; 932 DR7 dr7 = DR7Op; 933 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 934 fault = new InvalidOpcode(); 935 } else if (dr7.gd) { 936 fault = new DebugException(); 937 } else { 938 DestReg = merge(DestReg, DebugSrc1, dataSize); 939 } 940 ''' 941 942 class Wrdr(RegOp): 943 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 944 super(Wrdr, self).__init__(dest, \ 945 src1, "NUM_INTREGS", flags, dataSize) 946 code = ''' 947 CR4 cr4 = CR4Op; 948 DR7 dr7 = DR7Op; 949 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 950 fault = new InvalidOpcode(); 951 } else if ((dest == 6 || dest == 7) && 952 bits(psrc1, 63, 32) && 953 machInst.mode.mode == LongMode) { 954 fault = new GeneralProtection(0); 955 } else if (dr7.gd) { 956 fault = new DebugException(); 957 } else { 958 DebugDest = psrc1; 959 } 960 ''' 961 962 class Rdcr(RegOp): 963 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 964 super(Rdcr, self).__init__(dest, \ 965 src1, "NUM_INTREGS", flags, dataSize) 966 code = ''' 967 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 968 fault = new InvalidOpcode(); 969 } else { 970 DestReg = merge(DestReg, ControlSrc1, dataSize); 971 } 972 ''' 973 974 class Wrcr(RegOp): 975 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 976 super(Wrcr, self).__init__(dest, \ 977 src1, "NUM_INTREGS", flags, dataSize) 978 code = ''' 979 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 980 fault = new InvalidOpcode(); 981 } else { 982 // There are *s in the line below so it doesn't confuse the 983 // parser. They may be unnecessary. 984 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 985 MiscReg newVal = psrc1; 986 987 // Check for any modifications that would cause a fault. 988 switch(dest) { 989 case 0: 990 { 991 Efer efer = EferOp; 992 CR0 cr0 = newVal; 993 CR4 oldCr4 = CR4Op; 994 if (bits(newVal, 63, 32) || 995 (!cr0.pe && cr0.pg) || 996 (!cr0.cd && cr0.nw) || 997 (cr0.pg && efer.lme && !oldCr4.pae)) 998 fault = new GeneralProtection(0); 999 } 1000 break; 1001 case 2: 1002 break; 1003 case 3: 1004 break; 1005 case 4: 1006 { 1007 CR4 cr4 = newVal; 1008 // PAE can't be disabled in long mode. 1009 if (bits(newVal, 63, 11) || 1010 (machInst.mode.mode == LongMode && !cr4.pae)) 1011 fault = new GeneralProtection(0); 1012 } 1013 break; 1014 case 8: 1015 { 1016 if (bits(newVal, 63, 4)) 1017 fault = new GeneralProtection(0); 1018 } 1019 default: 1020 panic("Unrecognized control register %d.\\n", dest); 1021 } 1022 ControlDest = newVal; 1023 } 1024 ''' 1025 1026 # Microops for manipulating segmentation registers 1027 class SegOp(CondRegOp): 1028 abstract = True 1029 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1030 super(SegOp, self).__init__(dest, \ 1031 src1, "NUM_INTREGS", flags, dataSize) 1032 1033 class Wrbase(SegOp): 1034 code = ''' 1035 SegBaseDest = psrc1; 1036 ''' 1037 1038 class Wrlimit(SegOp): 1039 code = ''' 1040 SegLimitDest = psrc1; 1041 ''' 1042 1043 class Wrsel(SegOp): 1044 code = ''' 1045 SegSelDest = psrc1; 1046 ''' 1047 1048 class WrAttr(SegOp): 1049 code = ''' 1050 SegAttrDest = psrc1; 1051 ''' 1052 1053 class Rdbase(SegOp): 1054 code = ''' 1055 DestReg = merge(DestReg, SegBaseSrc1, dataSize); 1056 ''' 1057 1058 class Rdlimit(SegOp): 1059 code = ''' 1060 DestReg = merge(DestReg, SegLimitSrc1, dataSize); 1061 ''' 1062 1063 class RdAttr(SegOp): 1064 code = ''' 1065 DestReg = merge(DestReg, SegAttrSrc1, dataSize); 1066 ''' 1067 1068 class Rdsel(SegOp): 1069 code = ''' 1070 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1071 ''' 1072 1073 class Rdval(RegOp): 1074 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1075 super(Rdval, self).__init__(dest, \ 1076 src1, "NUM_INTREGS", flags, dataSize) 1077 code = ''' 1078 DestReg = MiscRegSrc1; 1079 ''' 1080 1081 class Wrval(RegOp): 1082 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1083 super(Wrval, self).__init__(dest, \ 1084 src1, "NUM_INTREGS", flags, dataSize) 1085 code = ''' 1086 MiscRegDest = SrcReg1; 1087 ''' 1088 1089 class Chks(RegOp): 1090 def __init__(self, dest, src1, src2=0, 1091 flags=None, dataSize="env.dataSize"): 1092 super(Chks, self).__init__(dest, 1093 src1, src2, flags, dataSize) 1094 code = ''' 1095 // The selector is in source 1 and can be at most 16 bits. 1096 SegSelector selector = DestReg; 1097 SegDescriptor desc = SrcReg1; 1098 HandyM5Reg m5reg = M5Reg; 1099 1100 switch (imm8) 1101 { 1102 case SegNoCheck: 1103 break; 1104 case SegCSCheck: 1105 panic("CS checks for far calls/jumps not implemented.\\n"); 1106 break; 1107 case SegCallGateCheck: 1108 panic("CS checks for far calls/jumps through call gates" 1109 "not implemented.\\n"); 1110 break; 1111 case SegSoftIntGateCheck: 1112 // Check permissions. 1113 if (desc.dpl < m5reg.cpl) { 1114 fault = new GeneralProtection(selector); 1115 break; 1116 } 1117 // Fall through on purpose 1118 case SegIntGateCheck: 1119 // Make sure the gate's the right type. 1120 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 1121 ((desc.type & 0x6) != 0x6)) { 1122 fault = new GeneralProtection(0); 1123 } 1124 break; 1125 case SegSSCheck: 1126 if (selector.si || selector.ti) { 1127 if (!desc.p) { 1128 fault = new StackFault(selector); 1129 } 1130 } else { 1131 if ((m5reg.submode != SixtyFourBitMode || 1132 m5reg.cpl == 3) || 1133 !(desc.s == 1 && 1134 desc.type.codeOrData == 0 && desc.type.w) || 1135 (desc.dpl != m5reg.cpl) || 1136 (selector.rpl != m5reg.cpl)) { 1137 fault = new GeneralProtection(selector); 1138 } 1139 } 1140 break; 1141 case SegIretCheck: 1142 { 1143 if ((!selector.si && !selector.ti) || 1144 (selector.rpl < m5reg.cpl) || 1145 !(desc.s == 1 && desc.type.codeOrData == 1) || 1146 (!desc.type.c && desc.dpl != selector.rpl) || 1147 (desc.type.c && desc.dpl > selector.rpl)) { 1148 fault = new GeneralProtection(selector); 1149 } else if (!desc.p) { 1150 fault = new SegmentNotPresent(selector); 1151 } 1152 break; 1153 } 1154 case SegIntCSCheck: 1155 if (m5reg.mode == LongMode) { 1156 if (desc.l != 1 || desc.d != 0) { 1157 fault = new GeneralProtection(selector); 1158 } 1159 } else { 1160 panic("Interrupt CS checks not implemented " 1161 "in legacy mode.\\n"); 1162 } 1163 break; 1164 case SegTRCheck: 1165 if (!selector.si || selector.ti) { 1166 fault = new GeneralProtection(selector); 1167 } 1168 break; 1169 case SegTSSCheck: 1170 if (!desc.p) { 1171 fault = new SegmentNotPresent(selector); 1172 } else if (!(desc.type == 0x9 || 1173 (desc.type == 1 && 1174 m5reg.mode != LongMode))) { 1175 fault = new GeneralProtection(selector); 1176 } 1177 break; 1178 case SegInGDTCheck: 1179 if (selector.ti) { 1180 fault = new GeneralProtection(selector); 1181 } 1182 break; 1183 case SegLDTCheck: 1184 if (!desc.p) { 1185 fault = new SegmentNotPresent(selector); 1186 } else if (desc.type != 0x2) { 1187 fault = new GeneralProtection(selector); 1188 } 1189 break; 1190 default: 1191 panic("Undefined segment check type.\\n"); 1192 } 1193 ''' 1194 flag_code = ''' 1195 // Check for a NULL selector and set ZF,EZF appropriately. 1196 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 1197 if (!selector.si && !selector.ti) 1198 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 1199 ''' 1200 1201 class Wrdh(RegOp): 1202 code = ''' 1203 SegDescriptor desc = SrcReg1; 1204 1205 uint64_t target = bits(SrcReg2, 31, 0) << 32; 1206 switch(desc.type) { 1207 case LDT64: 1208 case AvailableTSS64: 1209 case BusyTSS64: 1210 replaceBits(target, 23, 0, desc.baseLow); 1211 replaceBits(target, 31, 24, desc.baseHigh); 1212 break; 1213 case CallGate64: 1214 case IntGate64: 1215 case TrapGate64: 1216 replaceBits(target, 15, 0, bits(desc, 15, 0)); 1217 replaceBits(target, 31, 16, bits(desc, 63, 48)); 1218 break; 1219 default: 1220 panic("Wrdh used with wrong descriptor type!\\n"); 1221 } 1222 DestReg = target; 1223 ''' 1224 1225 class Wrtsc(WrRegOp): 1226 code = ''' 1227 TscOp = psrc1; 1228 ''' 1229 1230 class Rdtsc(RdRegOp): 1231 code = ''' 1232 DestReg = TscOp; 1233 ''' 1234 1235 class Rdm5reg(RdRegOp): 1236 code = ''' 1237 DestReg = M5Reg; 1238 ''' 1239 1240 class Wrdl(RegOp): 1241 code = ''' 1242 SegDescriptor desc = SrcReg1; 1243 SegSelector selector = SrcReg2; 1244 if (selector.si || selector.ti) { 1245 SegAttr attr = 0; 1246 attr.dpl = desc.dpl; 1247 attr.defaultSize = desc.d; 1248 if (!desc.s) { 1249 // The expand down bit happens to be set for gates. 1250 if (desc.type.e) { 1251 panic("Gate descriptor encountered.\\n"); 1252 } 1253 attr.readable = 1; 1254 attr.writable = 1; 1255 } else { 1256 if (!desc.p) 1257 panic("Segment not present.\\n"); 1258 if (desc.type.codeOrData) { 1259 attr.readable = desc.type.r; 1260 attr.longMode = desc.l; 1261 } else { 1262 attr.expandDown = desc.type.e; 1263 attr.readable = 1; 1264 attr.writable = desc.type.w; 1265 } 1266 } 1267 Addr base = desc.baseLow | (desc.baseHigh << 24); 1268 Addr limit = desc.limitLow | (desc.limitHigh << 16); 1269 if (desc.g) 1270 limit = (limit << 12) | mask(12); 1271 SegBaseDest = base; 1272 SegLimitDest = limit; 1273 SegAttrDest = attr; 1274 } else { 1275 SegBaseDest = SegBaseDest; 1276 SegLimitDest = SegLimitDest; 1277 SegAttrDest = SegAttrDest; 1278 } 1279 ''' 1280}}; 1281