regop.isa revision 5788
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 44519Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 54519Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 64519Sgblack@eecs.umich.edu// following conditions are met: 74519Sgblack@eecs.umich.edu// 84519Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 94519Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 104519Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 114519Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 134519Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 144519Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 154519Sgblack@eecs.umich.edu// commercial advantage. 164519Sgblack@eecs.umich.edu// 174519Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 184519Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 194519Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 204519Sgblack@eecs.umich.edu// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 224519Sgblack@eecs.umich.edu// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 274519Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 284519Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 294519Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 304519Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 314519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 324519Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 334519Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 344519Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 354519Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534519Sgblack@eecs.umich.edu// 544519Sgblack@eecs.umich.edu// Authors: Gabe Black 554519Sgblack@eecs.umich.edu 564519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574519Sgblack@eecs.umich.edu// 584519Sgblack@eecs.umich.edu// RegOp Microop templates 594519Sgblack@eecs.umich.edu// 604519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614519Sgblack@eecs.umich.edu 624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 694519Sgblack@eecs.umich.edu %(op_decl)s; 704519Sgblack@eecs.umich.edu %(op_rd)s; 714688Sgblack@eecs.umich.edu 724688Sgblack@eecs.umich.edu if(%(cond_check)s) 734688Sgblack@eecs.umich.edu { 744688Sgblack@eecs.umich.edu %(code)s; 754688Sgblack@eecs.umich.edu %(flag_code)s; 764688Sgblack@eecs.umich.edu } 774708Sgblack@eecs.umich.edu else 784708Sgblack@eecs.umich.edu { 794708Sgblack@eecs.umich.edu %(else_code)s; 804708Sgblack@eecs.umich.edu } 814519Sgblack@eecs.umich.edu 824519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 834519Sgblack@eecs.umich.edu if(fault == NoFault) 844519Sgblack@eecs.umich.edu { 854519Sgblack@eecs.umich.edu %(op_wb)s; 864519Sgblack@eecs.umich.edu } 874519Sgblack@eecs.umich.edu return fault; 884519Sgblack@eecs.umich.edu } 894519Sgblack@eecs.umich.edu}}; 904519Sgblack@eecs.umich.edu 914519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 924951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 934519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 944519Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu Fault fault = NoFault; 964519Sgblack@eecs.umich.edu 974519Sgblack@eecs.umich.edu %(op_decl)s; 984519Sgblack@eecs.umich.edu %(op_rd)s; 994688Sgblack@eecs.umich.edu 1004688Sgblack@eecs.umich.edu if(%(cond_check)s) 1014688Sgblack@eecs.umich.edu { 1024688Sgblack@eecs.umich.edu %(code)s; 1034688Sgblack@eecs.umich.edu %(flag_code)s; 1044688Sgblack@eecs.umich.edu } 1054708Sgblack@eecs.umich.edu else 1064708Sgblack@eecs.umich.edu { 1074708Sgblack@eecs.umich.edu %(else_code)s; 1084708Sgblack@eecs.umich.edu } 1094519Sgblack@eecs.umich.edu 1104519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1114519Sgblack@eecs.umich.edu if(fault == NoFault) 1124519Sgblack@eecs.umich.edu { 1134519Sgblack@eecs.umich.edu %(op_wb)s; 1144519Sgblack@eecs.umich.edu } 1154519Sgblack@eecs.umich.edu return fault; 1164519Sgblack@eecs.umich.edu } 1174519Sgblack@eecs.umich.edu}}; 1184519Sgblack@eecs.umich.edu 1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1204519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu protected: 1234519Sgblack@eecs.umich.edu void buildMe(); 1244519Sgblack@eecs.umich.edu 1254519Sgblack@eecs.umich.edu public: 1264519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1274519Sgblack@eecs.umich.edu const char * instMnem, 1284519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1294519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1304712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1334519Sgblack@eecs.umich.edu const char * instMnem, 1344519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1354712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1364519Sgblack@eecs.umich.edu 1374519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1384519Sgblack@eecs.umich.edu }; 1394519Sgblack@eecs.umich.edu}}; 1404519Sgblack@eecs.umich.edu 1414519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1424519Sgblack@eecs.umich.edu 1434951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1444519Sgblack@eecs.umich.edu { 1454519Sgblack@eecs.umich.edu protected: 1464519Sgblack@eecs.umich.edu void buildMe(); 1474519Sgblack@eecs.umich.edu 1484519Sgblack@eecs.umich.edu public: 1494951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1504519Sgblack@eecs.umich.edu const char * instMnem, 1514519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1524951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1534712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1544519Sgblack@eecs.umich.edu 1554951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1564519Sgblack@eecs.umich.edu const char * instMnem, 1574951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1584712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1594519Sgblack@eecs.umich.edu 1604519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1614519Sgblack@eecs.umich.edu }; 1624519Sgblack@eecs.umich.edu}}; 1634519Sgblack@eecs.umich.edu 1644519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1654519Sgblack@eecs.umich.edu 1664519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1674519Sgblack@eecs.umich.edu { 1684519Sgblack@eecs.umich.edu %(constructor)s; 1694519Sgblack@eecs.umich.edu } 1704519Sgblack@eecs.umich.edu 1714519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1724519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1734519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1744712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1754519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1764581Sgblack@eecs.umich.edu false, false, false, false, 1774688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1784581Sgblack@eecs.umich.edu %(op_class)s) 1794519Sgblack@eecs.umich.edu { 1804519Sgblack@eecs.umich.edu buildMe(); 1814519Sgblack@eecs.umich.edu } 1824519Sgblack@eecs.umich.edu 1834519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1844519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1854519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1864519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1874712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1884519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1894581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1904688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1914581Sgblack@eecs.umich.edu %(op_class)s) 1924519Sgblack@eecs.umich.edu { 1934519Sgblack@eecs.umich.edu buildMe(); 1944519Sgblack@eecs.umich.edu } 1954519Sgblack@eecs.umich.edu}}; 1964519Sgblack@eecs.umich.edu 1974519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1984519Sgblack@eecs.umich.edu 1994951Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 2004519Sgblack@eecs.umich.edu { 2014519Sgblack@eecs.umich.edu %(constructor)s; 2024519Sgblack@eecs.umich.edu } 2034519Sgblack@eecs.umich.edu 2044951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2054519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2064951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2074712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2084519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2094581Sgblack@eecs.umich.edu false, false, false, false, 2104688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2114581Sgblack@eecs.umich.edu %(op_class)s) 2124519Sgblack@eecs.umich.edu { 2134519Sgblack@eecs.umich.edu buildMe(); 2144519Sgblack@eecs.umich.edu } 2154519Sgblack@eecs.umich.edu 2164951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2174519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2184519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2194951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2204712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2214519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2224581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2234688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2244581Sgblack@eecs.umich.edu %(op_class)s) 2254519Sgblack@eecs.umich.edu { 2264519Sgblack@eecs.umich.edu buildMe(); 2274519Sgblack@eecs.umich.edu } 2284519Sgblack@eecs.umich.edu}}; 2294519Sgblack@eecs.umich.edu 2305075Sgblack@eecs.umich.eduoutput header {{ 2315075Sgblack@eecs.umich.edu void 2325075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2335075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 2345428Sgblack@eecs.umich.edu 2355428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 2365674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 2375428Sgblack@eecs.umich.edu SegSSCheck, SegIretCheck, SegIntCSCheck 2385428Sgblack@eecs.umich.edu }; 2395678Sgblack@eecs.umich.edu 2405678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 2415678Sgblack@eecs.umich.edu LDT64 = 2, 2425678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 2435678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 2445678Sgblack@eecs.umich.edu CallGate64 = 0xc, 2455678Sgblack@eecs.umich.edu IntGate64 = 0xe, 2465678Sgblack@eecs.umich.edu TrapGate64 = 0xf 2475678Sgblack@eecs.umich.edu }; 2485075Sgblack@eecs.umich.edu}}; 2495075Sgblack@eecs.umich.edu 2505075Sgblack@eecs.umich.eduoutput decoder {{ 2515075Sgblack@eecs.umich.edu void 2525075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2535075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 2545075Sgblack@eecs.umich.edu { 2555075Sgblack@eecs.umich.edu //Check for divide by zero. 2565075Sgblack@eecs.umich.edu if (divisor == 0) 2575075Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 2585075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 2595075Sgblack@eecs.umich.edu if (divisor <= dividend) { 2605075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 2615075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 2625075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 2635075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 2645075Sgblack@eecs.umich.edu divisor <<= shift; 2655075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 2665075Sgblack@eecs.umich.edu //now larger than the dividend. 2675075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 2685075Sgblack@eecs.umich.edu quotientBit <<= shift; 2695075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2705075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2715075Sgblack@eecs.umich.edu //part of one or two bit division. 2725075Sgblack@eecs.umich.edu if (divisor > dividend) { 2735075Sgblack@eecs.umich.edu quotientBit >>= 1; 2745075Sgblack@eecs.umich.edu divisor >>= 1; 2755075Sgblack@eecs.umich.edu } 2765075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2775075Sgblack@eecs.umich.edu quotient += quotientBit; 2785075Sgblack@eecs.umich.edu remainder -= divisor; 2795075Sgblack@eecs.umich.edu } 2805075Sgblack@eecs.umich.edu } 2815075Sgblack@eecs.umich.edu}}; 2825075Sgblack@eecs.umich.edu 2834519Sgblack@eecs.umich.edulet {{ 2845040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2855040Sgblack@eecs.umich.edu # them will always work. 2865040Sgblack@eecs.umich.edu header_output = "" 2875040Sgblack@eecs.umich.edu decoder_output = "" 2885040Sgblack@eecs.umich.edu exec_output = "" 2895040Sgblack@eecs.umich.edu 2905040Sgblack@eecs.umich.edu immTemplates = ( 2915040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2925040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2935040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2945040Sgblack@eecs.umich.edu 2955040Sgblack@eecs.umich.edu regTemplates = ( 2965040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2975040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2985040Sgblack@eecs.umich.edu MicroRegOpExecute) 2995040Sgblack@eecs.umich.edu 3005040Sgblack@eecs.umich.edu class RegOpMeta(type): 3015040Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 3025040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code): 3035040Sgblack@eecs.umich.edu 3045040Sgblack@eecs.umich.edu # Globals to stick the output in 3055040Sgblack@eecs.umich.edu global header_output 3065040Sgblack@eecs.umich.edu global decoder_output 3075040Sgblack@eecs.umich.edu global exec_output 3085040Sgblack@eecs.umich.edu 3095040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 3105040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3115040Sgblack@eecs.umich.edu 3125040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3135040Sgblack@eecs.umich.edu # of this code. 3145062Sgblack@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 3155062Sgblack@eecs.umich.edu match = matcher.search(allCode) 3165062Sgblack@eecs.umich.edu if match: 3175062Sgblack@eecs.umich.edu typeQual = "" 3185062Sgblack@eecs.umich.edu if match.group("typeQual"): 3195062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 3205062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3215040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3225062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 3235062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 3245062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 3255062Sgblack@eecs.umich.edu matcher.sub(src2_name, else_code)) 3265040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 3275040Sgblack@eecs.umich.edu matcher.sub("imm8", code), 3285040Sgblack@eecs.umich.edu matcher.sub("imm8", flag_code), 3295040Sgblack@eecs.umich.edu matcher.sub("imm8", cond_check), 3305040Sgblack@eecs.umich.edu matcher.sub("imm8", else_code)) 3315040Sgblack@eecs.umich.edu return 3325040Sgblack@eecs.umich.edu 3335040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 3345040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 3355239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 3365040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3375040Sgblack@eecs.umich.edu code, "", "true", else_code) 3385040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 3395040Sgblack@eecs.umich.edu 3405040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 3415040Sgblack@eecs.umich.edu # compute it. 3425040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 3435040Sgblack@eecs.umich.edu if matcher.search(allCode): 3445061Sgblack@eecs.umich.edu code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3455040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 3465040Sgblack@eecs.umich.edu if matcher.search(allCode): 3475061Sgblack@eecs.umich.edu code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3485061Sgblack@eecs.umich.edu # Also make available versions which do sign extension 3495061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3505061Sgblack@eecs.umich.edu if matcher.search(allCode): 3515061Sgblack@eecs.umich.edu code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3525061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3535061Sgblack@eecs.umich.edu if matcher.search(allCode): 3545061Sgblack@eecs.umich.edu code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3555040Sgblack@eecs.umich.edu 3565040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3575040Sgblack@eecs.umich.edu 3585040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3595040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3605040Sgblack@eecs.umich.edu templates = regTemplates 3615040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)imm8(?!\w)") 3625040Sgblack@eecs.umich.edu if matcher.search(allCode): 3635040Sgblack@eecs.umich.edu base += "Imm" 3645040Sgblack@eecs.umich.edu templates = immTemplates 3655040Sgblack@eecs.umich.edu 3665040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3675040Sgblack@eecs.umich.edu iop = InstObjParams(name, Name + suffix, base, 3685040Sgblack@eecs.umich.edu {"code" : code, 3695040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3705040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3715040Sgblack@eecs.umich.edu "else_code" : else_code}) 3725040Sgblack@eecs.umich.edu 3735040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3745040Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3755040Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3765040Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3775040Sgblack@eecs.umich.edu 3785040Sgblack@eecs.umich.edu 3795040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3804688Sgblack@eecs.umich.edu abstract = False 3815040Sgblack@eecs.umich.edu name = Name.lower() 3824688Sgblack@eecs.umich.edu if "abstract" in dict: 3834688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3844688Sgblack@eecs.umich.edu del dict['abstract'] 3854688Sgblack@eecs.umich.edu 3865040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3874688Sgblack@eecs.umich.edu if not abstract: 3885040Sgblack@eecs.umich.edu cls.className = Name 3895040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3905040Sgblack@eecs.umich.edu code = cls.code 3915040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3925040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3935040Sgblack@eecs.umich.edu else_code = cls.else_code 3945040Sgblack@eecs.umich.edu 3955040Sgblack@eecs.umich.edu # Set up the C++ classes 3965040Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", 3975040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code) 3985040Sgblack@eecs.umich.edu 3995040Sgblack@eecs.umich.edu # Hook into the microassembler dict 4005040Sgblack@eecs.umich.edu global microopClasses 4015040Sgblack@eecs.umich.edu microopClasses[name] = cls 4025040Sgblack@eecs.umich.edu 4035040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 4045040Sgblack@eecs.umich.edu 4055040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 4065040Sgblack@eecs.umich.edu # of this code. 4075040Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 4085040Sgblack@eecs.umich.edu if matcher.search(allCode): 4095040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 4104688Sgblack@eecs.umich.edu return cls 4114688Sgblack@eecs.umich.edu 4125040Sgblack@eecs.umich.edu 4135040Sgblack@eecs.umich.edu class RegOp(X86Microop): 4145040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 4155040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 4164688Sgblack@eecs.umich.edu abstract = True 4174688Sgblack@eecs.umich.edu 4185040Sgblack@eecs.umich.edu # Default template parameter values 4195040Sgblack@eecs.umich.edu flag_code = "" 4205040Sgblack@eecs.umich.edu cond_check = "true" 4215040Sgblack@eecs.umich.edu else_code = ";" 4225040Sgblack@eecs.umich.edu 4235040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4244519Sgblack@eecs.umich.edu self.dest = dest 4254519Sgblack@eecs.umich.edu self.src1 = src1 4265040Sgblack@eecs.umich.edu self.op2 = op2 4274688Sgblack@eecs.umich.edu self.flags = flags 4284701Sgblack@eecs.umich.edu self.dataSize = dataSize 4294688Sgblack@eecs.umich.edu if flags is None: 4304688Sgblack@eecs.umich.edu self.ext = 0 4314688Sgblack@eecs.umich.edu else: 4324688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4334688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4344688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 4354688Sgblack@eecs.umich.edu self.className += "Flags" 4364519Sgblack@eecs.umich.edu 4374519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 4385040Sgblack@eecs.umich.edu className = self.className 4395040Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4405040Sgblack@eecs.umich.edu className += "Imm" 4415788Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock 4425040Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4434688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4445040Sgblack@eecs.umich.edu "class_name" : className, 4454519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4465040Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4474519Sgblack@eecs.umich.edu "dest" : self.dest, 4484519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4494519Sgblack@eecs.umich.edu "ext" : self.ext} 4504539Sgblack@eecs.umich.edu return allocator 4514519Sgblack@eecs.umich.edu 4525040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4534688Sgblack@eecs.umich.edu abstract = True 4545040Sgblack@eecs.umich.edu flag_code = ''' 4555040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4565115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4575040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4585040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4595040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 4605115Sgblack@eecs.umich.edu ccFlagBits &= ~(ECFBit & ext); 4615040Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 4625040Sgblack@eecs.umich.edu ''' 4634519Sgblack@eecs.umich.edu 4645040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4655040Sgblack@eecs.umich.edu abstract = True 4665040Sgblack@eecs.umich.edu flag_code = \ 4675040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4684519Sgblack@eecs.umich.edu 4695040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4705040Sgblack@eecs.umich.edu abstract = True 4715040Sgblack@eecs.umich.edu flag_code = \ 4725040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4734519Sgblack@eecs.umich.edu 4745040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4755040Sgblack@eecs.umich.edu abstract = True 4765083Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits, ext)" 4774519Sgblack@eecs.umich.edu 4785063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4795063Sgblack@eecs.umich.edu abstract = True 4805063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4815063Sgblack@eecs.umich.edu if not src1: 4825063Sgblack@eecs.umich.edu src1 = dest 4835063Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 4845063Sgblack@eecs.umich.edu 4855063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4865063Sgblack@eecs.umich.edu abstract = True 4875063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4885063Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 4895063Sgblack@eecs.umich.edu 4905040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4915040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4924595Sgblack@eecs.umich.edu 4935040Sgblack@eecs.umich.edu class Or(LogicRegOp): 4945040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4954595Sgblack@eecs.umich.edu 4965040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 4975040Sgblack@eecs.umich.edu code = ''' 4984732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4995138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 5005040Sgblack@eecs.umich.edu ''' 5015040Sgblack@eecs.umich.edu 5025040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 5035040Sgblack@eecs.umich.edu code = ''' 5044732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5055138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 5065040Sgblack@eecs.umich.edu ''' 5075040Sgblack@eecs.umich.edu 5085040Sgblack@eecs.umich.edu class And(LogicRegOp): 5095040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 5105040Sgblack@eecs.umich.edu 5115040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5125040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 5135040Sgblack@eecs.umich.edu 5145040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5155040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 5165040Sgblack@eecs.umich.edu 5175065Sgblack@eecs.umich.edu # Neither of these is quite correct because it assumes that right shifting 5185065Sgblack@eecs.umich.edu # a signed or unsigned value does sign or zero extension respectively. 5195065Sgblack@eecs.umich.edu # The C standard says that what happens on a right shift with a 1 in the 5205065Sgblack@eecs.umich.edu # MSB position is undefined. On x86 and under likely most compilers the 5215065Sgblack@eecs.umich.edu # "right thing" happens, but this isn't a guarantee. 5225063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5235040Sgblack@eecs.umich.edu code = ''' 5245063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5255063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5265063Sgblack@eecs.umich.edu int64_t spsrc1_h = spsrc1 >> halfSize; 5275063Sgblack@eecs.umich.edu int64_t spsrc1_l = spsrc1 & mask(halfSize); 5285063Sgblack@eecs.umich.edu int64_t spsrc2_h = sop2 >> halfSize; 5295063Sgblack@eecs.umich.edu int64_t spsrc2_l = sop2 & mask(halfSize); 5305063Sgblack@eecs.umich.edu ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l + 5315063Sgblack@eecs.umich.edu ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) + 5325063Sgblack@eecs.umich.edu spsrc1_h * spsrc2_h; 5335040Sgblack@eecs.umich.edu ''' 5345040Sgblack@eecs.umich.edu 5355063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5365040Sgblack@eecs.umich.edu code = ''' 5375063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5384809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5395063Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 >> halfSize; 5405063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5415063Sgblack@eecs.umich.edu uint64_t psrc2_h = op2 >> halfSize; 5425063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5435063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5445063Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) + 5455063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5465040Sgblack@eecs.umich.edu ''' 5475040Sgblack@eecs.umich.edu 5485063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5495063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5505040Sgblack@eecs.umich.edu 5515063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5525063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5535063Sgblack@eecs.umich.edu if not src1: 5545063Sgblack@eecs.umich.edu src1 = dest 5555063Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize) 5565063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5575063Sgblack@eecs.umich.edu flag_code = ''' 5585063Sgblack@eecs.umich.edu if (ProdHi) 5595063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5605063Sgblack@eecs.umich.edu else 5615063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5625063Sgblack@eecs.umich.edu ''' 5635062Sgblack@eecs.umich.edu 5645075Sgblack@eecs.umich.edu # One or two bit divide 5655075Sgblack@eecs.umich.edu class Div1(WrRegOp): 5665040Sgblack@eecs.umich.edu code = ''' 5675075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 5685075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5695075Sgblack@eecs.umich.edu uint64_t quotient = 0; 5705075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 5715075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 5725075Sgblack@eecs.umich.edu //a source. 5735075Sgblack@eecs.umich.edu uint64_t divisor = op2; 5745075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 5755075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 5765075Sgblack@eecs.umich.edu //Do the division. 5775075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5785075Sgblack@eecs.umich.edu //Record the final results. 5795075Sgblack@eecs.umich.edu Remainder = remainder; 5805075Sgblack@eecs.umich.edu Quotient = quotient; 5815075Sgblack@eecs.umich.edu Divisor = divisor; 5825040Sgblack@eecs.umich.edu ''' 5834823Sgblack@eecs.umich.edu 5845075Sgblack@eecs.umich.edu # Step divide 5855075Sgblack@eecs.umich.edu class Div2(RegOp): 5865075Sgblack@eecs.umich.edu code = ''' 5875075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 5885075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 5895075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 5905075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 5915075Sgblack@eecs.umich.edu int remaining = op2; 5925075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 5935075Sgblack@eecs.umich.edu //little. 5945075Sgblack@eecs.umich.edu if (remaining) { 5955075Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 5965075Sgblack@eecs.umich.edu while(dividend < divisor && remaining) { 5975075Sgblack@eecs.umich.edu dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 5985075Sgblack@eecs.umich.edu quotient <<= 1; 5995075Sgblack@eecs.umich.edu remaining--; 6005075Sgblack@eecs.umich.edu } 6015075Sgblack@eecs.umich.edu remainder = dividend; 6025075Sgblack@eecs.umich.edu //Do the division. 6035075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6045075Sgblack@eecs.umich.edu } 6055075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 6065075Sgblack@eecs.umich.edu DestReg = merge(DestReg, remaining, dataSize); 6075075Sgblack@eecs.umich.edu //Record the final results 6085075Sgblack@eecs.umich.edu Remainder = remainder; 6095075Sgblack@eecs.umich.edu Quotient = quotient; 6105075Sgblack@eecs.umich.edu ''' 6115075Sgblack@eecs.umich.edu flag_code = ''' 6125075Sgblack@eecs.umich.edu if (DestReg == 0) 6135075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & EZFBit); 6145075Sgblack@eecs.umich.edu else 6155075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6165075Sgblack@eecs.umich.edu ''' 6174732Sgblack@eecs.umich.edu 6185075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6195075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6205075Sgblack@eecs.umich.edu 6215075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6225075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6235040Sgblack@eecs.umich.edu 6245040Sgblack@eecs.umich.edu class Mov(CondRegOp): 6255040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6265040Sgblack@eecs.umich.edu else_code = 'DestReg=DestReg;' 6275040Sgblack@eecs.umich.edu 6284732Sgblack@eecs.umich.edu # Shift instructions 6295040Sgblack@eecs.umich.edu 6305076Sgblack@eecs.umich.edu class Sll(RegOp): 6315040Sgblack@eecs.umich.edu code = ''' 6324756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6334823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6345040Sgblack@eecs.umich.edu ''' 6355076Sgblack@eecs.umich.edu flag_code = ''' 6365076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6375076Sgblack@eecs.umich.edu if (shiftAmt) { 6385076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6395076Sgblack@eecs.umich.edu //worry about setting them. 6405076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6415076Sgblack@eecs.umich.edu int CFBits = 0; 6425076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 6435076Sgblack@eecs.umich.edu if (bits(SrcReg1, dataSize * 8 - shiftAmt)) 6445076Sgblack@eecs.umich.edu CFBits = 1; 6455076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6465076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 6475076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6485076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6495076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 6505076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6515076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6525076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6535076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6545076Sgblack@eecs.umich.edu } 6555076Sgblack@eecs.umich.edu ''' 6565040Sgblack@eecs.umich.edu 6575076Sgblack@eecs.umich.edu class Srl(RegOp): 6585040Sgblack@eecs.umich.edu code = ''' 6594756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6604732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6614732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 6624732Sgblack@eecs.umich.edu // to be sure they're zero. 6634732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 6644823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 6655040Sgblack@eecs.umich.edu ''' 6665076Sgblack@eecs.umich.edu flag_code = ''' 6675076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6685076Sgblack@eecs.umich.edu if (shiftAmt) { 6695076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6705076Sgblack@eecs.umich.edu //worry about setting them. 6715076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6725076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6735076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 6745076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6755076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6765076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 6775076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6785076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6795076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6805076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6815076Sgblack@eecs.umich.edu } 6825076Sgblack@eecs.umich.edu ''' 6835040Sgblack@eecs.umich.edu 6845076Sgblack@eecs.umich.edu class Sra(RegOp): 6855040Sgblack@eecs.umich.edu code = ''' 6864756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6874732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6884732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 6894732Sgblack@eecs.umich.edu // them manually to be sure. 6904732Sgblack@eecs.umich.edu uint64_t arithMask = 6915032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 6924823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 6935040Sgblack@eecs.umich.edu ''' 6945076Sgblack@eecs.umich.edu flag_code = ''' 6955076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6965076Sgblack@eecs.umich.edu if (shiftAmt) { 6975076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6985076Sgblack@eecs.umich.edu //worry about setting them. 6995076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7005076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7015076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 7025076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7035076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7045076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7055076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7065076Sgblack@eecs.umich.edu } 7075076Sgblack@eecs.umich.edu ''' 7085040Sgblack@eecs.umich.edu 7095076Sgblack@eecs.umich.edu class Ror(RegOp): 7105040Sgblack@eecs.umich.edu code = ''' 7114732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7124756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7134732Sgblack@eecs.umich.edu if(shiftAmt) 7144732Sgblack@eecs.umich.edu { 7154823Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 7164823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 7174732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7184732Sgblack@eecs.umich.edu } 7194732Sgblack@eecs.umich.edu else 7204732Sgblack@eecs.umich.edu DestReg = DestReg; 7215040Sgblack@eecs.umich.edu ''' 7225076Sgblack@eecs.umich.edu flag_code = ''' 7235076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7245076Sgblack@eecs.umich.edu if (shiftAmt) { 7255076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7265076Sgblack@eecs.umich.edu //worry about setting them. 7275076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7285076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 7295076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7305076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 7315076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7325076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && msb) 7335076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7345076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7355076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 7365076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7375076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7385076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7395076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7405076Sgblack@eecs.umich.edu } 7415076Sgblack@eecs.umich.edu ''' 7425040Sgblack@eecs.umich.edu 7435076Sgblack@eecs.umich.edu class Rcr(RegOp): 7445040Sgblack@eecs.umich.edu code = ''' 7454733Sgblack@eecs.umich.edu uint8_t shiftAmt = 7464756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7474733Sgblack@eecs.umich.edu if(shiftAmt) 7484733Sgblack@eecs.umich.edu { 7494733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 7505138Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - shiftAmt); 7514733Sgblack@eecs.umich.edu if(shiftAmt > 1) 7524823Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 7534823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 7544733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7554733Sgblack@eecs.umich.edu } 7564733Sgblack@eecs.umich.edu else 7574733Sgblack@eecs.umich.edu DestReg = DestReg; 7585040Sgblack@eecs.umich.edu ''' 7595076Sgblack@eecs.umich.edu flag_code = ''' 7605076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7615076Sgblack@eecs.umich.edu if (shiftAmt) { 7625076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7635076Sgblack@eecs.umich.edu //worry about setting them. 7645076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7655076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7665076Sgblack@eecs.umich.edu if ((ext & OFBit) && ((ccFlagBits & CFBit) ^ 7675076Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) 7685076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7695076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7705076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 7715076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7725076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7735076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7745076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7755076Sgblack@eecs.umich.edu } 7765076Sgblack@eecs.umich.edu ''' 7775040Sgblack@eecs.umich.edu 7785076Sgblack@eecs.umich.edu class Rol(RegOp): 7795040Sgblack@eecs.umich.edu code = ''' 7804732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7814756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7824732Sgblack@eecs.umich.edu if(shiftAmt) 7834732Sgblack@eecs.umich.edu { 7844823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 7854732Sgblack@eecs.umich.edu uint64_t bottom = 7864823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 7874732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7884732Sgblack@eecs.umich.edu } 7894732Sgblack@eecs.umich.edu else 7904732Sgblack@eecs.umich.edu DestReg = DestReg; 7915040Sgblack@eecs.umich.edu ''' 7925076Sgblack@eecs.umich.edu flag_code = ''' 7935076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7945076Sgblack@eecs.umich.edu if (shiftAmt) { 7955076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7965076Sgblack@eecs.umich.edu //worry about setting them. 7975076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7985076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 7995076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 8005076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8015076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8025076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && lsb) 8035076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8045076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8055076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 8065076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8075076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8085076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8095076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8105076Sgblack@eecs.umich.edu } 8115076Sgblack@eecs.umich.edu ''' 8125040Sgblack@eecs.umich.edu 8135076Sgblack@eecs.umich.edu class Rcl(RegOp): 8145040Sgblack@eecs.umich.edu code = ''' 8154733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8164756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8174733Sgblack@eecs.umich.edu if(shiftAmt) 8184733Sgblack@eecs.umich.edu { 8194733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8204823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 8215138Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (shiftAmt - 1); 8224733Sgblack@eecs.umich.edu if(shiftAmt > 1) 8234733Sgblack@eecs.umich.edu bottom |= 8244823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 8254809Sgblack@eecs.umich.edu dataSize * 8 - shiftAmt + 1); 8264733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8274733Sgblack@eecs.umich.edu } 8284733Sgblack@eecs.umich.edu else 8294733Sgblack@eecs.umich.edu DestReg = DestReg; 8305040Sgblack@eecs.umich.edu ''' 8315076Sgblack@eecs.umich.edu flag_code = ''' 8325076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8335076Sgblack@eecs.umich.edu if (shiftAmt) { 8345076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8355076Sgblack@eecs.umich.edu //worry about setting them. 8365076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8375076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8385076Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt); 8395076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8405076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 8415076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8425076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8435076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 8445076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8455076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8465076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8475076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8485076Sgblack@eecs.umich.edu } 8495076Sgblack@eecs.umich.edu ''' 8504732Sgblack@eecs.umich.edu 8515040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 8525246Sgblack@eecs.umich.edu code = 'RIP = psrc1 + sop2 + CSBase' 8535040Sgblack@eecs.umich.edu else_code="RIP = RIP;" 8545040Sgblack@eecs.umich.edu 8555040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 8565040Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 8575040Sgblack@eecs.umich.edu 8585426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 8595426Sgblack@eecs.umich.edu code = ''' 8605426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 8615426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 8625426Sgblack@eecs.umich.edu // Get only the user flags 8635426Sgblack@eecs.umich.edu ccFlagBits = newFlags & userFlagMask; 8645426Sgblack@eecs.umich.edu // Get everything else 8655426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 8665426Sgblack@eecs.umich.edu ''' 8675426Sgblack@eecs.umich.edu 8685040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 8695246Sgblack@eecs.umich.edu code = 'DestReg = RIP - CSBase' 8705040Sgblack@eecs.umich.edu 8715040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 8725040Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 8735040Sgblack@eecs.umich.edu 8745426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 8755426Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits | nccFlagBits' 8765426Sgblack@eecs.umich.edu 8775040Sgblack@eecs.umich.edu class Ruflag(RegOp): 8785040Sgblack@eecs.umich.edu code = ''' 8795116Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8); 8804951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 8815011Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 8825011Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 8835040Sgblack@eecs.umich.edu ''' 8845040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 8855040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 8865040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 8875040Sgblack@eecs.umich.edu "NUM_INTREGS", imm, flags, dataSize) 8884732Sgblack@eecs.umich.edu 8895426Sgblack@eecs.umich.edu class Rflag(RegOp): 8905426Sgblack@eecs.umich.edu code = ''' 8915426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 8925426Sgblack@eecs.umich.edu MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 8935426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 8945426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 8955426Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 8965426Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 8975426Sgblack@eecs.umich.edu ''' 8985426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 8995426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 9005426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 9015426Sgblack@eecs.umich.edu "NUM_INTREGS", imm, flags, dataSize) 9025426Sgblack@eecs.umich.edu 9035040Sgblack@eecs.umich.edu class Sext(RegOp): 9045040Sgblack@eecs.umich.edu code = ''' 9054823Sgblack@eecs.umich.edu IntReg val = psrc1; 9065239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 9075239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 9085239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 9095239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 9105007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 9115007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 9125040Sgblack@eecs.umich.edu ''' 9135239Sgblack@eecs.umich.edu flag_code = ''' 9145239Sgblack@eecs.umich.edu if (!sign_bit) 9155239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & 9165239Sgblack@eecs.umich.edu ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 9175239Sgblack@eecs.umich.edu else 9185239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | 9195239Sgblack@eecs.umich.edu (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 9205239Sgblack@eecs.umich.edu ''' 9214714Sgblack@eecs.umich.edu 9225040Sgblack@eecs.umich.edu class Zext(RegOp): 9235239Sgblack@eecs.umich.edu code = 'DestReg = bits(psrc1, op2, 0);' 9245241Sgblack@eecs.umich.edu 9255296Sgblack@eecs.umich.edu class Rdcr(RegOp): 9265296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9275296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 9285296Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 9295296Sgblack@eecs.umich.edu code = ''' 9305296Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 9315296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 9325296Sgblack@eecs.umich.edu } else { 9335296Sgblack@eecs.umich.edu DestReg = ControlSrc1; 9345296Sgblack@eecs.umich.edu } 9355296Sgblack@eecs.umich.edu ''' 9365296Sgblack@eecs.umich.edu 9375241Sgblack@eecs.umich.edu class Wrcr(RegOp): 9385241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9395241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 9405241Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 9415241Sgblack@eecs.umich.edu code = ''' 9425241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 9435241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 9445241Sgblack@eecs.umich.edu } else { 9455241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 9465241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 9475241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 9485241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 9495241Sgblack@eecs.umich.edu 9505241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 9515241Sgblack@eecs.umich.edu switch(dest) { 9525241Sgblack@eecs.umich.edu case 0: 9535241Sgblack@eecs.umich.edu { 9545241Sgblack@eecs.umich.edu Efer efer = EferOp; 9555241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 9565241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 9575241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 9585241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 9595241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 9605241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 9615241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9625241Sgblack@eecs.umich.edu } 9635241Sgblack@eecs.umich.edu break; 9645241Sgblack@eecs.umich.edu case 2: 9655241Sgblack@eecs.umich.edu break; 9665241Sgblack@eecs.umich.edu case 3: 9675241Sgblack@eecs.umich.edu break; 9685241Sgblack@eecs.umich.edu case 4: 9695241Sgblack@eecs.umich.edu { 9705241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 9715241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 9725241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 9735241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 9745241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9755241Sgblack@eecs.umich.edu } 9765241Sgblack@eecs.umich.edu break; 9775241Sgblack@eecs.umich.edu case 8: 9785241Sgblack@eecs.umich.edu { 9795241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 9805241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9815241Sgblack@eecs.umich.edu } 9825241Sgblack@eecs.umich.edu default: 9835241Sgblack@eecs.umich.edu panic("Unrecognized control register %d.\\n", dest); 9845241Sgblack@eecs.umich.edu } 9855241Sgblack@eecs.umich.edu ControlDest = newVal; 9865241Sgblack@eecs.umich.edu } 9875241Sgblack@eecs.umich.edu ''' 9885290Sgblack@eecs.umich.edu 9895294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 9905672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 9915294Sgblack@eecs.umich.edu abstract = True 9925290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9935294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 9945290Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 9955294Sgblack@eecs.umich.edu 9965294Sgblack@eecs.umich.edu class Wrbase(SegOp): 9975290Sgblack@eecs.umich.edu code = ''' 9985294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 9995290Sgblack@eecs.umich.edu ''' 10005290Sgblack@eecs.umich.edu 10015294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 10025290Sgblack@eecs.umich.edu code = ''' 10035294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 10045294Sgblack@eecs.umich.edu ''' 10055294Sgblack@eecs.umich.edu 10065294Sgblack@eecs.umich.edu class Wrsel(SegOp): 10075294Sgblack@eecs.umich.edu code = ''' 10085294Sgblack@eecs.umich.edu SegSelDest = psrc1; 10095294Sgblack@eecs.umich.edu ''' 10105294Sgblack@eecs.umich.edu 10115294Sgblack@eecs.umich.edu class Rdbase(SegOp): 10125294Sgblack@eecs.umich.edu code = ''' 10135670Sgblack@eecs.umich.edu DestReg = SegBaseSrc1; 10145294Sgblack@eecs.umich.edu ''' 10155294Sgblack@eecs.umich.edu 10165294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 10175294Sgblack@eecs.umich.edu code = ''' 10185294Sgblack@eecs.umich.edu DestReg = SegLimitSrc1; 10195294Sgblack@eecs.umich.edu ''' 10205294Sgblack@eecs.umich.edu 10215427Sgblack@eecs.umich.edu class RdAttr(SegOp): 10225427Sgblack@eecs.umich.edu code = ''' 10235427Sgblack@eecs.umich.edu DestReg = SegAttrSrc1; 10245427Sgblack@eecs.umich.edu ''' 10255427Sgblack@eecs.umich.edu 10265294Sgblack@eecs.umich.edu class Rdsel(SegOp): 10275294Sgblack@eecs.umich.edu code = ''' 10285294Sgblack@eecs.umich.edu DestReg = SegSelSrc1; 10295294Sgblack@eecs.umich.edu ''' 10305294Sgblack@eecs.umich.edu 10315682Sgblack@eecs.umich.edu class Rdval(RegOp): 10325682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10335682Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, \ 10345682Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 10355682Sgblack@eecs.umich.edu code = ''' 10365682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 10375682Sgblack@eecs.umich.edu ''' 10385682Sgblack@eecs.umich.edu 10395682Sgblack@eecs.umich.edu class Wrval(RegOp): 10405682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 10415682Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, \ 10425682Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 10435682Sgblack@eecs.umich.edu code = ''' 10445682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 10455682Sgblack@eecs.umich.edu ''' 10465682Sgblack@eecs.umich.edu 10475428Sgblack@eecs.umich.edu class Chks(RegOp): 10485428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 10495428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 10505428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 10515428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 10525294Sgblack@eecs.umich.edu code = ''' 10535424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 10545433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 10555433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 10565433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 10575294Sgblack@eecs.umich.edu 10585428Sgblack@eecs.umich.edu switch (imm8) 10595428Sgblack@eecs.umich.edu { 10605428Sgblack@eecs.umich.edu case SegNoCheck: 10615428Sgblack@eecs.umich.edu break; 10625428Sgblack@eecs.umich.edu case SegCSCheck: 10635428Sgblack@eecs.umich.edu panic("CS checks for far calls/jumps not implemented.\\n"); 10645428Sgblack@eecs.umich.edu break; 10655428Sgblack@eecs.umich.edu case SegCallGateCheck: 10665428Sgblack@eecs.umich.edu panic("CS checks for far calls/jumps through call gates" 10675428Sgblack@eecs.umich.edu "not implemented.\\n"); 10685428Sgblack@eecs.umich.edu break; 10695674Sgblack@eecs.umich.edu case SegIntGateCheck: 10705674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 10715679Sgblack@eecs.umich.edu fault = new GeneralProtection((uint16_t)selector); 10725674Sgblack@eecs.umich.edu } 10735674Sgblack@eecs.umich.edu break; 10745428Sgblack@eecs.umich.edu case SegSSCheck: 10755433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 10765433Sgblack@eecs.umich.edu if (!desc.p) { 10775433Sgblack@eecs.umich.edu //FIXME This needs to also push the selector. 10785679Sgblack@eecs.umich.edu fault = new StackFault; 10795433Sgblack@eecs.umich.edu } 10805433Sgblack@eecs.umich.edu } else { 10815673Sgblack@eecs.umich.edu if ((m5reg.submode != SixtyFourBitMode || 10825673Sgblack@eecs.umich.edu m5reg.cpl == 3) || 10835433Sgblack@eecs.umich.edu !(desc.s == 1 && 10845433Sgblack@eecs.umich.edu desc.type.codeOrData == 0 && desc.type.w) || 10855433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 10865433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 10875679Sgblack@eecs.umich.edu fault = new GeneralProtection(psrc1 & 0xFFFF); 10885433Sgblack@eecs.umich.edu } 10895433Sgblack@eecs.umich.edu } 10905428Sgblack@eecs.umich.edu break; 10915428Sgblack@eecs.umich.edu case SegIretCheck: 10925428Sgblack@eecs.umich.edu { 10935433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 10945433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 10955433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 10965433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 10975679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 10985679Sgblack@eecs.umich.edu fault = new GeneralProtection(psrc1 & 0xFFFF); 10995679Sgblack@eecs.umich.edu } else if (!desc.p) { 11005679Sgblack@eecs.umich.edu fault = new SegmentNotPresent; 11015679Sgblack@eecs.umich.edu } 11025428Sgblack@eecs.umich.edu break; 11035428Sgblack@eecs.umich.edu } 11045428Sgblack@eecs.umich.edu case SegIntCSCheck: 11055675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 11065675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 11075679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 11085675Sgblack@eecs.umich.edu } 11095675Sgblack@eecs.umich.edu } else { 11105675Sgblack@eecs.umich.edu panic("Interrupt CS checks not implemented " 11115675Sgblack@eecs.umich.edu "in legacy mode.\\n"); 11125675Sgblack@eecs.umich.edu } 11135428Sgblack@eecs.umich.edu break; 11145428Sgblack@eecs.umich.edu default: 11155428Sgblack@eecs.umich.edu panic("Undefined segment check type.\\n"); 11165428Sgblack@eecs.umich.edu } 11175294Sgblack@eecs.umich.edu ''' 11185294Sgblack@eecs.umich.edu flag_code = ''' 11195294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 11205294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 11215424Sgblack@eecs.umich.edu if (!selector.si && !selector.ti) 11225294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 11235294Sgblack@eecs.umich.edu ''' 11245294Sgblack@eecs.umich.edu 11255294Sgblack@eecs.umich.edu class Wrdh(RegOp): 11265294Sgblack@eecs.umich.edu code = ''' 11275678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 11285294Sgblack@eecs.umich.edu 11295678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 11305678Sgblack@eecs.umich.edu switch(desc.type) { 11315678Sgblack@eecs.umich.edu case LDT64: 11325678Sgblack@eecs.umich.edu case AvailableTSS64: 11335678Sgblack@eecs.umich.edu case BusyTSS64: 11345678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 11355678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 11365678Sgblack@eecs.umich.edu break; 11375678Sgblack@eecs.umich.edu case CallGate64: 11385678Sgblack@eecs.umich.edu case IntGate64: 11395678Sgblack@eecs.umich.edu case TrapGate64: 11405678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 11415678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 11425678Sgblack@eecs.umich.edu break; 11435678Sgblack@eecs.umich.edu default: 11445678Sgblack@eecs.umich.edu panic("Wrdh used with wrong descriptor type!\\n"); 11455678Sgblack@eecs.umich.edu } 11465678Sgblack@eecs.umich.edu DestReg = target; 11475294Sgblack@eecs.umich.edu ''' 11485294Sgblack@eecs.umich.edu 11495409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 11505409Sgblack@eecs.umich.edu code = ''' 11515409Sgblack@eecs.umich.edu TscOp = psrc1; 11525409Sgblack@eecs.umich.edu ''' 11535409Sgblack@eecs.umich.edu 11545409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 11555409Sgblack@eecs.umich.edu code = ''' 11565409Sgblack@eecs.umich.edu DestReg = TscOp; 11575409Sgblack@eecs.umich.edu ''' 11585409Sgblack@eecs.umich.edu 11595429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 11605429Sgblack@eecs.umich.edu code = ''' 11615429Sgblack@eecs.umich.edu DestReg = M5Reg; 11625429Sgblack@eecs.umich.edu ''' 11635429Sgblack@eecs.umich.edu 11645294Sgblack@eecs.umich.edu class Wrdl(RegOp): 11655294Sgblack@eecs.umich.edu code = ''' 11665294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 11675433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 11685433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 11695433Sgblack@eecs.umich.edu SegAttr attr = 0; 11705433Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 11715433Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 11725433Sgblack@eecs.umich.edu if (!desc.s) { 11735433Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 11745433Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 11755433Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 11765433Sgblack@eecs.umich.edu panic("System segment encountered.\\n"); 11775433Sgblack@eecs.umich.edu } else { 11785433Sgblack@eecs.umich.edu if (!desc.p) 11795433Sgblack@eecs.umich.edu panic("Segment not present.\\n"); 11805433Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 11815433Sgblack@eecs.umich.edu attr.readable = desc.type.r; 11825433Sgblack@eecs.umich.edu attr.longMode = desc.l; 11835433Sgblack@eecs.umich.edu } else { 11845433Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 11855433Sgblack@eecs.umich.edu attr.readable = 1; 11865433Sgblack@eecs.umich.edu attr.writable = desc.type.w; 11875433Sgblack@eecs.umich.edu } 11885433Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 11895433Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 11905433Sgblack@eecs.umich.edu if (desc.g) 11915433Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 11925433Sgblack@eecs.umich.edu SegBaseDest = base; 11935433Sgblack@eecs.umich.edu SegLimitDest = limit; 11945433Sgblack@eecs.umich.edu SegAttrDest = attr; 11955433Sgblack@eecs.umich.edu } 11965433Sgblack@eecs.umich.edu } else { 11975295Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 11985295Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 11995295Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 12005294Sgblack@eecs.umich.edu } 12015290Sgblack@eecs.umich.edu ''' 12024519Sgblack@eecs.umich.edu}}; 1203