regop.isa revision 5675
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 44519Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 54519Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 64519Sgblack@eecs.umich.edu// following conditions are met: 74519Sgblack@eecs.umich.edu// 84519Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 94519Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 104519Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 114519Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 134519Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 144519Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 154519Sgblack@eecs.umich.edu// commercial advantage. 164519Sgblack@eecs.umich.edu// 174519Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 184519Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 194519Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 204519Sgblack@eecs.umich.edu// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 224519Sgblack@eecs.umich.edu// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 274519Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 284519Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 294519Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 304519Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 314519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 324519Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 334519Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 344519Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 354519Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534519Sgblack@eecs.umich.edu// 544519Sgblack@eecs.umich.edu// Authors: Gabe Black 554519Sgblack@eecs.umich.edu 564519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574519Sgblack@eecs.umich.edu// 584519Sgblack@eecs.umich.edu// RegOp Microop templates 594519Sgblack@eecs.umich.edu// 604519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614519Sgblack@eecs.umich.edu 624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 694519Sgblack@eecs.umich.edu %(op_decl)s; 704519Sgblack@eecs.umich.edu %(op_rd)s; 714688Sgblack@eecs.umich.edu 724688Sgblack@eecs.umich.edu if(%(cond_check)s) 734688Sgblack@eecs.umich.edu { 744688Sgblack@eecs.umich.edu %(code)s; 754688Sgblack@eecs.umich.edu %(flag_code)s; 764688Sgblack@eecs.umich.edu } 774708Sgblack@eecs.umich.edu else 784708Sgblack@eecs.umich.edu { 794708Sgblack@eecs.umich.edu %(else_code)s; 804708Sgblack@eecs.umich.edu } 814519Sgblack@eecs.umich.edu 824519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 834519Sgblack@eecs.umich.edu if(fault == NoFault) 844519Sgblack@eecs.umich.edu { 854519Sgblack@eecs.umich.edu %(op_wb)s; 864519Sgblack@eecs.umich.edu } 874519Sgblack@eecs.umich.edu return fault; 884519Sgblack@eecs.umich.edu } 894519Sgblack@eecs.umich.edu}}; 904519Sgblack@eecs.umich.edu 914519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 924951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 934519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 944519Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu Fault fault = NoFault; 964519Sgblack@eecs.umich.edu 974519Sgblack@eecs.umich.edu %(op_decl)s; 984519Sgblack@eecs.umich.edu %(op_rd)s; 994688Sgblack@eecs.umich.edu 1004688Sgblack@eecs.umich.edu if(%(cond_check)s) 1014688Sgblack@eecs.umich.edu { 1024688Sgblack@eecs.umich.edu %(code)s; 1034688Sgblack@eecs.umich.edu %(flag_code)s; 1044688Sgblack@eecs.umich.edu } 1054708Sgblack@eecs.umich.edu else 1064708Sgblack@eecs.umich.edu { 1074708Sgblack@eecs.umich.edu %(else_code)s; 1084708Sgblack@eecs.umich.edu } 1094519Sgblack@eecs.umich.edu 1104519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1114519Sgblack@eecs.umich.edu if(fault == NoFault) 1124519Sgblack@eecs.umich.edu { 1134519Sgblack@eecs.umich.edu %(op_wb)s; 1144519Sgblack@eecs.umich.edu } 1154519Sgblack@eecs.umich.edu return fault; 1164519Sgblack@eecs.umich.edu } 1174519Sgblack@eecs.umich.edu}}; 1184519Sgblack@eecs.umich.edu 1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1204519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu protected: 1234519Sgblack@eecs.umich.edu void buildMe(); 1244519Sgblack@eecs.umich.edu 1254519Sgblack@eecs.umich.edu public: 1264519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1274519Sgblack@eecs.umich.edu const char * instMnem, 1284519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1294519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1304712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1334519Sgblack@eecs.umich.edu const char * instMnem, 1344519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1354712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1364519Sgblack@eecs.umich.edu 1374519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1384519Sgblack@eecs.umich.edu }; 1394519Sgblack@eecs.umich.edu}}; 1404519Sgblack@eecs.umich.edu 1414519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1424519Sgblack@eecs.umich.edu 1434951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1444519Sgblack@eecs.umich.edu { 1454519Sgblack@eecs.umich.edu protected: 1464519Sgblack@eecs.umich.edu void buildMe(); 1474519Sgblack@eecs.umich.edu 1484519Sgblack@eecs.umich.edu public: 1494951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1504519Sgblack@eecs.umich.edu const char * instMnem, 1514519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1524951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1534712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1544519Sgblack@eecs.umich.edu 1554951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1564519Sgblack@eecs.umich.edu const char * instMnem, 1574951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1584712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1594519Sgblack@eecs.umich.edu 1604519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1614519Sgblack@eecs.umich.edu }; 1624519Sgblack@eecs.umich.edu}}; 1634519Sgblack@eecs.umich.edu 1644519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1654519Sgblack@eecs.umich.edu 1664519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1674519Sgblack@eecs.umich.edu { 1684519Sgblack@eecs.umich.edu %(constructor)s; 1694519Sgblack@eecs.umich.edu } 1704519Sgblack@eecs.umich.edu 1714519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1724519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1734519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1744712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1754519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1764581Sgblack@eecs.umich.edu false, false, false, false, 1774688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1784581Sgblack@eecs.umich.edu %(op_class)s) 1794519Sgblack@eecs.umich.edu { 1804519Sgblack@eecs.umich.edu buildMe(); 1814519Sgblack@eecs.umich.edu } 1824519Sgblack@eecs.umich.edu 1834519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1844519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1854519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1864519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1874712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1884519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1894581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1904688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1914581Sgblack@eecs.umich.edu %(op_class)s) 1924519Sgblack@eecs.umich.edu { 1934519Sgblack@eecs.umich.edu buildMe(); 1944519Sgblack@eecs.umich.edu } 1954519Sgblack@eecs.umich.edu}}; 1964519Sgblack@eecs.umich.edu 1974519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1984519Sgblack@eecs.umich.edu 1994951Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 2004519Sgblack@eecs.umich.edu { 2014519Sgblack@eecs.umich.edu %(constructor)s; 2024519Sgblack@eecs.umich.edu } 2034519Sgblack@eecs.umich.edu 2044951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2054519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2064951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2074712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2084519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2094581Sgblack@eecs.umich.edu false, false, false, false, 2104688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2114581Sgblack@eecs.umich.edu %(op_class)s) 2124519Sgblack@eecs.umich.edu { 2134519Sgblack@eecs.umich.edu buildMe(); 2144519Sgblack@eecs.umich.edu } 2154519Sgblack@eecs.umich.edu 2164951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2174519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2184519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2194951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2204712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2214519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2224581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2234688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2244581Sgblack@eecs.umich.edu %(op_class)s) 2254519Sgblack@eecs.umich.edu { 2264519Sgblack@eecs.umich.edu buildMe(); 2274519Sgblack@eecs.umich.edu } 2284519Sgblack@eecs.umich.edu}}; 2294519Sgblack@eecs.umich.edu 2305075Sgblack@eecs.umich.eduoutput header {{ 2315075Sgblack@eecs.umich.edu void 2325075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2335075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 2345428Sgblack@eecs.umich.edu 2355428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 2365674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 2375428Sgblack@eecs.umich.edu SegSSCheck, SegIretCheck, SegIntCSCheck 2385428Sgblack@eecs.umich.edu }; 2395075Sgblack@eecs.umich.edu}}; 2405075Sgblack@eecs.umich.edu 2415075Sgblack@eecs.umich.eduoutput decoder {{ 2425075Sgblack@eecs.umich.edu void 2435075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2445075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 2455075Sgblack@eecs.umich.edu { 2465075Sgblack@eecs.umich.edu //Check for divide by zero. 2475075Sgblack@eecs.umich.edu if (divisor == 0) 2485075Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 2495075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 2505075Sgblack@eecs.umich.edu if (divisor <= dividend) { 2515075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 2525075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 2535075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 2545075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 2555075Sgblack@eecs.umich.edu divisor <<= shift; 2565075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 2575075Sgblack@eecs.umich.edu //now larger than the dividend. 2585075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 2595075Sgblack@eecs.umich.edu quotientBit <<= shift; 2605075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2615075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2625075Sgblack@eecs.umich.edu //part of one or two bit division. 2635075Sgblack@eecs.umich.edu if (divisor > dividend) { 2645075Sgblack@eecs.umich.edu quotientBit >>= 1; 2655075Sgblack@eecs.umich.edu divisor >>= 1; 2665075Sgblack@eecs.umich.edu } 2675075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2685075Sgblack@eecs.umich.edu quotient += quotientBit; 2695075Sgblack@eecs.umich.edu remainder -= divisor; 2705075Sgblack@eecs.umich.edu } 2715075Sgblack@eecs.umich.edu } 2725075Sgblack@eecs.umich.edu}}; 2735075Sgblack@eecs.umich.edu 2744519Sgblack@eecs.umich.edulet {{ 2755040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2765040Sgblack@eecs.umich.edu # them will always work. 2775040Sgblack@eecs.umich.edu header_output = "" 2785040Sgblack@eecs.umich.edu decoder_output = "" 2795040Sgblack@eecs.umich.edu exec_output = "" 2805040Sgblack@eecs.umich.edu 2815040Sgblack@eecs.umich.edu immTemplates = ( 2825040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2835040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2845040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2855040Sgblack@eecs.umich.edu 2865040Sgblack@eecs.umich.edu regTemplates = ( 2875040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2885040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2895040Sgblack@eecs.umich.edu MicroRegOpExecute) 2905040Sgblack@eecs.umich.edu 2915040Sgblack@eecs.umich.edu class RegOpMeta(type): 2925040Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 2935040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code): 2945040Sgblack@eecs.umich.edu 2955040Sgblack@eecs.umich.edu # Globals to stick the output in 2965040Sgblack@eecs.umich.edu global header_output 2975040Sgblack@eecs.umich.edu global decoder_output 2985040Sgblack@eecs.umich.edu global exec_output 2995040Sgblack@eecs.umich.edu 3005040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 3015040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3025040Sgblack@eecs.umich.edu 3035040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3045040Sgblack@eecs.umich.edu # of this code. 3055062Sgblack@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 3065062Sgblack@eecs.umich.edu match = matcher.search(allCode) 3075062Sgblack@eecs.umich.edu if match: 3085062Sgblack@eecs.umich.edu typeQual = "" 3095062Sgblack@eecs.umich.edu if match.group("typeQual"): 3105062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 3115062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3125040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3135062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 3145062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 3155062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 3165062Sgblack@eecs.umich.edu matcher.sub(src2_name, else_code)) 3175040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 3185040Sgblack@eecs.umich.edu matcher.sub("imm8", code), 3195040Sgblack@eecs.umich.edu matcher.sub("imm8", flag_code), 3205040Sgblack@eecs.umich.edu matcher.sub("imm8", cond_check), 3215040Sgblack@eecs.umich.edu matcher.sub("imm8", else_code)) 3225040Sgblack@eecs.umich.edu return 3235040Sgblack@eecs.umich.edu 3245040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 3255040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 3265239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 3275040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3285040Sgblack@eecs.umich.edu code, "", "true", else_code) 3295040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 3305040Sgblack@eecs.umich.edu 3315040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 3325040Sgblack@eecs.umich.edu # compute it. 3335040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 3345040Sgblack@eecs.umich.edu if matcher.search(allCode): 3355061Sgblack@eecs.umich.edu code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3365040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 3375040Sgblack@eecs.umich.edu if matcher.search(allCode): 3385061Sgblack@eecs.umich.edu code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3395061Sgblack@eecs.umich.edu # Also make available versions which do sign extension 3405061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3415061Sgblack@eecs.umich.edu if matcher.search(allCode): 3425061Sgblack@eecs.umich.edu code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3435061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3445061Sgblack@eecs.umich.edu if matcher.search(allCode): 3455061Sgblack@eecs.umich.edu code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3465040Sgblack@eecs.umich.edu 3475040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3485040Sgblack@eecs.umich.edu 3495040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3505040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3515040Sgblack@eecs.umich.edu templates = regTemplates 3525040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)imm8(?!\w)") 3535040Sgblack@eecs.umich.edu if matcher.search(allCode): 3545040Sgblack@eecs.umich.edu base += "Imm" 3555040Sgblack@eecs.umich.edu templates = immTemplates 3565040Sgblack@eecs.umich.edu 3575040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3585040Sgblack@eecs.umich.edu iop = InstObjParams(name, Name + suffix, base, 3595040Sgblack@eecs.umich.edu {"code" : code, 3605040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3615040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3625040Sgblack@eecs.umich.edu "else_code" : else_code}) 3635040Sgblack@eecs.umich.edu 3645040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3655040Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3665040Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3675040Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3685040Sgblack@eecs.umich.edu 3695040Sgblack@eecs.umich.edu 3705040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3714688Sgblack@eecs.umich.edu abstract = False 3725040Sgblack@eecs.umich.edu name = Name.lower() 3734688Sgblack@eecs.umich.edu if "abstract" in dict: 3744688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3754688Sgblack@eecs.umich.edu del dict['abstract'] 3764688Sgblack@eecs.umich.edu 3775040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3784688Sgblack@eecs.umich.edu if not abstract: 3795040Sgblack@eecs.umich.edu cls.className = Name 3805040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3815040Sgblack@eecs.umich.edu code = cls.code 3825040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3835040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3845040Sgblack@eecs.umich.edu else_code = cls.else_code 3855040Sgblack@eecs.umich.edu 3865040Sgblack@eecs.umich.edu # Set up the C++ classes 3875040Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", 3885040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code) 3895040Sgblack@eecs.umich.edu 3905040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3915040Sgblack@eecs.umich.edu global microopClasses 3925040Sgblack@eecs.umich.edu microopClasses[name] = cls 3935040Sgblack@eecs.umich.edu 3945040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3955040Sgblack@eecs.umich.edu 3965040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3975040Sgblack@eecs.umich.edu # of this code. 3985040Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3995040Sgblack@eecs.umich.edu if matcher.search(allCode): 4005040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 4014688Sgblack@eecs.umich.edu return cls 4024688Sgblack@eecs.umich.edu 4035040Sgblack@eecs.umich.edu 4045040Sgblack@eecs.umich.edu class RegOp(X86Microop): 4055040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 4065040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 4074688Sgblack@eecs.umich.edu abstract = True 4084688Sgblack@eecs.umich.edu 4095040Sgblack@eecs.umich.edu # Default template parameter values 4105040Sgblack@eecs.umich.edu flag_code = "" 4115040Sgblack@eecs.umich.edu cond_check = "true" 4125040Sgblack@eecs.umich.edu else_code = ";" 4135040Sgblack@eecs.umich.edu 4145040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4154519Sgblack@eecs.umich.edu self.dest = dest 4164519Sgblack@eecs.umich.edu self.src1 = src1 4175040Sgblack@eecs.umich.edu self.op2 = op2 4184688Sgblack@eecs.umich.edu self.flags = flags 4194701Sgblack@eecs.umich.edu self.dataSize = dataSize 4204688Sgblack@eecs.umich.edu if flags is None: 4214688Sgblack@eecs.umich.edu self.ext = 0 4224688Sgblack@eecs.umich.edu else: 4234688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4244688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4254688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 4264688Sgblack@eecs.umich.edu self.className += "Flags" 4274519Sgblack@eecs.umich.edu 4284519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 4295040Sgblack@eecs.umich.edu className = self.className 4305040Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4315040Sgblack@eecs.umich.edu className += "Imm" 4324560Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 4335040Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4344688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4355040Sgblack@eecs.umich.edu "class_name" : className, 4364519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4375040Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4384519Sgblack@eecs.umich.edu "dest" : self.dest, 4394519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4404519Sgblack@eecs.umich.edu "ext" : self.ext} 4414539Sgblack@eecs.umich.edu return allocator 4424519Sgblack@eecs.umich.edu 4435040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4444688Sgblack@eecs.umich.edu abstract = True 4455040Sgblack@eecs.umich.edu flag_code = ''' 4465040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4475115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4485040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4495040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4505040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 4515115Sgblack@eecs.umich.edu ccFlagBits &= ~(ECFBit & ext); 4525040Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 4535040Sgblack@eecs.umich.edu ''' 4544519Sgblack@eecs.umich.edu 4555040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4565040Sgblack@eecs.umich.edu abstract = True 4575040Sgblack@eecs.umich.edu flag_code = \ 4585040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4594519Sgblack@eecs.umich.edu 4605040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4615040Sgblack@eecs.umich.edu abstract = True 4625040Sgblack@eecs.umich.edu flag_code = \ 4635040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4644519Sgblack@eecs.umich.edu 4655040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4665040Sgblack@eecs.umich.edu abstract = True 4675083Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits, ext)" 4684519Sgblack@eecs.umich.edu 4695063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4705063Sgblack@eecs.umich.edu abstract = True 4715063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4725063Sgblack@eecs.umich.edu if not src1: 4735063Sgblack@eecs.umich.edu src1 = dest 4745063Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 4755063Sgblack@eecs.umich.edu 4765063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4775063Sgblack@eecs.umich.edu abstract = True 4785063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4795063Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 4805063Sgblack@eecs.umich.edu 4815040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4825040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4834595Sgblack@eecs.umich.edu 4845040Sgblack@eecs.umich.edu class Or(LogicRegOp): 4855040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4864595Sgblack@eecs.umich.edu 4875040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 4885040Sgblack@eecs.umich.edu code = ''' 4894732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4905138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 4915040Sgblack@eecs.umich.edu ''' 4925040Sgblack@eecs.umich.edu 4935040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 4945040Sgblack@eecs.umich.edu code = ''' 4954732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4965138Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 4975040Sgblack@eecs.umich.edu ''' 4985040Sgblack@eecs.umich.edu 4995040Sgblack@eecs.umich.edu class And(LogicRegOp): 5005040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 5015040Sgblack@eecs.umich.edu 5025040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5035040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 5045040Sgblack@eecs.umich.edu 5055040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5065040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 5075040Sgblack@eecs.umich.edu 5085065Sgblack@eecs.umich.edu # Neither of these is quite correct because it assumes that right shifting 5095065Sgblack@eecs.umich.edu # a signed or unsigned value does sign or zero extension respectively. 5105065Sgblack@eecs.umich.edu # The C standard says that what happens on a right shift with a 1 in the 5115065Sgblack@eecs.umich.edu # MSB position is undefined. On x86 and under likely most compilers the 5125065Sgblack@eecs.umich.edu # "right thing" happens, but this isn't a guarantee. 5135063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5145040Sgblack@eecs.umich.edu code = ''' 5155063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5165063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5175063Sgblack@eecs.umich.edu int64_t spsrc1_h = spsrc1 >> halfSize; 5185063Sgblack@eecs.umich.edu int64_t spsrc1_l = spsrc1 & mask(halfSize); 5195063Sgblack@eecs.umich.edu int64_t spsrc2_h = sop2 >> halfSize; 5205063Sgblack@eecs.umich.edu int64_t spsrc2_l = sop2 & mask(halfSize); 5215063Sgblack@eecs.umich.edu ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l + 5225063Sgblack@eecs.umich.edu ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) + 5235063Sgblack@eecs.umich.edu spsrc1_h * spsrc2_h; 5245040Sgblack@eecs.umich.edu ''' 5255040Sgblack@eecs.umich.edu 5265063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5275040Sgblack@eecs.umich.edu code = ''' 5285063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5294809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5305063Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 >> halfSize; 5315063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5325063Sgblack@eecs.umich.edu uint64_t psrc2_h = op2 >> halfSize; 5335063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5345063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5355063Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) + 5365063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5375040Sgblack@eecs.umich.edu ''' 5385040Sgblack@eecs.umich.edu 5395063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5405063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5415040Sgblack@eecs.umich.edu 5425063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5435063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5445063Sgblack@eecs.umich.edu if not src1: 5455063Sgblack@eecs.umich.edu src1 = dest 5465063Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize) 5475063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5485063Sgblack@eecs.umich.edu flag_code = ''' 5495063Sgblack@eecs.umich.edu if (ProdHi) 5505063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5515063Sgblack@eecs.umich.edu else 5525063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5535063Sgblack@eecs.umich.edu ''' 5545062Sgblack@eecs.umich.edu 5555075Sgblack@eecs.umich.edu # One or two bit divide 5565075Sgblack@eecs.umich.edu class Div1(WrRegOp): 5575040Sgblack@eecs.umich.edu code = ''' 5585075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 5595075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5605075Sgblack@eecs.umich.edu uint64_t quotient = 0; 5615075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 5625075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 5635075Sgblack@eecs.umich.edu //a source. 5645075Sgblack@eecs.umich.edu uint64_t divisor = op2; 5655075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 5665075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 5675075Sgblack@eecs.umich.edu //Do the division. 5685075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5695075Sgblack@eecs.umich.edu //Record the final results. 5705075Sgblack@eecs.umich.edu Remainder = remainder; 5715075Sgblack@eecs.umich.edu Quotient = quotient; 5725075Sgblack@eecs.umich.edu Divisor = divisor; 5735040Sgblack@eecs.umich.edu ''' 5744823Sgblack@eecs.umich.edu 5755075Sgblack@eecs.umich.edu # Step divide 5765075Sgblack@eecs.umich.edu class Div2(RegOp): 5775075Sgblack@eecs.umich.edu code = ''' 5785075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 5795075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 5805075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 5815075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 5825075Sgblack@eecs.umich.edu int remaining = op2; 5835075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 5845075Sgblack@eecs.umich.edu //little. 5855075Sgblack@eecs.umich.edu if (remaining) { 5865075Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 5875075Sgblack@eecs.umich.edu while(dividend < divisor && remaining) { 5885075Sgblack@eecs.umich.edu dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 5895075Sgblack@eecs.umich.edu quotient <<= 1; 5905075Sgblack@eecs.umich.edu remaining--; 5915075Sgblack@eecs.umich.edu } 5925075Sgblack@eecs.umich.edu remainder = dividend; 5935075Sgblack@eecs.umich.edu //Do the division. 5945075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5955075Sgblack@eecs.umich.edu } 5965075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 5975075Sgblack@eecs.umich.edu DestReg = merge(DestReg, remaining, dataSize); 5985075Sgblack@eecs.umich.edu //Record the final results 5995075Sgblack@eecs.umich.edu Remainder = remainder; 6005075Sgblack@eecs.umich.edu Quotient = quotient; 6015075Sgblack@eecs.umich.edu ''' 6025075Sgblack@eecs.umich.edu flag_code = ''' 6035075Sgblack@eecs.umich.edu if (DestReg == 0) 6045075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & EZFBit); 6055075Sgblack@eecs.umich.edu else 6065075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6075075Sgblack@eecs.umich.edu ''' 6084732Sgblack@eecs.umich.edu 6095075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6105075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6115075Sgblack@eecs.umich.edu 6125075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6135075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6145040Sgblack@eecs.umich.edu 6155040Sgblack@eecs.umich.edu class Mov(CondRegOp): 6165040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6175040Sgblack@eecs.umich.edu else_code = 'DestReg=DestReg;' 6185040Sgblack@eecs.umich.edu 6194732Sgblack@eecs.umich.edu # Shift instructions 6205040Sgblack@eecs.umich.edu 6215076Sgblack@eecs.umich.edu class Sll(RegOp): 6225040Sgblack@eecs.umich.edu code = ''' 6234756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6244823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6255040Sgblack@eecs.umich.edu ''' 6265076Sgblack@eecs.umich.edu flag_code = ''' 6275076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6285076Sgblack@eecs.umich.edu if (shiftAmt) { 6295076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6305076Sgblack@eecs.umich.edu //worry about setting them. 6315076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6325076Sgblack@eecs.umich.edu int CFBits = 0; 6335076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 6345076Sgblack@eecs.umich.edu if (bits(SrcReg1, dataSize * 8 - shiftAmt)) 6355076Sgblack@eecs.umich.edu CFBits = 1; 6365076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6375076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 6385076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6395076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6405076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 6415076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6425076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6435076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6445076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6455076Sgblack@eecs.umich.edu } 6465076Sgblack@eecs.umich.edu ''' 6475040Sgblack@eecs.umich.edu 6485076Sgblack@eecs.umich.edu class Srl(RegOp): 6495040Sgblack@eecs.umich.edu code = ''' 6504756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6514732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6524732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 6534732Sgblack@eecs.umich.edu // to be sure they're zero. 6544732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 6554823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 6565040Sgblack@eecs.umich.edu ''' 6575076Sgblack@eecs.umich.edu flag_code = ''' 6585076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6595076Sgblack@eecs.umich.edu if (shiftAmt) { 6605076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6615076Sgblack@eecs.umich.edu //worry about setting them. 6625076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6635076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6645076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 6655076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6665076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6675076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 6685076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6695076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6705076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6715076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6725076Sgblack@eecs.umich.edu } 6735076Sgblack@eecs.umich.edu ''' 6745040Sgblack@eecs.umich.edu 6755076Sgblack@eecs.umich.edu class Sra(RegOp): 6765040Sgblack@eecs.umich.edu code = ''' 6774756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6784732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6794732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 6804732Sgblack@eecs.umich.edu // them manually to be sure. 6814732Sgblack@eecs.umich.edu uint64_t arithMask = 6825032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 6834823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 6845040Sgblack@eecs.umich.edu ''' 6855076Sgblack@eecs.umich.edu flag_code = ''' 6865076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6875076Sgblack@eecs.umich.edu if (shiftAmt) { 6885076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6895076Sgblack@eecs.umich.edu //worry about setting them. 6905076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6915076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6925076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 6935076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6945076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6955076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6965076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6975076Sgblack@eecs.umich.edu } 6985076Sgblack@eecs.umich.edu ''' 6995040Sgblack@eecs.umich.edu 7005076Sgblack@eecs.umich.edu class Ror(RegOp): 7015040Sgblack@eecs.umich.edu code = ''' 7024732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7034756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7044732Sgblack@eecs.umich.edu if(shiftAmt) 7054732Sgblack@eecs.umich.edu { 7064823Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 7074823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 7084732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7094732Sgblack@eecs.umich.edu } 7104732Sgblack@eecs.umich.edu else 7114732Sgblack@eecs.umich.edu DestReg = DestReg; 7125040Sgblack@eecs.umich.edu ''' 7135076Sgblack@eecs.umich.edu flag_code = ''' 7145076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7155076Sgblack@eecs.umich.edu if (shiftAmt) { 7165076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7175076Sgblack@eecs.umich.edu //worry about setting them. 7185076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7195076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 7205076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7215076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 7225076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7235076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && msb) 7245076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7255076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7265076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 7275076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7285076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7295076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7305076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7315076Sgblack@eecs.umich.edu } 7325076Sgblack@eecs.umich.edu ''' 7335040Sgblack@eecs.umich.edu 7345076Sgblack@eecs.umich.edu class Rcr(RegOp): 7355040Sgblack@eecs.umich.edu code = ''' 7364733Sgblack@eecs.umich.edu uint8_t shiftAmt = 7374756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7384733Sgblack@eecs.umich.edu if(shiftAmt) 7394733Sgblack@eecs.umich.edu { 7404733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 7415138Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - shiftAmt); 7424733Sgblack@eecs.umich.edu if(shiftAmt > 1) 7434823Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 7444823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 7454733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7464733Sgblack@eecs.umich.edu } 7474733Sgblack@eecs.umich.edu else 7484733Sgblack@eecs.umich.edu DestReg = DestReg; 7495040Sgblack@eecs.umich.edu ''' 7505076Sgblack@eecs.umich.edu flag_code = ''' 7515076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7525076Sgblack@eecs.umich.edu if (shiftAmt) { 7535076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7545076Sgblack@eecs.umich.edu //worry about setting them. 7555076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7565076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7575076Sgblack@eecs.umich.edu if ((ext & OFBit) && ((ccFlagBits & CFBit) ^ 7585076Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) 7595076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7605076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7615076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 7625076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7635076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7645076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7655076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7665076Sgblack@eecs.umich.edu } 7675076Sgblack@eecs.umich.edu ''' 7685040Sgblack@eecs.umich.edu 7695076Sgblack@eecs.umich.edu class Rol(RegOp): 7705040Sgblack@eecs.umich.edu code = ''' 7714732Sgblack@eecs.umich.edu uint8_t shiftAmt = 7724756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7734732Sgblack@eecs.umich.edu if(shiftAmt) 7744732Sgblack@eecs.umich.edu { 7754823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 7764732Sgblack@eecs.umich.edu uint64_t bottom = 7774823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 7784732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7794732Sgblack@eecs.umich.edu } 7804732Sgblack@eecs.umich.edu else 7814732Sgblack@eecs.umich.edu DestReg = DestReg; 7825040Sgblack@eecs.umich.edu ''' 7835076Sgblack@eecs.umich.edu flag_code = ''' 7845076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7855076Sgblack@eecs.umich.edu if (shiftAmt) { 7865076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7875076Sgblack@eecs.umich.edu //worry about setting them. 7885076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7895076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 7905076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 7915076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7925076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7935076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && lsb) 7945076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7955076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7965076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 7975076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7985076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7995076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8005076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8015076Sgblack@eecs.umich.edu } 8025076Sgblack@eecs.umich.edu ''' 8035040Sgblack@eecs.umich.edu 8045076Sgblack@eecs.umich.edu class Rcl(RegOp): 8055040Sgblack@eecs.umich.edu code = ''' 8064733Sgblack@eecs.umich.edu uint8_t shiftAmt = 8074756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8084733Sgblack@eecs.umich.edu if(shiftAmt) 8094733Sgblack@eecs.umich.edu { 8104733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8114823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 8125138Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (shiftAmt - 1); 8134733Sgblack@eecs.umich.edu if(shiftAmt > 1) 8144733Sgblack@eecs.umich.edu bottom |= 8154823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 8164809Sgblack@eecs.umich.edu dataSize * 8 - shiftAmt + 1); 8174733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8184733Sgblack@eecs.umich.edu } 8194733Sgblack@eecs.umich.edu else 8204733Sgblack@eecs.umich.edu DestReg = DestReg; 8215040Sgblack@eecs.umich.edu ''' 8225076Sgblack@eecs.umich.edu flag_code = ''' 8235076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8245076Sgblack@eecs.umich.edu if (shiftAmt) { 8255076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8265076Sgblack@eecs.umich.edu //worry about setting them. 8275076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8285076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8295076Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt); 8305076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8315076Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 8325076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8335076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8345076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 8355076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8365076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8375076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8385076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8395076Sgblack@eecs.umich.edu } 8405076Sgblack@eecs.umich.edu ''' 8414732Sgblack@eecs.umich.edu 8425040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 8435246Sgblack@eecs.umich.edu code = 'RIP = psrc1 + sop2 + CSBase' 8445040Sgblack@eecs.umich.edu else_code="RIP = RIP;" 8455040Sgblack@eecs.umich.edu 8465040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 8475040Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 8485040Sgblack@eecs.umich.edu 8495426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 8505426Sgblack@eecs.umich.edu code = ''' 8515426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 8525426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 8535426Sgblack@eecs.umich.edu // Get only the user flags 8545426Sgblack@eecs.umich.edu ccFlagBits = newFlags & userFlagMask; 8555426Sgblack@eecs.umich.edu // Get everything else 8565426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 8575426Sgblack@eecs.umich.edu ''' 8585426Sgblack@eecs.umich.edu 8595040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 8605246Sgblack@eecs.umich.edu code = 'DestReg = RIP - CSBase' 8615040Sgblack@eecs.umich.edu 8625040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 8635040Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 8645040Sgblack@eecs.umich.edu 8655426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 8665426Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits | nccFlagBits' 8675426Sgblack@eecs.umich.edu 8685040Sgblack@eecs.umich.edu class Ruflag(RegOp): 8695040Sgblack@eecs.umich.edu code = ''' 8705116Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8); 8714951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 8725011Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 8735011Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 8745040Sgblack@eecs.umich.edu ''' 8755040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 8765040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 8775040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 8785040Sgblack@eecs.umich.edu "NUM_INTREGS", imm, flags, dataSize) 8794732Sgblack@eecs.umich.edu 8805426Sgblack@eecs.umich.edu class Rflag(RegOp): 8815426Sgblack@eecs.umich.edu code = ''' 8825426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 8835426Sgblack@eecs.umich.edu MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 8845426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 8855426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 8865426Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 8875426Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 8885426Sgblack@eecs.umich.edu ''' 8895426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 8905426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 8915426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 8925426Sgblack@eecs.umich.edu "NUM_INTREGS", imm, flags, dataSize) 8935426Sgblack@eecs.umich.edu 8945040Sgblack@eecs.umich.edu class Sext(RegOp): 8955040Sgblack@eecs.umich.edu code = ''' 8964823Sgblack@eecs.umich.edu IntReg val = psrc1; 8975239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 8985239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 8995239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 9005239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 9015007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 9025007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 9035040Sgblack@eecs.umich.edu ''' 9045239Sgblack@eecs.umich.edu flag_code = ''' 9055239Sgblack@eecs.umich.edu if (!sign_bit) 9065239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & 9075239Sgblack@eecs.umich.edu ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 9085239Sgblack@eecs.umich.edu else 9095239Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | 9105239Sgblack@eecs.umich.edu (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 9115239Sgblack@eecs.umich.edu ''' 9124714Sgblack@eecs.umich.edu 9135040Sgblack@eecs.umich.edu class Zext(RegOp): 9145239Sgblack@eecs.umich.edu code = 'DestReg = bits(psrc1, op2, 0);' 9155241Sgblack@eecs.umich.edu 9165296Sgblack@eecs.umich.edu class Rdcr(RegOp): 9175296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9185296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 9195296Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 9205296Sgblack@eecs.umich.edu code = ''' 9215296Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 9225296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 9235296Sgblack@eecs.umich.edu } else { 9245296Sgblack@eecs.umich.edu DestReg = ControlSrc1; 9255296Sgblack@eecs.umich.edu } 9265296Sgblack@eecs.umich.edu ''' 9275296Sgblack@eecs.umich.edu 9285241Sgblack@eecs.umich.edu class Wrcr(RegOp): 9295241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9305241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 9315241Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 9325241Sgblack@eecs.umich.edu code = ''' 9335241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 9345241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 9355241Sgblack@eecs.umich.edu } else { 9365241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 9375241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 9385241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 9395241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 9405241Sgblack@eecs.umich.edu 9415241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 9425241Sgblack@eecs.umich.edu switch(dest) { 9435241Sgblack@eecs.umich.edu case 0: 9445241Sgblack@eecs.umich.edu { 9455241Sgblack@eecs.umich.edu Efer efer = EferOp; 9465241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 9475241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 9485241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 9495241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 9505241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 9515241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 9525241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9535241Sgblack@eecs.umich.edu } 9545241Sgblack@eecs.umich.edu break; 9555241Sgblack@eecs.umich.edu case 2: 9565241Sgblack@eecs.umich.edu break; 9575241Sgblack@eecs.umich.edu case 3: 9585241Sgblack@eecs.umich.edu break; 9595241Sgblack@eecs.umich.edu case 4: 9605241Sgblack@eecs.umich.edu { 9615241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 9625241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 9635241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 9645241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 9655241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9665241Sgblack@eecs.umich.edu } 9675241Sgblack@eecs.umich.edu break; 9685241Sgblack@eecs.umich.edu case 8: 9695241Sgblack@eecs.umich.edu { 9705241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 9715241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9725241Sgblack@eecs.umich.edu } 9735241Sgblack@eecs.umich.edu default: 9745241Sgblack@eecs.umich.edu panic("Unrecognized control register %d.\\n", dest); 9755241Sgblack@eecs.umich.edu } 9765241Sgblack@eecs.umich.edu ControlDest = newVal; 9775241Sgblack@eecs.umich.edu } 9785241Sgblack@eecs.umich.edu ''' 9795290Sgblack@eecs.umich.edu 9805294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 9815672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 9825294Sgblack@eecs.umich.edu abstract = True 9835290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9845294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 9855290Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 9865294Sgblack@eecs.umich.edu 9875294Sgblack@eecs.umich.edu class Wrbase(SegOp): 9885290Sgblack@eecs.umich.edu code = ''' 9895294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 9905290Sgblack@eecs.umich.edu ''' 9915290Sgblack@eecs.umich.edu 9925294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 9935290Sgblack@eecs.umich.edu code = ''' 9945294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 9955294Sgblack@eecs.umich.edu ''' 9965294Sgblack@eecs.umich.edu 9975294Sgblack@eecs.umich.edu class Wrsel(SegOp): 9985294Sgblack@eecs.umich.edu code = ''' 9995294Sgblack@eecs.umich.edu SegSelDest = psrc1; 10005294Sgblack@eecs.umich.edu ''' 10015294Sgblack@eecs.umich.edu 10025294Sgblack@eecs.umich.edu class Rdbase(SegOp): 10035294Sgblack@eecs.umich.edu code = ''' 10045670Sgblack@eecs.umich.edu DestReg = SegBaseSrc1; 10055294Sgblack@eecs.umich.edu ''' 10065294Sgblack@eecs.umich.edu 10075294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 10085294Sgblack@eecs.umich.edu code = ''' 10095294Sgblack@eecs.umich.edu DestReg = SegLimitSrc1; 10105294Sgblack@eecs.umich.edu ''' 10115294Sgblack@eecs.umich.edu 10125427Sgblack@eecs.umich.edu class RdAttr(SegOp): 10135427Sgblack@eecs.umich.edu code = ''' 10145427Sgblack@eecs.umich.edu DestReg = SegAttrSrc1; 10155427Sgblack@eecs.umich.edu ''' 10165427Sgblack@eecs.umich.edu 10175294Sgblack@eecs.umich.edu class Rdsel(SegOp): 10185294Sgblack@eecs.umich.edu code = ''' 10195294Sgblack@eecs.umich.edu DestReg = SegSelSrc1; 10205294Sgblack@eecs.umich.edu ''' 10215294Sgblack@eecs.umich.edu 10225428Sgblack@eecs.umich.edu class Chks(RegOp): 10235428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 10245428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 10255428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 10265428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 10275294Sgblack@eecs.umich.edu code = ''' 10285424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 10295433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 10305433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 10315433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 10325294Sgblack@eecs.umich.edu 10335428Sgblack@eecs.umich.edu switch (imm8) 10345428Sgblack@eecs.umich.edu { 10355428Sgblack@eecs.umich.edu case SegNoCheck: 10365428Sgblack@eecs.umich.edu break; 10375428Sgblack@eecs.umich.edu case SegCSCheck: 10385428Sgblack@eecs.umich.edu panic("CS checks for far calls/jumps not implemented.\\n"); 10395428Sgblack@eecs.umich.edu break; 10405428Sgblack@eecs.umich.edu case SegCallGateCheck: 10415428Sgblack@eecs.umich.edu panic("CS checks for far calls/jumps through call gates" 10425428Sgblack@eecs.umich.edu "not implemented.\\n"); 10435428Sgblack@eecs.umich.edu break; 10445674Sgblack@eecs.umich.edu case SegIntGateCheck: 10455674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 10465674Sgblack@eecs.umich.edu return new GeneralProtection((uint16_t)selector); 10475674Sgblack@eecs.umich.edu } 10485674Sgblack@eecs.umich.edu break; 10495428Sgblack@eecs.umich.edu case SegSSCheck: 10505433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 10515433Sgblack@eecs.umich.edu if (!desc.p) { 10525433Sgblack@eecs.umich.edu //FIXME This needs to also push the selector. 10535433Sgblack@eecs.umich.edu return new StackFault; 10545433Sgblack@eecs.umich.edu } 10555433Sgblack@eecs.umich.edu } else { 10565673Sgblack@eecs.umich.edu if ((m5reg.submode != SixtyFourBitMode || 10575673Sgblack@eecs.umich.edu m5reg.cpl == 3) || 10585433Sgblack@eecs.umich.edu !(desc.s == 1 && 10595433Sgblack@eecs.umich.edu desc.type.codeOrData == 0 && desc.type.w) || 10605433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 10615433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 10625433Sgblack@eecs.umich.edu return new GeneralProtection(psrc1 & 0xFFFF); 10635433Sgblack@eecs.umich.edu } 10645433Sgblack@eecs.umich.edu } 10655428Sgblack@eecs.umich.edu break; 10665428Sgblack@eecs.umich.edu case SegIretCheck: 10675428Sgblack@eecs.umich.edu { 10685433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 10695433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 10705433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 10715433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 10725433Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) 10735428Sgblack@eecs.umich.edu return new GeneralProtection(psrc1 & 0xFFFF); 10745433Sgblack@eecs.umich.edu if (!desc.p) 10755433Sgblack@eecs.umich.edu return new SegmentNotPresent; 10765428Sgblack@eecs.umich.edu break; 10775428Sgblack@eecs.umich.edu } 10785428Sgblack@eecs.umich.edu case SegIntCSCheck: 10795675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 10805675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 10815675Sgblack@eecs.umich.edu return new GeneralProtection(selector); 10825675Sgblack@eecs.umich.edu } 10835675Sgblack@eecs.umich.edu } else { 10845675Sgblack@eecs.umich.edu panic("Interrupt CS checks not implemented " 10855675Sgblack@eecs.umich.edu "in legacy mode.\\n"); 10865675Sgblack@eecs.umich.edu } 10875428Sgblack@eecs.umich.edu break; 10885428Sgblack@eecs.umich.edu default: 10895428Sgblack@eecs.umich.edu panic("Undefined segment check type.\\n"); 10905428Sgblack@eecs.umich.edu } 10915294Sgblack@eecs.umich.edu ''' 10925294Sgblack@eecs.umich.edu flag_code = ''' 10935294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 10945294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 10955424Sgblack@eecs.umich.edu if (!selector.si && !selector.ti) 10965294Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 10975294Sgblack@eecs.umich.edu ''' 10985294Sgblack@eecs.umich.edu 10995294Sgblack@eecs.umich.edu class Wrdh(RegOp): 11005294Sgblack@eecs.umich.edu code = ''' 11015294Sgblack@eecs.umich.edu 11025294Sgblack@eecs.umich.edu ''' 11035294Sgblack@eecs.umich.edu 11045409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 11055409Sgblack@eecs.umich.edu code = ''' 11065409Sgblack@eecs.umich.edu TscOp = psrc1; 11075409Sgblack@eecs.umich.edu ''' 11085409Sgblack@eecs.umich.edu 11095409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 11105409Sgblack@eecs.umich.edu code = ''' 11115409Sgblack@eecs.umich.edu DestReg = TscOp; 11125409Sgblack@eecs.umich.edu ''' 11135409Sgblack@eecs.umich.edu 11145429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 11155429Sgblack@eecs.umich.edu code = ''' 11165429Sgblack@eecs.umich.edu DestReg = M5Reg; 11175429Sgblack@eecs.umich.edu ''' 11185429Sgblack@eecs.umich.edu 11195294Sgblack@eecs.umich.edu class Wrdl(RegOp): 11205294Sgblack@eecs.umich.edu code = ''' 11215294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 11225433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 11235433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 11245433Sgblack@eecs.umich.edu SegAttr attr = 0; 11255433Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 11265433Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 11275433Sgblack@eecs.umich.edu if (!desc.s) { 11285433Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 11295433Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 11305433Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 11315433Sgblack@eecs.umich.edu panic("System segment encountered.\\n"); 11325433Sgblack@eecs.umich.edu } else { 11335433Sgblack@eecs.umich.edu if (!desc.p) 11345433Sgblack@eecs.umich.edu panic("Segment not present.\\n"); 11355433Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 11365433Sgblack@eecs.umich.edu attr.readable = desc.type.r; 11375433Sgblack@eecs.umich.edu attr.longMode = desc.l; 11385433Sgblack@eecs.umich.edu } else { 11395433Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 11405433Sgblack@eecs.umich.edu attr.readable = 1; 11415433Sgblack@eecs.umich.edu attr.writable = desc.type.w; 11425433Sgblack@eecs.umich.edu } 11435433Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 11445433Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 11455433Sgblack@eecs.umich.edu if (desc.g) 11465433Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 11475433Sgblack@eecs.umich.edu SegBaseDest = base; 11485433Sgblack@eecs.umich.edu SegLimitDest = limit; 11495433Sgblack@eecs.umich.edu SegAttrDest = attr; 11505433Sgblack@eecs.umich.edu } 11515433Sgblack@eecs.umich.edu } else { 11525295Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 11535295Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 11545295Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 11555294Sgblack@eecs.umich.edu } 11565290Sgblack@eecs.umich.edu ''' 11574519Sgblack@eecs.umich.edu}}; 1158