regop.isa revision 5424
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// Redistribution and use of this software in source and binary forms, 57087Snate@binkert.org// with or without modification, are permitted provided that the 67087Snate@binkert.org// following conditions are met: 77087Snate@binkert.org// 87087Snate@binkert.org// The software must be used only for Non-Commercial Use which means any 97087Snate@binkert.org// use which is NOT directed to receiving any direct monetary 107087Snate@binkert.org// compensation for, or commercial advantage from such use. Illustrative 117087Snate@binkert.org// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 137087Snate@binkert.org// Illustrative examples of commercial use are distributing products for 147087Snate@binkert.org// commercial advantage and providing services using the software for 157087Snate@binkert.org// commercial advantage. 167087Snate@binkert.org// 177087Snate@binkert.org// If you wish to use this software or functionality therein that may be 187087Snate@binkert.org// covered by patents for commercial use, please contact: 197087Snate@binkert.org// Director of Intellectual Property Licensing 207087Snate@binkert.org// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 227087Snate@binkert.org// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 274519Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 284519Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 294519Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 304519Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 314519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 324519Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 334519Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 344519Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 354519Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504809Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534688Sgblack@eecs.umich.edu// 547969Sgblack@eecs.umich.edu// Authors: Gabe Black 557969Sgblack@eecs.umich.edu 564688Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574688Sgblack@eecs.umich.edu// 584688Sgblack@eecs.umich.edu// RegOp Microop templates 594688Sgblack@eecs.umich.edu// 604688Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614708Sgblack@eecs.umich.edu 624708Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634708Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644708Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684519Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 694519Sgblack@eecs.umich.edu %(op_decl)s; 704519Sgblack@eecs.umich.edu %(op_rd)s; 714519Sgblack@eecs.umich.edu 724519Sgblack@eecs.umich.edu if(%(cond_check)s) 734519Sgblack@eecs.umich.edu { 744519Sgblack@eecs.umich.edu %(code)s; 754519Sgblack@eecs.umich.edu %(flag_code)s; 764951Sgblack@eecs.umich.edu } 774519Sgblack@eecs.umich.edu else 784519Sgblack@eecs.umich.edu { 794519Sgblack@eecs.umich.edu %(else_code)s; 804519Sgblack@eecs.umich.edu } 814519Sgblack@eecs.umich.edu 824519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 834688Sgblack@eecs.umich.edu if(fault == NoFault) 847969Sgblack@eecs.umich.edu { 857969Sgblack@eecs.umich.edu %(op_wb)s; 864688Sgblack@eecs.umich.edu } 874688Sgblack@eecs.umich.edu return fault; 884688Sgblack@eecs.umich.edu } 894688Sgblack@eecs.umich.edu}}; 904688Sgblack@eecs.umich.edu 914708Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 924708Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 934708Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 944708Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu Fault fault = NoFault; 964519Sgblack@eecs.umich.edu 974519Sgblack@eecs.umich.edu %(op_decl)s; 984519Sgblack@eecs.umich.edu %(op_rd)s; 994519Sgblack@eecs.umich.edu 1004519Sgblack@eecs.umich.edu if(%(cond_check)s) 1014519Sgblack@eecs.umich.edu { 1024519Sgblack@eecs.umich.edu %(code)s; 1034519Sgblack@eecs.umich.edu %(flag_code)s; 1044519Sgblack@eecs.umich.edu } 1054519Sgblack@eecs.umich.edu else 1064519Sgblack@eecs.umich.edu { 1074519Sgblack@eecs.umich.edu %(else_code)s; 1084519Sgblack@eecs.umich.edu } 1094519Sgblack@eecs.umich.edu 1107620Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1116345Sgblack@eecs.umich.edu if(fault == NoFault) 1124712Sgblack@eecs.umich.edu { 1134519Sgblack@eecs.umich.edu %(op_wb)s; 1144519Sgblack@eecs.umich.edu } 1154519Sgblack@eecs.umich.edu return fault; 1164519Sgblack@eecs.umich.edu } 1174519Sgblack@eecs.umich.edu}}; 1184519Sgblack@eecs.umich.edu 1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1204951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu protected: 1234951Sgblack@eecs.umich.edu void buildMe(); 1247620Sgblack@eecs.umich.edu 1256646Sgblack@eecs.umich.edu public: 1264712Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1274519Sgblack@eecs.umich.edu const char * instMnem, 1284519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1294519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1304519Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1334519Sgblack@eecs.umich.edu const char * instMnem, 1347620Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1356345Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1364712Sgblack@eecs.umich.edu 1377620Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1384688Sgblack@eecs.umich.edu }; 1394581Sgblack@eecs.umich.edu}}; 1404519Sgblack@eecs.umich.edu 1417626Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1427894SBrad.Beckmann@amd.com 1434519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1444519Sgblack@eecs.umich.edu { 1454519Sgblack@eecs.umich.edu protected: 1464519Sgblack@eecs.umich.edu void buildMe(); 1474951Sgblack@eecs.umich.edu 1487620Sgblack@eecs.umich.edu public: 1496646Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1504712Sgblack@eecs.umich.edu const char * instMnem, 1517620Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1524688Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1534581Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1544519Sgblack@eecs.umich.edu 1557626Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1567894SBrad.Beckmann@amd.com const char * instMnem, 1574519Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1584519Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1594519Sgblack@eecs.umich.edu 1605075Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1615075Sgblack@eecs.umich.edu }; 1625075Sgblack@eecs.umich.edu}}; 1635075Sgblack@eecs.umich.edu 1645428Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1655428Sgblack@eecs.umich.edu 1665674Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1675899Sgblack@eecs.umich.edu { 1685936Sgblack@eecs.umich.edu %(constructor)s; 1695428Sgblack@eecs.umich.edu } 1705678Sgblack@eecs.umich.edu 1715678Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1725678Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1735678Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1745678Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1755678Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1765678Sgblack@eecs.umich.edu false, false, false, false, 1775678Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1785678Sgblack@eecs.umich.edu %(op_class)s) 1795075Sgblack@eecs.umich.edu { 1805075Sgblack@eecs.umich.edu buildMe(); 1815075Sgblack@eecs.umich.edu } 1825075Sgblack@eecs.umich.edu 1835075Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1845075Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1855075Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1865075Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1877719Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1885075Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1895075Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1905075Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1915075Sgblack@eecs.umich.edu %(op_class)s) 1925075Sgblack@eecs.umich.edu { 1935075Sgblack@eecs.umich.edu buildMe(); 1945075Sgblack@eecs.umich.edu } 1955075Sgblack@eecs.umich.edu}}; 1965075Sgblack@eecs.umich.edu 1975075Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1985075Sgblack@eecs.umich.edu 1995075Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 2005075Sgblack@eecs.umich.edu { 2015075Sgblack@eecs.umich.edu %(constructor)s; 2025075Sgblack@eecs.umich.edu } 2035075Sgblack@eecs.umich.edu 2045075Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2055075Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2065075Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2075075Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2085075Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2095075Sgblack@eecs.umich.edu false, false, false, false, 2105075Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2115075Sgblack@eecs.umich.edu %(op_class)s) 2125075Sgblack@eecs.umich.edu { 2134519Sgblack@eecs.umich.edu buildMe(); 2145040Sgblack@eecs.umich.edu } 2155040Sgblack@eecs.umich.edu 2165040Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2175040Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2185040Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2195040Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2205040Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2215040Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2225040Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2235040Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2245040Sgblack@eecs.umich.edu %(op_class)s) 2255040Sgblack@eecs.umich.edu { 2265040Sgblack@eecs.umich.edu buildMe(); 2275040Sgblack@eecs.umich.edu } 2285040Sgblack@eecs.umich.edu}}; 2295040Sgblack@eecs.umich.edu 2305040Sgblack@eecs.umich.eduoutput header {{ 2317967Sgblack@eecs.umich.edu void 2327967Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2335040Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 2345040Sgblack@eecs.umich.edu}}; 2355040Sgblack@eecs.umich.edu 2365040Sgblack@eecs.umich.eduoutput decoder {{ 2375040Sgblack@eecs.umich.edu void 2385040Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2395040Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 2407894SBrad.Beckmann@amd.com { 2417894SBrad.Beckmann@amd.com //Check for divide by zero. 2427967Sgblack@eecs.umich.edu if (divisor == 0) 2437967Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 2445040Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 2455040Sgblack@eecs.umich.edu if (divisor <= dividend) { 2465040Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 2478588Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 2487967Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 2495062Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 2505062Sgblack@eecs.umich.edu divisor <<= shift; 2515062Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 2525062Sgblack@eecs.umich.edu //now larger than the dividend. 2535062Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 2545040Sgblack@eecs.umich.edu quotientBit <<= shift; 2555062Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2567967Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2575062Sgblack@eecs.umich.edu //part of one or two bit division. 2585062Sgblack@eecs.umich.edu if (divisor > dividend) { 2597894SBrad.Beckmann@amd.com quotientBit >>= 1; 2607894SBrad.Beckmann@amd.com divisor >>= 1; 2616647Sgblack@eecs.umich.edu } 2625040Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2636647Sgblack@eecs.umich.edu quotient += quotientBit; 2647967Sgblack@eecs.umich.edu remainder -= divisor; 2656647Sgblack@eecs.umich.edu } 2666647Sgblack@eecs.umich.edu } 2677894SBrad.Beckmann@amd.com}}; 2687894SBrad.Beckmann@amd.com 2695040Sgblack@eecs.umich.edulet {{ 2705040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2715040Sgblack@eecs.umich.edu # them will always work. 2725040Sgblack@eecs.umich.edu header_output = "" 2735239Sgblack@eecs.umich.edu decoder_output = "" 2745040Sgblack@eecs.umich.edu exec_output = "" 2757967Sgblack@eecs.umich.edu 2765040Sgblack@eecs.umich.edu immTemplates = ( 2775040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2785040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2795040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2807967Sgblack@eecs.umich.edu 2817967Sgblack@eecs.umich.edu regTemplates = ( 2827967Sgblack@eecs.umich.edu MicroRegOpDeclare, 2837967Sgblack@eecs.umich.edu MicroRegOpConstructor, 2847967Sgblack@eecs.umich.edu MicroRegOpExecute) 2857967Sgblack@eecs.umich.edu 2867967Sgblack@eecs.umich.edu class RegOpMeta(type): 2877967Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 2887967Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code): 2897967Sgblack@eecs.umich.edu 2907967Sgblack@eecs.umich.edu # Globals to stick the output in 2917967Sgblack@eecs.umich.edu global header_output 2927967Sgblack@eecs.umich.edu global decoder_output 2937967Sgblack@eecs.umich.edu global exec_output 2947967Sgblack@eecs.umich.edu 2957967Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2967967Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 2977967Sgblack@eecs.umich.edu 2987967Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2997967Sgblack@eecs.umich.edu # of this code. 3007967Sgblack@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 3015040Sgblack@eecs.umich.edu match = matcher.search(allCode) 3025040Sgblack@eecs.umich.edu if match: 3035040Sgblack@eecs.umich.edu typeQual = "" 3045040Sgblack@eecs.umich.edu if match.group("typeQual"): 3055040Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 3065040Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3076647Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3085040Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 3095040Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 3105040Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 3115040Sgblack@eecs.umich.edu matcher.sub(src2_name, else_code)) 3125040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 3137967Sgblack@eecs.umich.edu matcher.sub("imm8", code), 3145040Sgblack@eecs.umich.edu matcher.sub("imm8", flag_code), 3155040Sgblack@eecs.umich.edu matcher.sub("imm8", cond_check), 3165040Sgblack@eecs.umich.edu matcher.sub("imm8", else_code)) 3177894SBrad.Beckmann@amd.com return 3187967Sgblack@eecs.umich.edu 3197967Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 3207967Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 3217967Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 3227967Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3237967Sgblack@eecs.umich.edu code, "", "true", else_code) 3247967Sgblack@eecs.umich.edu suffix = "Flags" + suffix 3257967Sgblack@eecs.umich.edu 3267967Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 3275040Sgblack@eecs.umich.edu # compute it. 3285040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 3297967Sgblack@eecs.umich.edu if matcher.search(allCode): 3307967Sgblack@eecs.umich.edu code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3317967Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 3327967Sgblack@eecs.umich.edu if matcher.search(allCode): 3335040Sgblack@eecs.umich.edu code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3345040Sgblack@eecs.umich.edu # Also make available versions which do sign extension 3355040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3364688Sgblack@eecs.umich.edu if matcher.search(allCode): 3375040Sgblack@eecs.umich.edu code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3384688Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3394688Sgblack@eecs.umich.edu if matcher.search(allCode): 3404688Sgblack@eecs.umich.edu code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3414688Sgblack@eecs.umich.edu 3425040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3434688Sgblack@eecs.umich.edu 3445040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3455040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3465040Sgblack@eecs.umich.edu templates = regTemplates 3477967Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)imm8(?!\w)") 3485040Sgblack@eecs.umich.edu if matcher.search(allCode): 3495040Sgblack@eecs.umich.edu base += "Imm" 3505040Sgblack@eecs.umich.edu templates = immTemplates 3517894SBrad.Beckmann@amd.com 3525040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3535040Sgblack@eecs.umich.edu iop = InstObjParams(name, Name + suffix, base, 3547967Sgblack@eecs.umich.edu {"code" : code, 3557967Sgblack@eecs.umich.edu "flag_code" : flag_code, 3567967Sgblack@eecs.umich.edu "cond_check" : cond_check, 3575040Sgblack@eecs.umich.edu "else_code" : else_code}) 3585040Sgblack@eecs.umich.edu 3595040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3605040Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3615040Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3627894SBrad.Beckmann@amd.com exec_output += templates[2].subst(iop) 3637894SBrad.Beckmann@amd.com 3645040Sgblack@eecs.umich.edu 3655040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3665040Sgblack@eecs.umich.edu abstract = False 3678588Sgblack@eecs.umich.edu name = Name.lower() 3685040Sgblack@eecs.umich.edu if "abstract" in dict: 3695040Sgblack@eecs.umich.edu abstract = dict['abstract'] 3704688Sgblack@eecs.umich.edu del dict['abstract'] 3714688Sgblack@eecs.umich.edu 3725040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3735040Sgblack@eecs.umich.edu if not abstract: 3745040Sgblack@eecs.umich.edu cls.className = Name 3755040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3764688Sgblack@eecs.umich.edu code = cls.code 3774688Sgblack@eecs.umich.edu flag_code = cls.flag_code 3785040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3797967Sgblack@eecs.umich.edu else_code = cls.else_code 3805040Sgblack@eecs.umich.edu 3815040Sgblack@eecs.umich.edu # Set up the C++ classes 3825040Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", 3837894SBrad.Beckmann@amd.com code, flag_code, cond_check, else_code) 3845040Sgblack@eecs.umich.edu 3855040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3864519Sgblack@eecs.umich.edu global microopClasses 3874519Sgblack@eecs.umich.edu microopClasses[name] = cls 3885040Sgblack@eecs.umich.edu 3894688Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3904701Sgblack@eecs.umich.edu 3914688Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3924688Sgblack@eecs.umich.edu # of this code. 3934688Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3944688Sgblack@eecs.umich.edu if matcher.search(allCode): 3954688Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3964688Sgblack@eecs.umich.edu return cls 3974688Sgblack@eecs.umich.edu 3984519Sgblack@eecs.umich.edu 3997620Sgblack@eecs.umich.edu class RegOp(X86Microop): 4007967Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 4017967Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 4027967Sgblack@eecs.umich.edu abstract = True 4037967Sgblack@eecs.umich.edu 4047967Sgblack@eecs.umich.edu # Default template parameter values 4057967Sgblack@eecs.umich.edu flag_code = "" 4067967Sgblack@eecs.umich.edu cond_check = "true" 4077967Sgblack@eecs.umich.edu else_code = ";" 4087967Sgblack@eecs.umich.edu 4097967Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4107967Sgblack@eecs.umich.edu self.dest = dest 4117967Sgblack@eecs.umich.edu self.src1 = src1 4127967Sgblack@eecs.umich.edu self.op2 = op2 4137967Sgblack@eecs.umich.edu self.flags = flags 4147967Sgblack@eecs.umich.edu self.dataSize = dataSize 4157967Sgblack@eecs.umich.edu if flags is None: 4167967Sgblack@eecs.umich.edu self.ext = 0 4177967Sgblack@eecs.umich.edu else: 4187967Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4197967Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4207967Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 4217967Sgblack@eecs.umich.edu self.className += "Flags" 4227967Sgblack@eecs.umich.edu 4237967Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 4247967Sgblack@eecs.umich.edu className = self.className 4257967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4267967Sgblack@eecs.umich.edu className += "Imm" 4277967Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 4287967Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4297967Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4307967Sgblack@eecs.umich.edu "class_name" : className, 4317967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4327967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4337967Sgblack@eecs.umich.edu "dest" : self.dest, 4347967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4354519Sgblack@eecs.umich.edu "ext" : self.ext} 4365040Sgblack@eecs.umich.edu return allocator 4374688Sgblack@eecs.umich.edu 4385040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4395040Sgblack@eecs.umich.edu abstract = True 4405115Sgblack@eecs.umich.edu flag_code = ''' 4417969Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4425040Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4435040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4445115Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4455040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 4465040Sgblack@eecs.umich.edu ccFlagBits &= ~(ECFBit & ext); 4474519Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 4485040Sgblack@eecs.umich.edu ''' 4495040Sgblack@eecs.umich.edu 4505040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4517969Sgblack@eecs.umich.edu abstract = True 4524519Sgblack@eecs.umich.edu flag_code = \ 4535040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4545040Sgblack@eecs.umich.edu 4555040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4567969Sgblack@eecs.umich.edu abstract = True 4574519Sgblack@eecs.umich.edu flag_code = \ 4585040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4595040Sgblack@eecs.umich.edu 4605083Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4617894SBrad.Beckmann@amd.com abstract = True 4624519Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits, ext)" 4635063Sgblack@eecs.umich.edu 4645063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4655063Sgblack@eecs.umich.edu abstract = True 4665063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4675063Sgblack@eecs.umich.edu if not src1: 4686345Sgblack@eecs.umich.edu src1 = dest 4696345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 4705063Sgblack@eecs.umich.edu 4715063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4725063Sgblack@eecs.umich.edu abstract = True 4735063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4746345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 4756345Sgblack@eecs.umich.edu 4765063Sgblack@eecs.umich.edu class Add(FlagRegOp): 4775040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4787969Sgblack@eecs.umich.edu 4797969Sgblack@eecs.umich.edu class Or(LogicRegOp): 4804595Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4815040Sgblack@eecs.umich.edu 4827969Sgblack@eecs.umich.edu class Adc(FlagRegOp): 4837969Sgblack@eecs.umich.edu code = ''' 4844595Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4855040Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 4865040Sgblack@eecs.umich.edu ''' 4874732Sgblack@eecs.umich.edu 4887969Sgblack@eecs.umich.edu class Sbb(SubRegOp): 4895040Sgblack@eecs.umich.edu code = ''' 4907967Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4917967Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 4927969Sgblack@eecs.umich.edu ''' 4937967Sgblack@eecs.umich.edu 4945040Sgblack@eecs.umich.edu class And(LogicRegOp): 4955040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 4965040Sgblack@eecs.umich.edu 4974732Sgblack@eecs.umich.edu class Sub(SubRegOp): 4987969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 4995040Sgblack@eecs.umich.edu 5007967Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5017967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 5027969Sgblack@eecs.umich.edu 5037967Sgblack@eecs.umich.edu # Neither of these is quite correct because it assumes that right shifting 5045040Sgblack@eecs.umich.edu # a signed or unsigned value does sign or zero extension respectively. 5055040Sgblack@eecs.umich.edu # The C standard says that what happens on a right shift with a 1 in the 5067969Sgblack@eecs.umich.edu # MSB position is undefined. On x86 and under likely most compilers the 5077969Sgblack@eecs.umich.edu # "right thing" happens, but this isn't a guarantee. 5085040Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5095040Sgblack@eecs.umich.edu code = ''' 5107969Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5117969Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5125040Sgblack@eecs.umich.edu int64_t spsrc1_h = spsrc1 >> halfSize; 5135040Sgblack@eecs.umich.edu int64_t spsrc1_l = spsrc1 & mask(halfSize); 5147969Sgblack@eecs.umich.edu int64_t spsrc2_h = sop2 >> halfSize; 5157969Sgblack@eecs.umich.edu int64_t spsrc2_l = sop2 & mask(halfSize); 5165040Sgblack@eecs.umich.edu ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l + 5175063Sgblack@eecs.umich.edu ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) + 5185040Sgblack@eecs.umich.edu spsrc1_h * spsrc2_h; 5195063Sgblack@eecs.umich.edu ''' 5205063Sgblack@eecs.umich.edu 5216742Svince@csl.cornell.edu class Mul1u(WrRegOp): 5226430Sgblack@eecs.umich.edu code = ''' 5236430Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5246430Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5256461Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 >> halfSize; 5266430Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5276430Sgblack@eecs.umich.edu uint64_t psrc2_h = op2 >> halfSize; 5286430Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5296430Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5306462Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) + 5316430Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5326462Sgblack@eecs.umich.edu ''' 5336430Sgblack@eecs.umich.edu 5346430Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5355040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5366463Sgblack@eecs.umich.edu 5376463Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5386463Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5396463Sgblack@eecs.umich.edu if not src1: 5406463Sgblack@eecs.umich.edu src1 = dest 5416463Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize) 5426463Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5436463Sgblack@eecs.umich.edu flag_code = ''' 5445040Sgblack@eecs.umich.edu if (ProdHi) 5455063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5465040Sgblack@eecs.umich.edu else 5475063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5484809Sgblack@eecs.umich.edu ''' 5496742Svince@csl.cornell.edu 5506430Sgblack@eecs.umich.edu # One or two bit divide 5515063Sgblack@eecs.umich.edu class Div1(WrRegOp): 5526461Sgblack@eecs.umich.edu code = ''' 5535063Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 5545063Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5556430Sgblack@eecs.umich.edu uint64_t quotient = 0; 5565063Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 5575040Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 5586463Sgblack@eecs.umich.edu //a source. 5596463Sgblack@eecs.umich.edu uint64_t divisor = op2; 5606463Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 5616463Sgblack@eecs.umich.edu uint64_t dividend = remainder; 5626463Sgblack@eecs.umich.edu //Do the division. 5636463Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5646463Sgblack@eecs.umich.edu //Record the final results. 5655040Sgblack@eecs.umich.edu Remainder = remainder; 5665063Sgblack@eecs.umich.edu Quotient = quotient; 5675063Sgblack@eecs.umich.edu Divisor = divisor; 5687967Sgblack@eecs.umich.edu ''' 5695040Sgblack@eecs.umich.edu 5705063Sgblack@eecs.umich.edu # Step divide 5715063Sgblack@eecs.umich.edu class Div2(RegOp): 5725063Sgblack@eecs.umich.edu code = ''' 5735063Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 5746345Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 5756345Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 5765063Sgblack@eecs.umich.edu uint64_t remainder = dividend; 5777967Sgblack@eecs.umich.edu int remaining = op2; 5785062Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 5795075Sgblack@eecs.umich.edu //little. 5805075Sgblack@eecs.umich.edu if (remaining) { 5815040Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 5825075Sgblack@eecs.umich.edu while(dividend < divisor && remaining) { 5835075Sgblack@eecs.umich.edu dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 5845075Sgblack@eecs.umich.edu quotient <<= 1; 5855075Sgblack@eecs.umich.edu remaining--; 5865075Sgblack@eecs.umich.edu } 5875075Sgblack@eecs.umich.edu remainder = dividend; 5885075Sgblack@eecs.umich.edu //Do the division. 5895075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5905075Sgblack@eecs.umich.edu } 5915075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 5927719Sgblack@eecs.umich.edu DestReg = merge(DestReg, remaining, dataSize); 5937719Sgblack@eecs.umich.edu //Record the final results 5947719Sgblack@eecs.umich.edu Remainder = remainder; 5957719Sgblack@eecs.umich.edu Quotient = quotient; 5967719Sgblack@eecs.umich.edu ''' 5977719Sgblack@eecs.umich.edu flag_code = ''' 5987719Sgblack@eecs.umich.edu if (DestReg == 0) 5997719Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & EZFBit); 6007719Sgblack@eecs.umich.edu else 6015040Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6024823Sgblack@eecs.umich.edu ''' 6035075Sgblack@eecs.umich.edu 6045075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6057967Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6065075Sgblack@eecs.umich.edu 6075075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6085075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6095075Sgblack@eecs.umich.edu 6105075Sgblack@eecs.umich.edu class Mov(CondRegOp): 6115075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6125075Sgblack@eecs.umich.edu else_code = 'DestReg=DestReg;' 6137719Sgblack@eecs.umich.edu 6147719Sgblack@eecs.umich.edu # Shift instructions 6157719Sgblack@eecs.umich.edu 6167070Sgblack@eecs.umich.edu class Sll(RegOp): 6177070Sgblack@eecs.umich.edu code = ''' 6187070Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6197070Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6207070Sgblack@eecs.umich.edu ''' 6217070Sgblack@eecs.umich.edu flag_code = ''' 6227070Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6237070Sgblack@eecs.umich.edu if (shiftAmt) { 6247080Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6257070Sgblack@eecs.umich.edu //worry about setting them. 6267080Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6277070Sgblack@eecs.umich.edu int CFBits = 0; 6287070Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 6297070Sgblack@eecs.umich.edu if (bits(SrcReg1, dataSize * 8 - shiftAmt)) 6307070Sgblack@eecs.umich.edu CFBits = 1; 6317070Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6327080Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 6337080Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6347080Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6357080Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 6367070Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6377070Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6387070Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6397070Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6407070Sgblack@eecs.umich.edu } 6417070Sgblack@eecs.umich.edu ''' 6427070Sgblack@eecs.umich.edu 6437070Sgblack@eecs.umich.edu class Srl(RegOp): 6447070Sgblack@eecs.umich.edu code = ''' 6457070Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6467070Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6477070Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 6487070Sgblack@eecs.umich.edu // to be sure they're zero. 6495075Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 6505075Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 6515075Sgblack@eecs.umich.edu ''' 6527967Sgblack@eecs.umich.edu flag_code = ''' 6535075Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6545075Sgblack@eecs.umich.edu if (shiftAmt) { 6555075Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6565075Sgblack@eecs.umich.edu //worry about setting them. 6577967Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6587967Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6595075Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 6607480Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6615075Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 6625075Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 6635075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 6645075Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6654732Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6665075Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6675075Sgblack@eecs.umich.edu } 6687967Sgblack@eecs.umich.edu ''' 6695075Sgblack@eecs.umich.edu 6705075Sgblack@eecs.umich.edu class Sra(RegOp): 6715075Sgblack@eecs.umich.edu code = ''' 6727967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6735040Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6745040Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 6755040Sgblack@eecs.umich.edu // them manually to be sure. 6766482Sgblack@eecs.umich.edu uint64_t arithMask = 6775040Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 6784732Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 6795040Sgblack@eecs.umich.edu ''' 6805076Sgblack@eecs.umich.edu flag_code = ''' 6815040Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 6824756Sgblack@eecs.umich.edu if (shiftAmt) { 6834823Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6845040Sgblack@eecs.umich.edu //worry about setting them. 6857967Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6867967Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 6877967Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 6887967Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6895076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 6905076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6915076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 6925076Sgblack@eecs.umich.edu } 6935076Sgblack@eecs.umich.edu ''' 6945076Sgblack@eecs.umich.edu 6955076Sgblack@eecs.umich.edu class Ror(RegOp): 6965076Sgblack@eecs.umich.edu code = ''' 6976441Sgblack@eecs.umich.edu uint8_t shiftAmt = 6986441Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6995076Sgblack@eecs.umich.edu if(shiftAmt) 7006441Sgblack@eecs.umich.edu { 7015076Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 7025076Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 7035076Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7045076Sgblack@eecs.umich.edu } 7055076Sgblack@eecs.umich.edu else 7065076Sgblack@eecs.umich.edu DestReg = DestReg; 7075076Sgblack@eecs.umich.edu ''' 7085076Sgblack@eecs.umich.edu flag_code = ''' 7095076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7105076Sgblack@eecs.umich.edu if (shiftAmt) { 7115076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7125040Sgblack@eecs.umich.edu //worry about setting them. 7135076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7147967Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 7157967Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7167967Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 7175040Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7184756Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && msb) 7194732Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7204823Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7215040Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 7227967Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7237967Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7247967Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7257967Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7267967Sgblack@eecs.umich.edu } 7275076Sgblack@eecs.umich.edu ''' 7285076Sgblack@eecs.umich.edu 7295076Sgblack@eecs.umich.edu class Rcr(RegOp): 7305076Sgblack@eecs.umich.edu code = ''' 7315076Sgblack@eecs.umich.edu uint8_t shiftAmt = 7325076Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7335076Sgblack@eecs.umich.edu if(shiftAmt) 7346442Sgblack@eecs.umich.edu { 7356442Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 7366442Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - shiftAmt); 7375076Sgblack@eecs.umich.edu if(shiftAmt > 1) 7386442Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 7395076Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 7405076Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7415076Sgblack@eecs.umich.edu } 7425076Sgblack@eecs.umich.edu else 7435076Sgblack@eecs.umich.edu DestReg = DestReg; 7445076Sgblack@eecs.umich.edu ''' 7455076Sgblack@eecs.umich.edu flag_code = ''' 7465076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7475040Sgblack@eecs.umich.edu if (shiftAmt) { 7485076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7497967Sgblack@eecs.umich.edu //worry about setting them. 7507967Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7517967Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7525040Sgblack@eecs.umich.edu if ((ext & OFBit) && ((ccFlagBits & CFBit) ^ 7534756Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) 7546443Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7555032Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7564823Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 7575040Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7587967Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7597967Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7607967Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7617967Sgblack@eecs.umich.edu } 7627967Sgblack@eecs.umich.edu ''' 7637967Sgblack@eecs.umich.edu 7645076Sgblack@eecs.umich.edu class Rol(RegOp): 7655076Sgblack@eecs.umich.edu code = ''' 7665076Sgblack@eecs.umich.edu uint8_t shiftAmt = 7675076Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7685076Sgblack@eecs.umich.edu if(shiftAmt) 7695076Sgblack@eecs.umich.edu { 7705076Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 7716444Sgblack@eecs.umich.edu uint64_t bottom = 7726444Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 7736444Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7746444Sgblack@eecs.umich.edu } 7755076Sgblack@eecs.umich.edu else 7766444Sgblack@eecs.umich.edu DestReg = DestReg; 7775076Sgblack@eecs.umich.edu ''' 7785076Sgblack@eecs.umich.edu flag_code = ''' 7795076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7805076Sgblack@eecs.umich.edu if (shiftAmt) { 7815076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7825040Sgblack@eecs.umich.edu //worry about setting them. 7835076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 7845040Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 7854732Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 7864756Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 7876449Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7887967Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && lsb) 7896449Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 7906449Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7914732Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 7927967Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 7936447Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7945040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 7955076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 7965076Sgblack@eecs.umich.edu } 7975076Sgblack@eecs.umich.edu ''' 7985076Sgblack@eecs.umich.edu 7995076Sgblack@eecs.umich.edu class Rcl(RegOp): 8005076Sgblack@eecs.umich.edu code = ''' 8015076Sgblack@eecs.umich.edu uint8_t shiftAmt = 8025076Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8035076Sgblack@eecs.umich.edu if(shiftAmt) 8045076Sgblack@eecs.umich.edu { 8055076Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 8065076Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 8075076Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (shiftAmt - 1); 8085076Sgblack@eecs.umich.edu if(shiftAmt > 1) 8095076Sgblack@eecs.umich.edu bottom |= 8105076Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 8115076Sgblack@eecs.umich.edu dataSize * 8 - shiftAmt + 1); 8125076Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8135076Sgblack@eecs.umich.edu } 8145076Sgblack@eecs.umich.edu else 8155040Sgblack@eecs.umich.edu DestReg = DestReg; 8165076Sgblack@eecs.umich.edu ''' 8175040Sgblack@eecs.umich.edu flag_code = ''' 8184733Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8194756Sgblack@eecs.umich.edu if (shiftAmt) { 8206454Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8217967Sgblack@eecs.umich.edu //worry about setting them. 8224733Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 8236454Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8246454Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt); 8256454Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8266454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && CFBits) 8274733Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 8287967Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8296447Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 8305040Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | OFBit; 8315076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8325076Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 8335076Sgblack@eecs.umich.edu DestReg, psrc1, op2); 8346453Sgblack@eecs.umich.edu } 8355076Sgblack@eecs.umich.edu ''' 8365076Sgblack@eecs.umich.edu 8375076Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 8385076Sgblack@eecs.umich.edu code = 'RIP = psrc1 + sop2 + CSBase' 8396453Sgblack@eecs.umich.edu else_code="RIP = RIP;" 8406453Sgblack@eecs.umich.edu 8415076Sgblack@eecs.umich.edu class Br(WrRegOp, CondRegOp): 8426453Sgblack@eecs.umich.edu code = 'nuIP = psrc1 + op2;' 8435076Sgblack@eecs.umich.edu else_code='nuIP = nuIP;' 8446454Sgblack@eecs.umich.edu 8456454Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 8466454Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 8475076Sgblack@eecs.umich.edu 8486454Sgblack@eecs.umich.edu class Rdip(RdRegOp): 8495076Sgblack@eecs.umich.edu code = 'DestReg = RIP - CSBase' 8505076Sgblack@eecs.umich.edu 8515076Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 8525076Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 8535076Sgblack@eecs.umich.edu 8545040Sgblack@eecs.umich.edu class Ruflag(RegOp): 8555076Sgblack@eecs.umich.edu code = ''' 8565040Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8); 8574732Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 8584756Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 8596446Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 8607967Sgblack@eecs.umich.edu ''' 8616446Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 8624732Sgblack@eecs.umich.edu dataSize="env.dataSize"): 8636446Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 8644732Sgblack@eecs.umich.edu "NUM_INTREGS", imm, flags, dataSize) 8657967Sgblack@eecs.umich.edu 8666447Sgblack@eecs.umich.edu class Sext(RegOp): 8675040Sgblack@eecs.umich.edu code = ''' 8685076Sgblack@eecs.umich.edu IntReg val = psrc1; 8695076Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 8705076Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 8715076Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 8725076Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 8735076Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 8745076Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 8755076Sgblack@eecs.umich.edu ''' 8765076Sgblack@eecs.umich.edu flag_code = ''' 8775076Sgblack@eecs.umich.edu if (!sign_bit) 8785076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & 8795076Sgblack@eecs.umich.edu ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 8805076Sgblack@eecs.umich.edu else 8815076Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | 8825076Sgblack@eecs.umich.edu (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 8835076Sgblack@eecs.umich.edu ''' 8845076Sgblack@eecs.umich.edu 8855076Sgblack@eecs.umich.edu class Zext(RegOp): 8865076Sgblack@eecs.umich.edu code = 'DestReg = bits(psrc1, op2, 0);' 8875076Sgblack@eecs.umich.edu 8885040Sgblack@eecs.umich.edu class Rdcr(RegOp): 8895076Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 8905040Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 8914733Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 8924756Sgblack@eecs.umich.edu code = ''' 8936456Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 8947967Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 8954733Sgblack@eecs.umich.edu } else { 8966456Sgblack@eecs.umich.edu DestReg = ControlSrc1; 8976456Sgblack@eecs.umich.edu } 8984733Sgblack@eecs.umich.edu ''' 8994733Sgblack@eecs.umich.edu 9004823Sgblack@eecs.umich.edu class Wrcr(RegOp): 9016456Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9024733Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 9037967Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 9046447Sgblack@eecs.umich.edu code = ''' 9055040Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 9065076Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 9075076Sgblack@eecs.umich.edu } else { 9085076Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 9096456Sgblack@eecs.umich.edu // parser. They may be unnecessary. 9105076Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 9115076Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 9125076Sgblack@eecs.umich.edu 9135076Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 9146456Sgblack@eecs.umich.edu switch(dest) { 9155076Sgblack@eecs.umich.edu case 0: 9166456Sgblack@eecs.umich.edu { 9176456Sgblack@eecs.umich.edu Efer efer = EferOp; 9185076Sgblack@eecs.umich.edu CR0 cr0 = newVal; 9195076Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 9205076Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 9215076Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 9225076Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 9235076Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 9245076Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9255076Sgblack@eecs.umich.edu } 9265076Sgblack@eecs.umich.edu break; 9274732Sgblack@eecs.umich.edu case 2: 9286479Sgblack@eecs.umich.edu break; 9297967Sgblack@eecs.umich.edu case 3: 9306479Sgblack@eecs.umich.edu break; 9316479Sgblack@eecs.umich.edu case 4: 9327967Sgblack@eecs.umich.edu { 9336479Sgblack@eecs.umich.edu CR4 cr4 = newVal; 9346479Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 9356479Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 9366479Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 9376479Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9386479Sgblack@eecs.umich.edu } 9396479Sgblack@eecs.umich.edu break; 9406479Sgblack@eecs.umich.edu case 8: 9416479Sgblack@eecs.umich.edu { 9426479Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 9437967Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 9446479Sgblack@eecs.umich.edu } 9457967Sgblack@eecs.umich.edu default: 9467967Sgblack@eecs.umich.edu panic("Unrecognized control register %d.\\n", dest); 9476479Sgblack@eecs.umich.edu } 9486479Sgblack@eecs.umich.edu ControlDest = newVal; 9496479Sgblack@eecs.umich.edu } 9506479Sgblack@eecs.umich.edu ''' 9516479Sgblack@eecs.umich.edu 9526479Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 9536479Sgblack@eecs.umich.edu class SegOp(RegOp): 9546479Sgblack@eecs.umich.edu abstract = True 9556479Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 9566479Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 9576479Sgblack@eecs.umich.edu src1, "NUM_INTREGS", flags, dataSize) 9586479Sgblack@eecs.umich.edu 9596479Sgblack@eecs.umich.edu class Wrbase(SegOp): 9606479Sgblack@eecs.umich.edu code = ''' 9616479Sgblack@eecs.umich.edu SegBaseDest = psrc1; 9626479Sgblack@eecs.umich.edu ''' 9636479Sgblack@eecs.umich.edu 9646479Sgblack@eecs.umich.edu class Wrlimit(SegOp): 9656479Sgblack@eecs.umich.edu code = ''' 9666479Sgblack@eecs.umich.edu SegLimitDest = psrc1; 9676479Sgblack@eecs.umich.edu ''' 9686479Sgblack@eecs.umich.edu 9696479Sgblack@eecs.umich.edu class Wrsel(SegOp): 9706479Sgblack@eecs.umich.edu code = ''' 9716479Sgblack@eecs.umich.edu SegSelDest = psrc1; 9726479Sgblack@eecs.umich.edu ''' 9736479Sgblack@eecs.umich.edu 9746479Sgblack@eecs.umich.edu class Rdbase(SegOp): 9756479Sgblack@eecs.umich.edu code = ''' 9766479Sgblack@eecs.umich.edu DestReg = SegBaseDest; 9777967Sgblack@eecs.umich.edu ''' 9786479Sgblack@eecs.umich.edu 9796479Sgblack@eecs.umich.edu class Rdlimit(SegOp): 9807967Sgblack@eecs.umich.edu code = ''' 9816479Sgblack@eecs.umich.edu DestReg = SegLimitSrc1; 9826479Sgblack@eecs.umich.edu ''' 9836479Sgblack@eecs.umich.edu 9846479Sgblack@eecs.umich.edu class Rdsel(SegOp): 9856479Sgblack@eecs.umich.edu code = ''' 9866479Sgblack@eecs.umich.edu DestReg = SegSelSrc1; 9876479Sgblack@eecs.umich.edu ''' 9886479Sgblack@eecs.umich.edu 9896479Sgblack@eecs.umich.edu class Chks(SegOp): 9906479Sgblack@eecs.umich.edu code = ''' 9916479Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 9926479Sgblack@eecs.umich.edu SegSelector selector = psrc1; 9936479Sgblack@eecs.umich.edu 9946479Sgblack@eecs.umich.edu // Compute the address of the descriptor and set DestReg to it. 9956479Sgblack@eecs.umich.edu if (selector.ti) { 9966479Sgblack@eecs.umich.edu // A descriptor in the LDT 9977967Sgblack@eecs.umich.edu Addr target = (selector.si << 3) + LDTRBase; 9986479Sgblack@eecs.umich.edu if (!LDTRSel || (selector.si << 3) + dataSize > LDTRLimit) 9997967Sgblack@eecs.umich.edu fault = new GeneralProtection(selector & mask(16)); 10007967Sgblack@eecs.umich.edu DestReg = target; 10016479Sgblack@eecs.umich.edu } else { 10026479Sgblack@eecs.umich.edu // A descriptor in the GDT 10036479Sgblack@eecs.umich.edu Addr target = (selector.si << 3) + GDTRBase; 10046479Sgblack@eecs.umich.edu if ((selector.si << 3) + dataSize > GDTRLimit) 10056479Sgblack@eecs.umich.edu fault = new GeneralProtection(selector & mask(16)); 10066479Sgblack@eecs.umich.edu DestReg = target; 10076479Sgblack@eecs.umich.edu } 10086479Sgblack@eecs.umich.edu ''' 10096479Sgblack@eecs.umich.edu flag_code = ''' 10106479Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 10116479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 10126479Sgblack@eecs.umich.edu if (!selector.si && !selector.ti) 10136479Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 10146479Sgblack@eecs.umich.edu ''' 10156479Sgblack@eecs.umich.edu 10166479Sgblack@eecs.umich.edu class Wrdh(RegOp): 10176479Sgblack@eecs.umich.edu code = ''' 10186479Sgblack@eecs.umich.edu 10196479Sgblack@eecs.umich.edu ''' 10206479Sgblack@eecs.umich.edu 10216479Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 10226479Sgblack@eecs.umich.edu code = ''' 10236479Sgblack@eecs.umich.edu TscOp = psrc1; 10246479Sgblack@eecs.umich.edu ''' 10256479Sgblack@eecs.umich.edu 10266479Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 10276479Sgblack@eecs.umich.edu code = ''' 10286479Sgblack@eecs.umich.edu DestReg = TscOp; 10296479Sgblack@eecs.umich.edu ''' 10306479Sgblack@eecs.umich.edu 10316479Sgblack@eecs.umich.edu class Wrdl(RegOp): 10326479Sgblack@eecs.umich.edu code = ''' 10335040Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 10347789Sgblack@eecs.umich.edu SegAttr attr = 0; 10357789Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 10365040Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 10375040Sgblack@eecs.umich.edu if (!desc.s) { 10385040Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 10395040Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 10405426Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 10415426Sgblack@eecs.umich.edu panic("System segment encountered.\\n"); 10425426Sgblack@eecs.umich.edu } else { 10435426Sgblack@eecs.umich.edu if (!desc.p) 10445426Sgblack@eecs.umich.edu panic("Segment not present.\\n"); 10455426Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 10465426Sgblack@eecs.umich.edu attr.readable = desc.type.r; 10475426Sgblack@eecs.umich.edu attr.longMode = desc.l; 10485426Sgblack@eecs.umich.edu } else { 10495426Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 10505040Sgblack@eecs.umich.edu attr.readable = 1; 10517789Sgblack@eecs.umich.edu attr.writable = desc.type.w; 10525040Sgblack@eecs.umich.edu } 10535040Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 10545040Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 10555040Sgblack@eecs.umich.edu if (desc.g) 10565426Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 10575426Sgblack@eecs.umich.edu SegBaseDest = base; 10585426Sgblack@eecs.umich.edu SegLimitDest = limit; 10595040Sgblack@eecs.umich.edu SegAttrDest = attr; 10605040Sgblack@eecs.umich.edu } 10615116Sgblack@eecs.umich.edu ''' 10624951Sgblack@eecs.umich.edu}}; 10635011Sgblack@eecs.umich.edu