regop.isa revision 5075
14519Sgblack@eecs.umich.edu// Copyright (c) 2007 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 44519Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 54519Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 64519Sgblack@eecs.umich.edu// following conditions are met: 74519Sgblack@eecs.umich.edu// 84519Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 94519Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 104519Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 114519Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 134519Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 144519Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 154519Sgblack@eecs.umich.edu// commercial advantage. 164519Sgblack@eecs.umich.edu// 174519Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 184519Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 194519Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 204519Sgblack@eecs.umich.edu// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 224519Sgblack@eecs.umich.edu// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 274519Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 284519Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 294519Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 304519Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 314519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 324519Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 334519Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 344519Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 354519Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534519Sgblack@eecs.umich.edu// 544519Sgblack@eecs.umich.edu// Authors: Gabe Black 554519Sgblack@eecs.umich.edu 564519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574519Sgblack@eecs.umich.edu// 584519Sgblack@eecs.umich.edu// RegOp Microop templates 594519Sgblack@eecs.umich.edu// 604519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614519Sgblack@eecs.umich.edu 624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 694519Sgblack@eecs.umich.edu %(op_decl)s; 704519Sgblack@eecs.umich.edu %(op_rd)s; 714688Sgblack@eecs.umich.edu 724688Sgblack@eecs.umich.edu if(%(cond_check)s) 734688Sgblack@eecs.umich.edu { 744688Sgblack@eecs.umich.edu %(code)s; 754688Sgblack@eecs.umich.edu %(flag_code)s; 764688Sgblack@eecs.umich.edu } 774708Sgblack@eecs.umich.edu else 784708Sgblack@eecs.umich.edu { 794708Sgblack@eecs.umich.edu %(else_code)s; 804708Sgblack@eecs.umich.edu } 814519Sgblack@eecs.umich.edu 824519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 834519Sgblack@eecs.umich.edu if(fault == NoFault) 844519Sgblack@eecs.umich.edu { 854519Sgblack@eecs.umich.edu %(op_wb)s; 864519Sgblack@eecs.umich.edu } 874519Sgblack@eecs.umich.edu return fault; 884519Sgblack@eecs.umich.edu } 894519Sgblack@eecs.umich.edu}}; 904519Sgblack@eecs.umich.edu 914519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 924951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 934519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 944519Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu Fault fault = NoFault; 964519Sgblack@eecs.umich.edu 974519Sgblack@eecs.umich.edu %(op_decl)s; 984519Sgblack@eecs.umich.edu %(op_rd)s; 994688Sgblack@eecs.umich.edu 1004688Sgblack@eecs.umich.edu if(%(cond_check)s) 1014688Sgblack@eecs.umich.edu { 1024688Sgblack@eecs.umich.edu %(code)s; 1034688Sgblack@eecs.umich.edu %(flag_code)s; 1044688Sgblack@eecs.umich.edu } 1054708Sgblack@eecs.umich.edu else 1064708Sgblack@eecs.umich.edu { 1074708Sgblack@eecs.umich.edu %(else_code)s; 1084708Sgblack@eecs.umich.edu } 1094519Sgblack@eecs.umich.edu 1104519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1114519Sgblack@eecs.umich.edu if(fault == NoFault) 1124519Sgblack@eecs.umich.edu { 1134519Sgblack@eecs.umich.edu %(op_wb)s; 1144519Sgblack@eecs.umich.edu } 1154519Sgblack@eecs.umich.edu return fault; 1164519Sgblack@eecs.umich.edu } 1174519Sgblack@eecs.umich.edu}}; 1184519Sgblack@eecs.umich.edu 1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1204519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu protected: 1234519Sgblack@eecs.umich.edu void buildMe(); 1244519Sgblack@eecs.umich.edu 1254519Sgblack@eecs.umich.edu public: 1264519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1274519Sgblack@eecs.umich.edu const char * instMnem, 1284519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1294519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1304712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1334519Sgblack@eecs.umich.edu const char * instMnem, 1344519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1354712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1364519Sgblack@eecs.umich.edu 1374519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1384519Sgblack@eecs.umich.edu }; 1394519Sgblack@eecs.umich.edu}}; 1404519Sgblack@eecs.umich.edu 1414519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1424519Sgblack@eecs.umich.edu 1434951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1444519Sgblack@eecs.umich.edu { 1454519Sgblack@eecs.umich.edu protected: 1464519Sgblack@eecs.umich.edu void buildMe(); 1474519Sgblack@eecs.umich.edu 1484519Sgblack@eecs.umich.edu public: 1494951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1504519Sgblack@eecs.umich.edu const char * instMnem, 1514519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1524951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1534712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1544519Sgblack@eecs.umich.edu 1554951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1564519Sgblack@eecs.umich.edu const char * instMnem, 1574951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1584712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1594519Sgblack@eecs.umich.edu 1604519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1614519Sgblack@eecs.umich.edu }; 1624519Sgblack@eecs.umich.edu}}; 1634519Sgblack@eecs.umich.edu 1644519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1654519Sgblack@eecs.umich.edu 1664519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1674519Sgblack@eecs.umich.edu { 1684519Sgblack@eecs.umich.edu %(constructor)s; 1694519Sgblack@eecs.umich.edu } 1704519Sgblack@eecs.umich.edu 1714519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1724519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1734519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1744712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1754519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1764581Sgblack@eecs.umich.edu false, false, false, false, 1774688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1784581Sgblack@eecs.umich.edu %(op_class)s) 1794519Sgblack@eecs.umich.edu { 1804519Sgblack@eecs.umich.edu buildMe(); 1814519Sgblack@eecs.umich.edu } 1824519Sgblack@eecs.umich.edu 1834519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1844519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1854519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1864519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1874712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1884519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1894581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1904688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1914581Sgblack@eecs.umich.edu %(op_class)s) 1924519Sgblack@eecs.umich.edu { 1934519Sgblack@eecs.umich.edu buildMe(); 1944519Sgblack@eecs.umich.edu } 1954519Sgblack@eecs.umich.edu}}; 1964519Sgblack@eecs.umich.edu 1974519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1984519Sgblack@eecs.umich.edu 1994951Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 2004519Sgblack@eecs.umich.edu { 2014519Sgblack@eecs.umich.edu %(constructor)s; 2024519Sgblack@eecs.umich.edu } 2034519Sgblack@eecs.umich.edu 2044951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2054519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2064951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2074712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2084519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2094581Sgblack@eecs.umich.edu false, false, false, false, 2104688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2114581Sgblack@eecs.umich.edu %(op_class)s) 2124519Sgblack@eecs.umich.edu { 2134519Sgblack@eecs.umich.edu buildMe(); 2144519Sgblack@eecs.umich.edu } 2154519Sgblack@eecs.umich.edu 2164951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2174519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2184519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2194951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2204712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2214519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2224581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2234688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2244581Sgblack@eecs.umich.edu %(op_class)s) 2254519Sgblack@eecs.umich.edu { 2264519Sgblack@eecs.umich.edu buildMe(); 2274519Sgblack@eecs.umich.edu } 2284519Sgblack@eecs.umich.edu}}; 2294519Sgblack@eecs.umich.edu 2305075Sgblack@eecs.umich.eduoutput header {{ 2315075Sgblack@eecs.umich.edu void 2325075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2335075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 2345075Sgblack@eecs.umich.edu}}; 2355075Sgblack@eecs.umich.edu 2365075Sgblack@eecs.umich.eduoutput decoder {{ 2375075Sgblack@eecs.umich.edu void 2385075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2395075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 2405075Sgblack@eecs.umich.edu { 2415075Sgblack@eecs.umich.edu //Check for divide by zero. 2425075Sgblack@eecs.umich.edu if (divisor == 0) 2435075Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 2445075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 2455075Sgblack@eecs.umich.edu if (divisor <= dividend) { 2465075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 2475075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 2485075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 2495075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 2505075Sgblack@eecs.umich.edu divisor <<= shift; 2515075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 2525075Sgblack@eecs.umich.edu //now larger than the dividend. 2535075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 2545075Sgblack@eecs.umich.edu quotientBit <<= shift; 2555075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2565075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2575075Sgblack@eecs.umich.edu //part of one or two bit division. 2585075Sgblack@eecs.umich.edu if (divisor > dividend) { 2595075Sgblack@eecs.umich.edu quotientBit >>= 1; 2605075Sgblack@eecs.umich.edu divisor >>= 1; 2615075Sgblack@eecs.umich.edu } 2625075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2635075Sgblack@eecs.umich.edu quotient += quotientBit; 2645075Sgblack@eecs.umich.edu remainder -= divisor; 2655075Sgblack@eecs.umich.edu } 2665075Sgblack@eecs.umich.edu } 2675075Sgblack@eecs.umich.edu}}; 2685075Sgblack@eecs.umich.edu 2694519Sgblack@eecs.umich.edulet {{ 2705040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2715040Sgblack@eecs.umich.edu # them will always work. 2725040Sgblack@eecs.umich.edu header_output = "" 2735040Sgblack@eecs.umich.edu decoder_output = "" 2745040Sgblack@eecs.umich.edu exec_output = "" 2755040Sgblack@eecs.umich.edu 2765040Sgblack@eecs.umich.edu immTemplates = ( 2775040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2785040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2795040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2805040Sgblack@eecs.umich.edu 2815040Sgblack@eecs.umich.edu regTemplates = ( 2825040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2835040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2845040Sgblack@eecs.umich.edu MicroRegOpExecute) 2855040Sgblack@eecs.umich.edu 2865040Sgblack@eecs.umich.edu class RegOpMeta(type): 2875040Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 2885040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code): 2895040Sgblack@eecs.umich.edu 2905040Sgblack@eecs.umich.edu # Globals to stick the output in 2915040Sgblack@eecs.umich.edu global header_output 2925040Sgblack@eecs.umich.edu global decoder_output 2935040Sgblack@eecs.umich.edu global exec_output 2945040Sgblack@eecs.umich.edu 2955040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2965040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 2975040Sgblack@eecs.umich.edu 2985040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2995040Sgblack@eecs.umich.edu # of this code. 3005062Sgblack@eecs.umich.edu matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 3015062Sgblack@eecs.umich.edu match = matcher.search(allCode) 3025062Sgblack@eecs.umich.edu if match: 3035062Sgblack@eecs.umich.edu typeQual = "" 3045062Sgblack@eecs.umich.edu if match.group("typeQual"): 3055062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 3065062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3075040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3085062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 3095062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 3105062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 3115062Sgblack@eecs.umich.edu matcher.sub(src2_name, else_code)) 3125040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 3135040Sgblack@eecs.umich.edu matcher.sub("imm8", code), 3145040Sgblack@eecs.umich.edu matcher.sub("imm8", flag_code), 3155040Sgblack@eecs.umich.edu matcher.sub("imm8", cond_check), 3165040Sgblack@eecs.umich.edu matcher.sub("imm8", else_code)) 3175040Sgblack@eecs.umich.edu return 3185040Sgblack@eecs.umich.edu 3195040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 3205040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 3215040Sgblack@eecs.umich.edu if flag_code is not "" or cond_check is not "true": 3225040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 3235040Sgblack@eecs.umich.edu code, "", "true", else_code) 3245040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 3255040Sgblack@eecs.umich.edu 3265040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 3275040Sgblack@eecs.umich.edu # compute it. 3285040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 3295040Sgblack@eecs.umich.edu if matcher.search(allCode): 3305061Sgblack@eecs.umich.edu code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3315040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 3325040Sgblack@eecs.umich.edu if matcher.search(allCode): 3335061Sgblack@eecs.umich.edu code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3345061Sgblack@eecs.umich.edu # Also make available versions which do sign extension 3355061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3365061Sgblack@eecs.umich.edu if matcher.search(allCode): 3375061Sgblack@eecs.umich.edu code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3385061Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3395061Sgblack@eecs.umich.edu if matcher.search(allCode): 3405061Sgblack@eecs.umich.edu code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3415040Sgblack@eecs.umich.edu 3425040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3435040Sgblack@eecs.umich.edu 3445040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3455040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3465040Sgblack@eecs.umich.edu templates = regTemplates 3475040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)imm8(?!\w)") 3485040Sgblack@eecs.umich.edu if matcher.search(allCode): 3495040Sgblack@eecs.umich.edu base += "Imm" 3505040Sgblack@eecs.umich.edu templates = immTemplates 3515040Sgblack@eecs.umich.edu 3525040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3535040Sgblack@eecs.umich.edu iop = InstObjParams(name, Name + suffix, base, 3545040Sgblack@eecs.umich.edu {"code" : code, 3555040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3565040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3575040Sgblack@eecs.umich.edu "else_code" : else_code}) 3585040Sgblack@eecs.umich.edu 3595040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3605040Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3615040Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3625040Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3635040Sgblack@eecs.umich.edu 3645040Sgblack@eecs.umich.edu 3655040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3664688Sgblack@eecs.umich.edu abstract = False 3675040Sgblack@eecs.umich.edu name = Name.lower() 3684688Sgblack@eecs.umich.edu if "abstract" in dict: 3694688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3704688Sgblack@eecs.umich.edu del dict['abstract'] 3714688Sgblack@eecs.umich.edu 3725040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3734688Sgblack@eecs.umich.edu if not abstract: 3745040Sgblack@eecs.umich.edu cls.className = Name 3755040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3765040Sgblack@eecs.umich.edu code = cls.code 3775040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3785040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3795040Sgblack@eecs.umich.edu else_code = cls.else_code 3805040Sgblack@eecs.umich.edu 3815040Sgblack@eecs.umich.edu # Set up the C++ classes 3825040Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", 3835040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code) 3845040Sgblack@eecs.umich.edu 3855040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3865040Sgblack@eecs.umich.edu global microopClasses 3875040Sgblack@eecs.umich.edu microopClasses[name] = cls 3885040Sgblack@eecs.umich.edu 3895040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3905040Sgblack@eecs.umich.edu 3915040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3925040Sgblack@eecs.umich.edu # of this code. 3935040Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3945040Sgblack@eecs.umich.edu if matcher.search(allCode): 3955040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3964688Sgblack@eecs.umich.edu return cls 3974688Sgblack@eecs.umich.edu 3985040Sgblack@eecs.umich.edu 3995040Sgblack@eecs.umich.edu class RegOp(X86Microop): 4005040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 4015040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 4024688Sgblack@eecs.umich.edu abstract = True 4034688Sgblack@eecs.umich.edu 4045040Sgblack@eecs.umich.edu # Default template parameter values 4055040Sgblack@eecs.umich.edu flag_code = "" 4065040Sgblack@eecs.umich.edu cond_check = "true" 4075040Sgblack@eecs.umich.edu else_code = ";" 4085040Sgblack@eecs.umich.edu 4095040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4104519Sgblack@eecs.umich.edu self.dest = dest 4114519Sgblack@eecs.umich.edu self.src1 = src1 4125040Sgblack@eecs.umich.edu self.op2 = op2 4134688Sgblack@eecs.umich.edu self.flags = flags 4144701Sgblack@eecs.umich.edu self.dataSize = dataSize 4154688Sgblack@eecs.umich.edu if flags is None: 4164688Sgblack@eecs.umich.edu self.ext = 0 4174688Sgblack@eecs.umich.edu else: 4184688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4194688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4204688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 4214688Sgblack@eecs.umich.edu self.className += "Flags" 4224519Sgblack@eecs.umich.edu 4234519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 4245040Sgblack@eecs.umich.edu className = self.className 4255040Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4265040Sgblack@eecs.umich.edu className += "Imm" 4274560Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 4285040Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4294688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4305040Sgblack@eecs.umich.edu "class_name" : className, 4314519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4325040Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4334519Sgblack@eecs.umich.edu "dest" : self.dest, 4344519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4354519Sgblack@eecs.umich.edu "ext" : self.ext} 4364539Sgblack@eecs.umich.edu return allocator 4374519Sgblack@eecs.umich.edu 4385040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4394688Sgblack@eecs.umich.edu abstract = True 4405040Sgblack@eecs.umich.edu flag_code = ''' 4415040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4425040Sgblack@eecs.umich.edu uint64_t mask = CFBit | OFBit; 4435040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4445040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4455040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 4465040Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 4475040Sgblack@eecs.umich.edu ''' 4484519Sgblack@eecs.umich.edu 4495040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4505040Sgblack@eecs.umich.edu abstract = True 4515040Sgblack@eecs.umich.edu flag_code = \ 4525040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4534519Sgblack@eecs.umich.edu 4545040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4555040Sgblack@eecs.umich.edu abstract = True 4565040Sgblack@eecs.umich.edu flag_code = \ 4575040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4584519Sgblack@eecs.umich.edu 4595040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4605040Sgblack@eecs.umich.edu abstract = True 4615040Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits)" 4624519Sgblack@eecs.umich.edu 4635063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4645063Sgblack@eecs.umich.edu abstract = True 4655063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4665063Sgblack@eecs.umich.edu if not src1: 4675063Sgblack@eecs.umich.edu src1 = dest 4685063Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 4695063Sgblack@eecs.umich.edu 4705063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 4715063Sgblack@eecs.umich.edu abstract = True 4725063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4735063Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 4745063Sgblack@eecs.umich.edu 4755040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4765040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4774595Sgblack@eecs.umich.edu 4785040Sgblack@eecs.umich.edu class Or(LogicRegOp): 4795040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4804595Sgblack@eecs.umich.edu 4815040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 4825040Sgblack@eecs.umich.edu code = ''' 4834732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4844823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize); 4855040Sgblack@eecs.umich.edu ''' 4865040Sgblack@eecs.umich.edu 4875040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 4885040Sgblack@eecs.umich.edu code = ''' 4894732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4904823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize); 4915040Sgblack@eecs.umich.edu ''' 4925040Sgblack@eecs.umich.edu 4935040Sgblack@eecs.umich.edu class And(LogicRegOp): 4945040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 4955040Sgblack@eecs.umich.edu 4965040Sgblack@eecs.umich.edu class Sub(SubRegOp): 4975040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 4985040Sgblack@eecs.umich.edu 4995040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5005040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 5015040Sgblack@eecs.umich.edu 5025065Sgblack@eecs.umich.edu # Neither of these is quite correct because it assumes that right shifting 5035065Sgblack@eecs.umich.edu # a signed or unsigned value does sign or zero extension respectively. 5045065Sgblack@eecs.umich.edu # The C standard says that what happens on a right shift with a 1 in the 5055065Sgblack@eecs.umich.edu # MSB position is undefined. On x86 and under likely most compilers the 5065065Sgblack@eecs.umich.edu # "right thing" happens, but this isn't a guarantee. 5075063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5085040Sgblack@eecs.umich.edu code = ''' 5095063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5105063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5115063Sgblack@eecs.umich.edu int64_t spsrc1_h = spsrc1 >> halfSize; 5125063Sgblack@eecs.umich.edu int64_t spsrc1_l = spsrc1 & mask(halfSize); 5135063Sgblack@eecs.umich.edu int64_t spsrc2_h = sop2 >> halfSize; 5145063Sgblack@eecs.umich.edu int64_t spsrc2_l = sop2 & mask(halfSize); 5155063Sgblack@eecs.umich.edu ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l + 5165063Sgblack@eecs.umich.edu ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) + 5175063Sgblack@eecs.umich.edu spsrc1_h * spsrc2_h; 5185040Sgblack@eecs.umich.edu ''' 5195040Sgblack@eecs.umich.edu 5205063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5215040Sgblack@eecs.umich.edu code = ''' 5225063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5234809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5245063Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 >> halfSize; 5255063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5265063Sgblack@eecs.umich.edu uint64_t psrc2_h = op2 >> halfSize; 5275063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5285063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5295063Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) + 5305063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5315040Sgblack@eecs.umich.edu ''' 5325040Sgblack@eecs.umich.edu 5335063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 5345063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5355040Sgblack@eecs.umich.edu 5365063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 5375063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5385063Sgblack@eecs.umich.edu if not src1: 5395063Sgblack@eecs.umich.edu src1 = dest 5405063Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize) 5415063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5425063Sgblack@eecs.umich.edu flag_code = ''' 5435063Sgblack@eecs.umich.edu if (ProdHi) 5445063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5455063Sgblack@eecs.umich.edu else 5465063Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5475063Sgblack@eecs.umich.edu ''' 5485062Sgblack@eecs.umich.edu 5495075Sgblack@eecs.umich.edu # One or two bit divide 5505075Sgblack@eecs.umich.edu class Div1(WrRegOp): 5515040Sgblack@eecs.umich.edu code = ''' 5525075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 5535075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 5545075Sgblack@eecs.umich.edu uint64_t quotient = 0; 5555075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 5565075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 5575075Sgblack@eecs.umich.edu //a source. 5585075Sgblack@eecs.umich.edu uint64_t divisor = op2; 5595075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 5605075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 5615075Sgblack@eecs.umich.edu //Do the division. 5625075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5635075Sgblack@eecs.umich.edu //Record the final results. 5645075Sgblack@eecs.umich.edu Remainder = remainder; 5655075Sgblack@eecs.umich.edu Quotient = quotient; 5665075Sgblack@eecs.umich.edu Divisor = divisor; 5675040Sgblack@eecs.umich.edu ''' 5684823Sgblack@eecs.umich.edu 5695075Sgblack@eecs.umich.edu # Step divide 5705075Sgblack@eecs.umich.edu class Div2(RegOp): 5715075Sgblack@eecs.umich.edu code = ''' 5725075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 5735075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 5745075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 5755075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 5765075Sgblack@eecs.umich.edu int remaining = op2; 5775075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 5785075Sgblack@eecs.umich.edu //little. 5795075Sgblack@eecs.umich.edu if (remaining) { 5805075Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 5815075Sgblack@eecs.umich.edu while(dividend < divisor && remaining) { 5825075Sgblack@eecs.umich.edu dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 5835075Sgblack@eecs.umich.edu quotient <<= 1; 5845075Sgblack@eecs.umich.edu remaining--; 5855075Sgblack@eecs.umich.edu } 5865075Sgblack@eecs.umich.edu remainder = dividend; 5875075Sgblack@eecs.umich.edu //Do the division. 5885075Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 5895075Sgblack@eecs.umich.edu } 5905075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 5915075Sgblack@eecs.umich.edu DestReg = merge(DestReg, remaining, dataSize); 5925075Sgblack@eecs.umich.edu //Record the final results 5935075Sgblack@eecs.umich.edu Remainder = remainder; 5945075Sgblack@eecs.umich.edu Quotient = quotient; 5955075Sgblack@eecs.umich.edu ''' 5965075Sgblack@eecs.umich.edu flag_code = ''' 5975075Sgblack@eecs.umich.edu if (DestReg == 0) 5985075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ext & EZFBit); 5995075Sgblack@eecs.umich.edu else 6005075Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6015075Sgblack@eecs.umich.edu ''' 6024732Sgblack@eecs.umich.edu 6035075Sgblack@eecs.umich.edu class Divq(RdRegOp): 6045075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6055075Sgblack@eecs.umich.edu 6065075Sgblack@eecs.umich.edu class Divr(RdRegOp): 6075075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6085040Sgblack@eecs.umich.edu 6095040Sgblack@eecs.umich.edu class Mov(CondRegOp): 6105040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6115040Sgblack@eecs.umich.edu else_code = 'DestReg=DestReg;' 6125040Sgblack@eecs.umich.edu 6134732Sgblack@eecs.umich.edu # Shift instructions 6145040Sgblack@eecs.umich.edu 6155040Sgblack@eecs.umich.edu class Sll(FlagRegOp): 6165040Sgblack@eecs.umich.edu code = ''' 6174756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6184823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6195040Sgblack@eecs.umich.edu ''' 6205040Sgblack@eecs.umich.edu 6215040Sgblack@eecs.umich.edu class Srl(FlagRegOp): 6225040Sgblack@eecs.umich.edu code = ''' 6234756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6244732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6254732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 6264732Sgblack@eecs.umich.edu // to be sure they're zero. 6274732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 6284823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 6295040Sgblack@eecs.umich.edu ''' 6305040Sgblack@eecs.umich.edu 6315040Sgblack@eecs.umich.edu class Sra(FlagRegOp): 6325040Sgblack@eecs.umich.edu code = ''' 6334756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6344732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 6354732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 6364732Sgblack@eecs.umich.edu // them manually to be sure. 6374732Sgblack@eecs.umich.edu uint64_t arithMask = 6385032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 6394823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 6405040Sgblack@eecs.umich.edu ''' 6415040Sgblack@eecs.umich.edu 6425040Sgblack@eecs.umich.edu class Ror(FlagRegOp): 6435040Sgblack@eecs.umich.edu code = ''' 6444732Sgblack@eecs.umich.edu uint8_t shiftAmt = 6454756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6464732Sgblack@eecs.umich.edu if(shiftAmt) 6474732Sgblack@eecs.umich.edu { 6484823Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 6494823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 6504732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 6514732Sgblack@eecs.umich.edu } 6524732Sgblack@eecs.umich.edu else 6534732Sgblack@eecs.umich.edu DestReg = DestReg; 6545040Sgblack@eecs.umich.edu ''' 6555040Sgblack@eecs.umich.edu 6565040Sgblack@eecs.umich.edu class Rcr(FlagRegOp): 6575040Sgblack@eecs.umich.edu code = ''' 6584733Sgblack@eecs.umich.edu uint8_t shiftAmt = 6594756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6604733Sgblack@eecs.umich.edu if(shiftAmt) 6614733Sgblack@eecs.umich.edu { 6624733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 6634733Sgblack@eecs.umich.edu uint64_t top = flags.CF << (dataSize * 8 - shiftAmt); 6644733Sgblack@eecs.umich.edu if(shiftAmt > 1) 6654823Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 6664823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 6674733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 6684733Sgblack@eecs.umich.edu } 6694733Sgblack@eecs.umich.edu else 6704733Sgblack@eecs.umich.edu DestReg = DestReg; 6715040Sgblack@eecs.umich.edu ''' 6725040Sgblack@eecs.umich.edu 6735040Sgblack@eecs.umich.edu class Rol(FlagRegOp): 6745040Sgblack@eecs.umich.edu code = ''' 6754732Sgblack@eecs.umich.edu uint8_t shiftAmt = 6764756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6774732Sgblack@eecs.umich.edu if(shiftAmt) 6784732Sgblack@eecs.umich.edu { 6794823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 6804732Sgblack@eecs.umich.edu uint64_t bottom = 6814823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 6824732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 6834732Sgblack@eecs.umich.edu } 6844732Sgblack@eecs.umich.edu else 6854732Sgblack@eecs.umich.edu DestReg = DestReg; 6865040Sgblack@eecs.umich.edu ''' 6875040Sgblack@eecs.umich.edu 6885040Sgblack@eecs.umich.edu class Rcl(FlagRegOp): 6895040Sgblack@eecs.umich.edu code = ''' 6904733Sgblack@eecs.umich.edu uint8_t shiftAmt = 6914756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6924733Sgblack@eecs.umich.edu if(shiftAmt) 6934733Sgblack@eecs.umich.edu { 6944733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 6954823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 6964733Sgblack@eecs.umich.edu uint64_t bottom = flags.CF << (shiftAmt - 1); 6974733Sgblack@eecs.umich.edu if(shiftAmt > 1) 6984733Sgblack@eecs.umich.edu bottom |= 6994823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 7004809Sgblack@eecs.umich.edu dataSize * 8 - shiftAmt + 1); 7014733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 7024733Sgblack@eecs.umich.edu } 7034733Sgblack@eecs.umich.edu else 7044733Sgblack@eecs.umich.edu DestReg = DestReg; 7055040Sgblack@eecs.umich.edu ''' 7064732Sgblack@eecs.umich.edu 7075040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 7085040Sgblack@eecs.umich.edu code = 'RIP = psrc1 + op2' 7095040Sgblack@eecs.umich.edu else_code="RIP = RIP;" 7105040Sgblack@eecs.umich.edu 7115040Sgblack@eecs.umich.edu class Br(WrRegOp, CondRegOp): 7125040Sgblack@eecs.umich.edu code = 'nuIP = psrc1 + op2;' 7135040Sgblack@eecs.umich.edu else_code='nuIP = nuIP;' 7145040Sgblack@eecs.umich.edu 7155040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 7165040Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 7175040Sgblack@eecs.umich.edu 7185040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 7195040Sgblack@eecs.umich.edu code = 'DestReg = RIP' 7205040Sgblack@eecs.umich.edu 7215040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 7225040Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 7235040Sgblack@eecs.umich.edu 7245040Sgblack@eecs.umich.edu class Ruflag(RegOp): 7255040Sgblack@eecs.umich.edu code = ''' 7265011Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8 + 0*psrc1); 7274951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 7285011Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 7295011Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 7305040Sgblack@eecs.umich.edu ''' 7315040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 7325040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 7335040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 7345040Sgblack@eecs.umich.edu "NUM_INTREGS", imm, flags, dataSize) 7354732Sgblack@eecs.umich.edu 7365040Sgblack@eecs.umich.edu class Sext(RegOp): 7375040Sgblack@eecs.umich.edu code = ''' 7384823Sgblack@eecs.umich.edu IntReg val = psrc1; 7394595Sgblack@eecs.umich.edu int sign_bit = bits(val, imm8-1, imm8-1); 7405007Sgblack@eecs.umich.edu uint64_t maskVal = mask(imm8); 7415007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 7425007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 7435040Sgblack@eecs.umich.edu ''' 7444714Sgblack@eecs.umich.edu 7455040Sgblack@eecs.umich.edu class Zext(RegOp): 7465040Sgblack@eecs.umich.edu code = 'DestReg = bits(psrc1, imm8-1, 0);' 7475046Sgblack@eecs.umich.edu 7485058Sgblack@eecs.umich.edu class Compfp(WrRegOp): 7495058Sgblack@eecs.umich.edu # This class sets the condition codes in rflags according to the 7505058Sgblack@eecs.umich.edu # rules for comparing floating point. 7515058Sgblack@eecs.umich.edu code = ''' 7525058Sgblack@eecs.umich.edu // ZF PF CF 7535058Sgblack@eecs.umich.edu // Unordered 1 1 1 7545058Sgblack@eecs.umich.edu // Greater than 0 0 0 7555058Sgblack@eecs.umich.edu // Less than 0 0 1 7565058Sgblack@eecs.umich.edu // Equal 1 0 0 7575058Sgblack@eecs.umich.edu // OF = SF = AF = 0 7585058Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit | 7595058Sgblack@eecs.umich.edu ZFBit | PFBit | CFBit); 7605058Sgblack@eecs.umich.edu if (isnan(FpSrcReg1) || isnan(FpSrcReg2)) 7615058Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit); 7625058Sgblack@eecs.umich.edu else if(FpSrcReg1 < FpSrcReg2) 7635058Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | CFBit; 7645058Sgblack@eecs.umich.edu else if(FpSrcReg1 == FpSrcReg2) 7655058Sgblack@eecs.umich.edu ccFlagBits = ccFlagBits | ZFBit; 7665058Sgblack@eecs.umich.edu ''' 7675058Sgblack@eecs.umich.edu 7685058Sgblack@eecs.umich.edu class Xorfp(RegOp): 7695058Sgblack@eecs.umich.edu code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' 7705058Sgblack@eecs.umich.edu 7715059Sgblack@eecs.umich.edu class Sqrtfp(RegOp): 7725059Sgblack@eecs.umich.edu code = 'FpDestReg = sqrt(FpSrcReg2);' 7735059Sgblack@eecs.umich.edu 7745058Sgblack@eecs.umich.edu class Movfp(CondRegOp): 7755058Sgblack@eecs.umich.edu code = 'FpDestReg.uqw = FpSrcReg2.uqw;' 7765058Sgblack@eecs.umich.edu else_code = 'FpDestReg.uqw = FpDestReg.uqw;' 7775058Sgblack@eecs.umich.edu 7785046Sgblack@eecs.umich.edu # Conversion microops 7795046Sgblack@eecs.umich.edu class ConvOp(RegOp): 7805046Sgblack@eecs.umich.edu abstract = True 7815046Sgblack@eecs.umich.edu def __init__(self, dest, src1): 7825046Sgblack@eecs.umich.edu super(ConvOp, self).__init__(dest, src1, "NUM_INTREGS") 7835046Sgblack@eecs.umich.edu 7845046Sgblack@eecs.umich.edu #FIXME This needs to always use 32 bits unless REX.W is present 7855046Sgblack@eecs.umich.edu class cvtf_i2d(ConvOp): 7865061Sgblack@eecs.umich.edu code = 'FpDestReg = spsrc1;' 7875046Sgblack@eecs.umich.edu 7885046Sgblack@eecs.umich.edu class cvtf_i2d_hi(ConvOp): 7895046Sgblack@eecs.umich.edu code = 'FpDestReg = bits(SrcReg1, 63, 32);' 7905046Sgblack@eecs.umich.edu 7915046Sgblack@eecs.umich.edu class cvtf_d2i(ConvOp): 7925046Sgblack@eecs.umich.edu code = ''' 7935046Sgblack@eecs.umich.edu int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1); 7945046Sgblack@eecs.umich.edu DestReg = merge(DestReg, intSrcReg1, dataSize); 7955046Sgblack@eecs.umich.edu ''' 7965047Sgblack@eecs.umich.edu 7975047Sgblack@eecs.umich.edu # These need to consider size at some point. They'll always use doubles 7985047Sgblack@eecs.umich.edu # for the moment. 7995047Sgblack@eecs.umich.edu class addfp(RegOp): 8005047Sgblack@eecs.umich.edu code = 'FpDestReg = FpSrcReg1 + FpSrcReg2;' 8015047Sgblack@eecs.umich.edu 8025047Sgblack@eecs.umich.edu class mulfp(RegOp): 8035047Sgblack@eecs.umich.edu code = 'FpDestReg = FpSrcReg1 * FpSrcReg2;' 8045047Sgblack@eecs.umich.edu 8055047Sgblack@eecs.umich.edu class divfp(RegOp): 8065047Sgblack@eecs.umich.edu code = 'FpDestReg = FpSrcReg1 / FpSrcReg2;' 8075047Sgblack@eecs.umich.edu 8085047Sgblack@eecs.umich.edu class subfp(RegOp): 8095047Sgblack@eecs.umich.edu code = 'FpDestReg = FpSrcReg1 - FpSrcReg2;' 8104519Sgblack@eecs.umich.edu}}; 811