regop.isa revision 5042
14519Sgblack@eecs.umich.edu// Copyright (c) 2007 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 44519Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 54519Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 64519Sgblack@eecs.umich.edu// following conditions are met: 74519Sgblack@eecs.umich.edu// 84519Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 94519Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 104519Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 114519Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 134519Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 144519Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 154519Sgblack@eecs.umich.edu// commercial advantage. 164519Sgblack@eecs.umich.edu// 174519Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 184519Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 194519Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 204519Sgblack@eecs.umich.edu// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 224519Sgblack@eecs.umich.edu// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. 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Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534519Sgblack@eecs.umich.edu// 544519Sgblack@eecs.umich.edu// Authors: Gabe Black 554519Sgblack@eecs.umich.edu 564519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574519Sgblack@eecs.umich.edu// 584519Sgblack@eecs.umich.edu// RegOp Microop templates 594519Sgblack@eecs.umich.edu// 604519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614519Sgblack@eecs.umich.edu 624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 694519Sgblack@eecs.umich.edu %(op_decl)s; 704519Sgblack@eecs.umich.edu %(op_rd)s; 714688Sgblack@eecs.umich.edu 724688Sgblack@eecs.umich.edu if(%(cond_check)s) 734688Sgblack@eecs.umich.edu { 744688Sgblack@eecs.umich.edu %(code)s; 754688Sgblack@eecs.umich.edu %(flag_code)s; 764688Sgblack@eecs.umich.edu } 774708Sgblack@eecs.umich.edu else 784708Sgblack@eecs.umich.edu { 794708Sgblack@eecs.umich.edu %(else_code)s; 804708Sgblack@eecs.umich.edu } 814519Sgblack@eecs.umich.edu 824519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 834519Sgblack@eecs.umich.edu if(fault == NoFault) 844519Sgblack@eecs.umich.edu { 854519Sgblack@eecs.umich.edu %(op_wb)s; 864519Sgblack@eecs.umich.edu } 874519Sgblack@eecs.umich.edu return fault; 884519Sgblack@eecs.umich.edu } 894519Sgblack@eecs.umich.edu}}; 904519Sgblack@eecs.umich.edu 914519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 924951Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 934519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 944519Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu Fault fault = NoFault; 964519Sgblack@eecs.umich.edu 974519Sgblack@eecs.umich.edu %(op_decl)s; 984519Sgblack@eecs.umich.edu %(op_rd)s; 994688Sgblack@eecs.umich.edu 1004688Sgblack@eecs.umich.edu if(%(cond_check)s) 1014688Sgblack@eecs.umich.edu { 1024688Sgblack@eecs.umich.edu %(code)s; 1034688Sgblack@eecs.umich.edu %(flag_code)s; 1044688Sgblack@eecs.umich.edu } 1054708Sgblack@eecs.umich.edu else 1064708Sgblack@eecs.umich.edu { 1074708Sgblack@eecs.umich.edu %(else_code)s; 1084708Sgblack@eecs.umich.edu } 1094519Sgblack@eecs.umich.edu 1104519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1114519Sgblack@eecs.umich.edu if(fault == NoFault) 1124519Sgblack@eecs.umich.edu { 1134519Sgblack@eecs.umich.edu %(op_wb)s; 1144519Sgblack@eecs.umich.edu } 1154519Sgblack@eecs.umich.edu return fault; 1164519Sgblack@eecs.umich.edu } 1174519Sgblack@eecs.umich.edu}}; 1184519Sgblack@eecs.umich.edu 1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1204519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu protected: 1234519Sgblack@eecs.umich.edu void buildMe(); 1244519Sgblack@eecs.umich.edu 1254519Sgblack@eecs.umich.edu public: 1264519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1274519Sgblack@eecs.umich.edu const char * instMnem, 1284519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1294519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1304712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1334519Sgblack@eecs.umich.edu const char * instMnem, 1344519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1354712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1364519Sgblack@eecs.umich.edu 1374519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1384519Sgblack@eecs.umich.edu }; 1394519Sgblack@eecs.umich.edu}}; 1404519Sgblack@eecs.umich.edu 1414519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1424519Sgblack@eecs.umich.edu 1434951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1444519Sgblack@eecs.umich.edu { 1454519Sgblack@eecs.umich.edu protected: 1464519Sgblack@eecs.umich.edu void buildMe(); 1474519Sgblack@eecs.umich.edu 1484519Sgblack@eecs.umich.edu public: 1494951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1504519Sgblack@eecs.umich.edu const char * instMnem, 1514519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1524951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1534712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1544519Sgblack@eecs.umich.edu 1554951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1564519Sgblack@eecs.umich.edu const char * instMnem, 1574951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 1584712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1594519Sgblack@eecs.umich.edu 1604519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1614519Sgblack@eecs.umich.edu }; 1624519Sgblack@eecs.umich.edu}}; 1634519Sgblack@eecs.umich.edu 1644519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1654519Sgblack@eecs.umich.edu 1664519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1674519Sgblack@eecs.umich.edu { 1684519Sgblack@eecs.umich.edu %(constructor)s; 1694519Sgblack@eecs.umich.edu } 1704519Sgblack@eecs.umich.edu 1714519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1724519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1734519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1744712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1754519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1764581Sgblack@eecs.umich.edu false, false, false, false, 1774688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1784581Sgblack@eecs.umich.edu %(op_class)s) 1794519Sgblack@eecs.umich.edu { 1804519Sgblack@eecs.umich.edu buildMe(); 1814519Sgblack@eecs.umich.edu } 1824519Sgblack@eecs.umich.edu 1834519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1844519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1854519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1864519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1874712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1884519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1894581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1904688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1914581Sgblack@eecs.umich.edu %(op_class)s) 1924519Sgblack@eecs.umich.edu { 1934519Sgblack@eecs.umich.edu buildMe(); 1944519Sgblack@eecs.umich.edu } 1954519Sgblack@eecs.umich.edu}}; 1964519Sgblack@eecs.umich.edu 1974519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1984519Sgblack@eecs.umich.edu 1994951Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 2004519Sgblack@eecs.umich.edu { 2014519Sgblack@eecs.umich.edu %(constructor)s; 2024519Sgblack@eecs.umich.edu } 2034519Sgblack@eecs.umich.edu 2044951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2054519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2064951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2074712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2084519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2094581Sgblack@eecs.umich.edu false, false, false, false, 2104688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2114581Sgblack@eecs.umich.edu %(op_class)s) 2124519Sgblack@eecs.umich.edu { 2134519Sgblack@eecs.umich.edu buildMe(); 2144519Sgblack@eecs.umich.edu } 2154519Sgblack@eecs.umich.edu 2164951Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2174519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2184519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2194951Sgblack@eecs.umich.edu RegIndex _src1, uint16_t _imm8, RegIndex _dest, 2204712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2214519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2224581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2234688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2244581Sgblack@eecs.umich.edu %(op_class)s) 2254519Sgblack@eecs.umich.edu { 2264519Sgblack@eecs.umich.edu buildMe(); 2274519Sgblack@eecs.umich.edu } 2284519Sgblack@eecs.umich.edu}}; 2294519Sgblack@eecs.umich.edu 2304519Sgblack@eecs.umich.edulet {{ 2315040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2325040Sgblack@eecs.umich.edu # them will always work. 2335040Sgblack@eecs.umich.edu header_output = "" 2345040Sgblack@eecs.umich.edu decoder_output = "" 2355040Sgblack@eecs.umich.edu exec_output = "" 2365040Sgblack@eecs.umich.edu 2375040Sgblack@eecs.umich.edu immTemplates = ( 2385040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2395040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2405040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2415040Sgblack@eecs.umich.edu 2425040Sgblack@eecs.umich.edu regTemplates = ( 2435040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2445040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2455040Sgblack@eecs.umich.edu MicroRegOpExecute) 2465040Sgblack@eecs.umich.edu 2475040Sgblack@eecs.umich.edu class RegOpMeta(type): 2485040Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, \ 2495040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code): 2505040Sgblack@eecs.umich.edu 2515040Sgblack@eecs.umich.edu # Globals to stick the output in 2525040Sgblack@eecs.umich.edu global header_output 2535040Sgblack@eecs.umich.edu global decoder_output 2545040Sgblack@eecs.umich.edu global exec_output 2555040Sgblack@eecs.umich.edu 2565040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2575040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 2585040Sgblack@eecs.umich.edu 2595040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2605040Sgblack@eecs.umich.edu # of this code. 2615040Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 2625040Sgblack@eecs.umich.edu if matcher.search(allCode): 2635040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2645040Sgblack@eecs.umich.edu matcher.sub("psrc2", code), 2655040Sgblack@eecs.umich.edu matcher.sub("psrc2", flag_code), 2665040Sgblack@eecs.umich.edu matcher.sub("psrc2", cond_check), 2675040Sgblack@eecs.umich.edu matcher.sub("psrc2", else_code)) 2685040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 2695040Sgblack@eecs.umich.edu matcher.sub("imm8", code), 2705040Sgblack@eecs.umich.edu matcher.sub("imm8", flag_code), 2715040Sgblack@eecs.umich.edu matcher.sub("imm8", cond_check), 2725040Sgblack@eecs.umich.edu matcher.sub("imm8", else_code)) 2735040Sgblack@eecs.umich.edu return 2745040Sgblack@eecs.umich.edu 2755040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 2765040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 2775040Sgblack@eecs.umich.edu if flag_code is not "" or cond_check is not "true": 2785040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2795040Sgblack@eecs.umich.edu code, "", "true", else_code) 2805040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 2815040Sgblack@eecs.umich.edu 2825040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 2835040Sgblack@eecs.umich.edu # compute it. 2845040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc1(?!\w)") 2855040Sgblack@eecs.umich.edu if matcher.search(allCode): 2865040Sgblack@eecs.umich.edu code = "IntReg psrc1 = pick(SrcReg1, 0, dataSize);" + code 2875040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 2885040Sgblack@eecs.umich.edu if matcher.search(allCode): 2895040Sgblack@eecs.umich.edu code = "IntReg psrc2 = pick(SrcReg2, 1, dataSize);" + code 2905040Sgblack@eecs.umich.edu 2915040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 2925040Sgblack@eecs.umich.edu 2935040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 2945040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 2955040Sgblack@eecs.umich.edu templates = regTemplates 2965040Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)imm8(?!\w)") 2975040Sgblack@eecs.umich.edu if matcher.search(allCode): 2985040Sgblack@eecs.umich.edu base += "Imm" 2995040Sgblack@eecs.umich.edu templates = immTemplates 3005040Sgblack@eecs.umich.edu 3015040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3025040Sgblack@eecs.umich.edu iop = InstObjParams(name, Name + suffix, base, 3035040Sgblack@eecs.umich.edu {"code" : code, 3045040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3055040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3065040Sgblack@eecs.umich.edu "else_code" : else_code}) 3075040Sgblack@eecs.umich.edu 3085040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3095040Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3105040Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3115040Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3125040Sgblack@eecs.umich.edu 3135040Sgblack@eecs.umich.edu 3145040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3154688Sgblack@eecs.umich.edu abstract = False 3165040Sgblack@eecs.umich.edu name = Name.lower() 3174688Sgblack@eecs.umich.edu if "abstract" in dict: 3184688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3194688Sgblack@eecs.umich.edu del dict['abstract'] 3204688Sgblack@eecs.umich.edu 3215040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3224688Sgblack@eecs.umich.edu if not abstract: 3235040Sgblack@eecs.umich.edu cls.className = Name 3245040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3255040Sgblack@eecs.umich.edu code = cls.code 3265040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3275040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3285040Sgblack@eecs.umich.edu else_code = cls.else_code 3295040Sgblack@eecs.umich.edu 3305040Sgblack@eecs.umich.edu # Set up the C++ classes 3315040Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", 3325040Sgblack@eecs.umich.edu code, flag_code, cond_check, else_code) 3335040Sgblack@eecs.umich.edu 3345040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3355040Sgblack@eecs.umich.edu global microopClasses 3365040Sgblack@eecs.umich.edu microopClasses[name] = cls 3375040Sgblack@eecs.umich.edu 3385040Sgblack@eecs.umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 3395040Sgblack@eecs.umich.edu 3405040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3415040Sgblack@eecs.umich.edu # of this code. 3425040Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3435040Sgblack@eecs.umich.edu if matcher.search(allCode): 3445040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3454688Sgblack@eecs.umich.edu return cls 3464688Sgblack@eecs.umich.edu 3475040Sgblack@eecs.umich.edu 3485040Sgblack@eecs.umich.edu class RegOp(X86Microop): 3495040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 3505040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 3514688Sgblack@eecs.umich.edu abstract = True 3524688Sgblack@eecs.umich.edu 3535040Sgblack@eecs.umich.edu # Default template parameter values 3545040Sgblack@eecs.umich.edu flag_code = "" 3555040Sgblack@eecs.umich.edu cond_check = "true" 3565040Sgblack@eecs.umich.edu else_code = ";" 3575040Sgblack@eecs.umich.edu 3585040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 3594519Sgblack@eecs.umich.edu self.dest = dest 3604519Sgblack@eecs.umich.edu self.src1 = src1 3615040Sgblack@eecs.umich.edu self.op2 = op2 3624688Sgblack@eecs.umich.edu self.flags = flags 3634701Sgblack@eecs.umich.edu self.dataSize = dataSize 3644688Sgblack@eecs.umich.edu if flags is None: 3654688Sgblack@eecs.umich.edu self.ext = 0 3664688Sgblack@eecs.umich.edu else: 3674688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 3684688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 3694688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 3704688Sgblack@eecs.umich.edu self.className += "Flags" 3714519Sgblack@eecs.umich.edu 3724519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 3735040Sgblack@eecs.umich.edu className = self.className 3745040Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 3755040Sgblack@eecs.umich.edu className += "Imm" 3764560Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 3775040Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 3784688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 3795040Sgblack@eecs.umich.edu "class_name" : className, 3804519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 3815040Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 3824519Sgblack@eecs.umich.edu "dest" : self.dest, 3834519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 3844519Sgblack@eecs.umich.edu "ext" : self.ext} 3854539Sgblack@eecs.umich.edu return allocator 3864519Sgblack@eecs.umich.edu 3875040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 3884688Sgblack@eecs.umich.edu abstract = True 3895040Sgblack@eecs.umich.edu flag_code = ''' 3905040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 3915040Sgblack@eecs.umich.edu uint64_t mask = CFBit | OFBit; 3925040Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 3935040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 3945040Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 3955040Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 3965040Sgblack@eecs.umich.edu ''' 3974519Sgblack@eecs.umich.edu 3985040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 3995040Sgblack@eecs.umich.edu abstract = True 4005040Sgblack@eecs.umich.edu flag_code = \ 4015040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4024519Sgblack@eecs.umich.edu 4035040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4045040Sgblack@eecs.umich.edu abstract = True 4055040Sgblack@eecs.umich.edu flag_code = \ 4065040Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4074519Sgblack@eecs.umich.edu 4085040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4095040Sgblack@eecs.umich.edu abstract = True 4105040Sgblack@eecs.umich.edu cond_check = "checkCondition(ccFlagBits)" 4114519Sgblack@eecs.umich.edu 4125040Sgblack@eecs.umich.edu class Add(FlagRegOp): 4135040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4144595Sgblack@eecs.umich.edu 4155040Sgblack@eecs.umich.edu class Or(LogicRegOp): 4165040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4174595Sgblack@eecs.umich.edu 4185040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 4195040Sgblack@eecs.umich.edu code = ''' 4204732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4214823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize); 4225040Sgblack@eecs.umich.edu ''' 4235040Sgblack@eecs.umich.edu 4245040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 4255040Sgblack@eecs.umich.edu code = ''' 4264732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4274823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize); 4285040Sgblack@eecs.umich.edu ''' 4295040Sgblack@eecs.umich.edu 4305040Sgblack@eecs.umich.edu class And(LogicRegOp): 4315040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 4325040Sgblack@eecs.umich.edu 4335040Sgblack@eecs.umich.edu class Sub(SubRegOp): 4345040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 4355040Sgblack@eecs.umich.edu 4365040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 4375040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 4385040Sgblack@eecs.umich.edu 4395040Sgblack@eecs.umich.edu class Mul1s(FlagRegOp): 4405040Sgblack@eecs.umich.edu code = ''' 4414809Sgblack@eecs.umich.edu int signPos = (dataSize * 8) / 2 - 1; 4424823Sgblack@eecs.umich.edu IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos); 4434823Sgblack@eecs.umich.edu IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos); 4444809Sgblack@eecs.umich.edu DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize) 4455040Sgblack@eecs.umich.edu ''' 4465040Sgblack@eecs.umich.edu 4475040Sgblack@eecs.umich.edu class Mul1u(FlagRegOp): 4485040Sgblack@eecs.umich.edu code = ''' 4494809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 4504823Sgblack@eecs.umich.edu IntReg srcVal1 = psrc1 & mask(halfSize); 4514809Sgblack@eecs.umich.edu IntReg srcVal2 = op2 & mask(halfSize); 4524809Sgblack@eecs.umich.edu DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize) 4535040Sgblack@eecs.umich.edu ''' 4545040Sgblack@eecs.umich.edu 4555040Sgblack@eecs.umich.edu class Mulel(FlagRegOp): 4565042Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 * op2, dataSize);' 4575040Sgblack@eecs.umich.edu 4585040Sgblack@eecs.umich.edu class Muleh(FlagRegOp): 4595040Sgblack@eecs.umich.edu code = ''' 4604809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 4614823Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 >> halfSize; 4624823Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 4634823Sgblack@eecs.umich.edu uint64_t psrc2_h = op2 >> halfSize; 4644823Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 4654809Sgblack@eecs.umich.edu uint64_t result = 4664823Sgblack@eecs.umich.edu ((psrc1_l * psrc2_h) >> halfSize) + 4674823Sgblack@eecs.umich.edu ((psrc1_h * psrc2_l) >> halfSize) + 4684823Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 4694809Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 4705040Sgblack@eecs.umich.edu ''' 4715040Sgblack@eecs.umich.edu 4725040Sgblack@eecs.umich.edu class Div1(FlagRegOp): 4735040Sgblack@eecs.umich.edu code = ''' 4744823Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 4754823Sgblack@eecs.umich.edu IntReg quotient = (psrc1 / op2) & mask(halfSize); 4764823Sgblack@eecs.umich.edu IntReg remainder = (psrc1 % op2) & mask(halfSize); 4774823Sgblack@eecs.umich.edu IntReg result = quotient | (remainder << halfSize); 4784823Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 4795040Sgblack@eecs.umich.edu ''' 4804823Sgblack@eecs.umich.edu 4815040Sgblack@eecs.umich.edu class Divq(FlagRegOp): 4825040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 / op2, dataSize);' 4834732Sgblack@eecs.umich.edu 4845040Sgblack@eecs.umich.edu class Divr(FlagRegOp): 4855040Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, psrc1 % op2, dataSize);' 4865040Sgblack@eecs.umich.edu 4875040Sgblack@eecs.umich.edu class Mov(CondRegOp): 4885040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 4895040Sgblack@eecs.umich.edu else_code = 'DestReg=DestReg;' 4905040Sgblack@eecs.umich.edu 4915040Sgblack@eecs.umich.edu class Movfp(CondRegOp): 4925040Sgblack@eecs.umich.edu code = 'FpDestReg = FpSrcReg2' 4935040Sgblack@eecs.umich.edu else_code = 'FpDestReg = FpDestReg;' 4945028Sgblack@eecs.umich.edu 4954732Sgblack@eecs.umich.edu # Shift instructions 4965040Sgblack@eecs.umich.edu 4975040Sgblack@eecs.umich.edu class Sll(FlagRegOp): 4985040Sgblack@eecs.umich.edu code = ''' 4994756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5004823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 5015040Sgblack@eecs.umich.edu ''' 5025040Sgblack@eecs.umich.edu 5035040Sgblack@eecs.umich.edu class Srl(FlagRegOp): 5045040Sgblack@eecs.umich.edu code = ''' 5054756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5064732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 5074732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 5084732Sgblack@eecs.umich.edu // to be sure they're zero. 5094732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 5104823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 5115040Sgblack@eecs.umich.edu ''' 5125040Sgblack@eecs.umich.edu 5135040Sgblack@eecs.umich.edu class Sra(FlagRegOp): 5145040Sgblack@eecs.umich.edu code = ''' 5154756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5164732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 5174732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 5184732Sgblack@eecs.umich.edu // them manually to be sure. 5194732Sgblack@eecs.umich.edu uint64_t arithMask = 5205032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 5214823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 5225040Sgblack@eecs.umich.edu ''' 5235040Sgblack@eecs.umich.edu 5245040Sgblack@eecs.umich.edu class Ror(FlagRegOp): 5255040Sgblack@eecs.umich.edu code = ''' 5264732Sgblack@eecs.umich.edu uint8_t shiftAmt = 5274756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5284732Sgblack@eecs.umich.edu if(shiftAmt) 5294732Sgblack@eecs.umich.edu { 5304823Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 5314823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 5324732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5334732Sgblack@eecs.umich.edu } 5344732Sgblack@eecs.umich.edu else 5354732Sgblack@eecs.umich.edu DestReg = DestReg; 5365040Sgblack@eecs.umich.edu ''' 5375040Sgblack@eecs.umich.edu 5385040Sgblack@eecs.umich.edu class Rcr(FlagRegOp): 5395040Sgblack@eecs.umich.edu code = ''' 5404733Sgblack@eecs.umich.edu uint8_t shiftAmt = 5414756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5424733Sgblack@eecs.umich.edu if(shiftAmt) 5434733Sgblack@eecs.umich.edu { 5444733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5454733Sgblack@eecs.umich.edu uint64_t top = flags.CF << (dataSize * 8 - shiftAmt); 5464733Sgblack@eecs.umich.edu if(shiftAmt > 1) 5474823Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 5484823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 5494733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5504733Sgblack@eecs.umich.edu } 5514733Sgblack@eecs.umich.edu else 5524733Sgblack@eecs.umich.edu DestReg = DestReg; 5535040Sgblack@eecs.umich.edu ''' 5545040Sgblack@eecs.umich.edu 5555040Sgblack@eecs.umich.edu class Rol(FlagRegOp): 5565040Sgblack@eecs.umich.edu code = ''' 5574732Sgblack@eecs.umich.edu uint8_t shiftAmt = 5584756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5594732Sgblack@eecs.umich.edu if(shiftAmt) 5604732Sgblack@eecs.umich.edu { 5614823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 5624732Sgblack@eecs.umich.edu uint64_t bottom = 5634823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 5644732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5654732Sgblack@eecs.umich.edu } 5664732Sgblack@eecs.umich.edu else 5674732Sgblack@eecs.umich.edu DestReg = DestReg; 5685040Sgblack@eecs.umich.edu ''' 5695040Sgblack@eecs.umich.edu 5705040Sgblack@eecs.umich.edu class Rcl(FlagRegOp): 5715040Sgblack@eecs.umich.edu code = ''' 5724733Sgblack@eecs.umich.edu uint8_t shiftAmt = 5734756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5744733Sgblack@eecs.umich.edu if(shiftAmt) 5754733Sgblack@eecs.umich.edu { 5764733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5774823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 5784733Sgblack@eecs.umich.edu uint64_t bottom = flags.CF << (shiftAmt - 1); 5794733Sgblack@eecs.umich.edu if(shiftAmt > 1) 5804733Sgblack@eecs.umich.edu bottom |= 5814823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 5824809Sgblack@eecs.umich.edu dataSize * 8 - shiftAmt + 1); 5834733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5844733Sgblack@eecs.umich.edu } 5854733Sgblack@eecs.umich.edu else 5864733Sgblack@eecs.umich.edu DestReg = DestReg; 5875040Sgblack@eecs.umich.edu ''' 5884732Sgblack@eecs.umich.edu 5895040Sgblack@eecs.umich.edu class WrRegOp(RegOp): 5905040Sgblack@eecs.umich.edu abstract = True 5915040Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 5925040Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 5934732Sgblack@eecs.umich.edu 5945040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 5955040Sgblack@eecs.umich.edu code = 'RIP = psrc1 + op2' 5965040Sgblack@eecs.umich.edu else_code="RIP = RIP;" 5975040Sgblack@eecs.umich.edu 5985040Sgblack@eecs.umich.edu class Br(WrRegOp, CondRegOp): 5995040Sgblack@eecs.umich.edu code = 'nuIP = psrc1 + op2;' 6005040Sgblack@eecs.umich.edu else_code='nuIP = nuIP;' 6015040Sgblack@eecs.umich.edu 6025040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 6035040Sgblack@eecs.umich.edu code = 'ccFlagBits = psrc1 ^ op2' 6045040Sgblack@eecs.umich.edu 6055040Sgblack@eecs.umich.edu class RdRegOp(RegOp): 6065040Sgblack@eecs.umich.edu abstract = True 6075040Sgblack@eecs.umich.edu def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"): 6085040Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 6095040Sgblack@eecs.umich.edu 6105040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 6115040Sgblack@eecs.umich.edu code = 'DestReg = RIP' 6125040Sgblack@eecs.umich.edu 6135040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 6145040Sgblack@eecs.umich.edu code = 'DestReg = ccFlagBits' 6155040Sgblack@eecs.umich.edu 6165040Sgblack@eecs.umich.edu class Ruflag(RegOp): 6175040Sgblack@eecs.umich.edu code = ''' 6185011Sgblack@eecs.umich.edu int flag = bits(ccFlagBits, imm8 + 0*psrc1); 6194951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 6205011Sgblack@eecs.umich.edu ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 6215011Sgblack@eecs.umich.edu (ccFlagBits & ~EZFBit); 6225040Sgblack@eecs.umich.edu ''' 6235040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 6245040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 6255040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 6265040Sgblack@eecs.umich.edu "NUM_INTREGS", imm, flags, dataSize) 6274732Sgblack@eecs.umich.edu 6285040Sgblack@eecs.umich.edu class Sext(RegOp): 6295040Sgblack@eecs.umich.edu code = ''' 6304823Sgblack@eecs.umich.edu IntReg val = psrc1; 6314595Sgblack@eecs.umich.edu int sign_bit = bits(val, imm8-1, imm8-1); 6325007Sgblack@eecs.umich.edu uint64_t maskVal = mask(imm8); 6335007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 6345007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 6355040Sgblack@eecs.umich.edu ''' 6364714Sgblack@eecs.umich.edu 6375040Sgblack@eecs.umich.edu class Zext(RegOp): 6385040Sgblack@eecs.umich.edu code = 'DestReg = bits(psrc1, imm8-1, 0);' 6394519Sgblack@eecs.umich.edu}}; 640