regop.isa revision 5028
14519Sgblack@eecs.umich.edu// Copyright (c) 2007 The Hewlett-Packard Development Company
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64519Sgblack@eecs.umich.edu// following conditions are met:
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534519Sgblack@eecs.umich.edu//
544519Sgblack@eecs.umich.edu// Authors: Gabe Black
554519Sgblack@eecs.umich.edu
564519Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////////
574519Sgblack@eecs.umich.edu//
584519Sgblack@eecs.umich.edu// RegOp Microop templates
594519Sgblack@eecs.umich.edu//
604519Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////////
614519Sgblack@eecs.umich.edu
624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{
634519Sgblack@eecs.umich.edu        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
644519Sgblack@eecs.umich.edu                Trace::InstRecord *traceData) const
654519Sgblack@eecs.umich.edu        {
664519Sgblack@eecs.umich.edu            Fault fault = NoFault;
674519Sgblack@eecs.umich.edu
684809Sgblack@eecs.umich.edu            DPRINTF(X86, "The data size is %d\n", dataSize);
694519Sgblack@eecs.umich.edu            %(op_decl)s;
704519Sgblack@eecs.umich.edu            %(op_rd)s;
714688Sgblack@eecs.umich.edu
724688Sgblack@eecs.umich.edu            if(%(cond_check)s)
734688Sgblack@eecs.umich.edu            {
744688Sgblack@eecs.umich.edu                %(code)s;
754688Sgblack@eecs.umich.edu                %(flag_code)s;
764688Sgblack@eecs.umich.edu            }
774708Sgblack@eecs.umich.edu            else
784708Sgblack@eecs.umich.edu            {
794708Sgblack@eecs.umich.edu                %(else_code)s;
804708Sgblack@eecs.umich.edu            }
814519Sgblack@eecs.umich.edu
824519Sgblack@eecs.umich.edu            //Write the resulting state to the execution context
834519Sgblack@eecs.umich.edu            if(fault == NoFault)
844519Sgblack@eecs.umich.edu            {
854519Sgblack@eecs.umich.edu                %(op_wb)s;
864519Sgblack@eecs.umich.edu            }
874519Sgblack@eecs.umich.edu            return fault;
884519Sgblack@eecs.umich.edu        }
894519Sgblack@eecs.umich.edu}};
904519Sgblack@eecs.umich.edu
914519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{
924951Sgblack@eecs.umich.edu        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
934519Sgblack@eecs.umich.edu                Trace::InstRecord *traceData) const
944519Sgblack@eecs.umich.edu        {
954519Sgblack@eecs.umich.edu            Fault fault = NoFault;
964519Sgblack@eecs.umich.edu
974519Sgblack@eecs.umich.edu            %(op_decl)s;
984519Sgblack@eecs.umich.edu            %(op_rd)s;
994688Sgblack@eecs.umich.edu
1004688Sgblack@eecs.umich.edu            if(%(cond_check)s)
1014688Sgblack@eecs.umich.edu            {
1024688Sgblack@eecs.umich.edu                %(code)s;
1034688Sgblack@eecs.umich.edu                %(flag_code)s;
1044688Sgblack@eecs.umich.edu            }
1054708Sgblack@eecs.umich.edu            else
1064708Sgblack@eecs.umich.edu            {
1074708Sgblack@eecs.umich.edu                %(else_code)s;
1084708Sgblack@eecs.umich.edu            }
1094519Sgblack@eecs.umich.edu
1104519Sgblack@eecs.umich.edu            //Write the resulting state to the execution context
1114519Sgblack@eecs.umich.edu            if(fault == NoFault)
1124519Sgblack@eecs.umich.edu            {
1134519Sgblack@eecs.umich.edu                %(op_wb)s;
1144519Sgblack@eecs.umich.edu            }
1154519Sgblack@eecs.umich.edu            return fault;
1164519Sgblack@eecs.umich.edu        }
1174519Sgblack@eecs.umich.edu}};
1184519Sgblack@eecs.umich.edu
1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{
1204519Sgblack@eecs.umich.edu    class %(class_name)s : public %(base_class)s
1214519Sgblack@eecs.umich.edu    {
1224519Sgblack@eecs.umich.edu      protected:
1234519Sgblack@eecs.umich.edu        void buildMe();
1244519Sgblack@eecs.umich.edu
1254519Sgblack@eecs.umich.edu      public:
1264519Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
1274519Sgblack@eecs.umich.edu                const char * instMnem,
1284519Sgblack@eecs.umich.edu                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
1294519Sgblack@eecs.umich.edu                RegIndex _src1, RegIndex _src2, RegIndex _dest,
1304712Sgblack@eecs.umich.edu                uint8_t _dataSize, uint16_t _ext);
1314519Sgblack@eecs.umich.edu
1324519Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
1334519Sgblack@eecs.umich.edu                const char * instMnem,
1344519Sgblack@eecs.umich.edu                RegIndex _src1, RegIndex _src2, RegIndex _dest,
1354712Sgblack@eecs.umich.edu                uint8_t _dataSize, uint16_t _ext);
1364519Sgblack@eecs.umich.edu
1374519Sgblack@eecs.umich.edu        %(BasicExecDeclare)s
1384519Sgblack@eecs.umich.edu    };
1394519Sgblack@eecs.umich.edu}};
1404519Sgblack@eecs.umich.edu
1414519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{
1424519Sgblack@eecs.umich.edu
1434951Sgblack@eecs.umich.edu    class %(class_name)s : public %(base_class)s
1444519Sgblack@eecs.umich.edu    {
1454519Sgblack@eecs.umich.edu      protected:
1464519Sgblack@eecs.umich.edu        void buildMe();
1474519Sgblack@eecs.umich.edu
1484519Sgblack@eecs.umich.edu      public:
1494951Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
1504519Sgblack@eecs.umich.edu                const char * instMnem,
1514519Sgblack@eecs.umich.edu                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
1524951Sgblack@eecs.umich.edu                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
1534712Sgblack@eecs.umich.edu                uint8_t _dataSize, uint16_t _ext);
1544519Sgblack@eecs.umich.edu
1554951Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
1564519Sgblack@eecs.umich.edu                const char * instMnem,
1574951Sgblack@eecs.umich.edu                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
1584712Sgblack@eecs.umich.edu                uint8_t _dataSize, uint16_t _ext);
1594519Sgblack@eecs.umich.edu
1604519Sgblack@eecs.umich.edu        %(BasicExecDeclare)s
1614519Sgblack@eecs.umich.edu    };
1624519Sgblack@eecs.umich.edu}};
1634519Sgblack@eecs.umich.edu
1644519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{
1654519Sgblack@eecs.umich.edu
1664519Sgblack@eecs.umich.edu    inline void %(class_name)s::buildMe()
1674519Sgblack@eecs.umich.edu    {
1684519Sgblack@eecs.umich.edu        %(constructor)s;
1694519Sgblack@eecs.umich.edu    }
1704519Sgblack@eecs.umich.edu
1714519Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
1724519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
1734519Sgblack@eecs.umich.edu            RegIndex _src1, RegIndex _src2, RegIndex _dest,
1744712Sgblack@eecs.umich.edu            uint8_t _dataSize, uint16_t _ext) :
1754519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
1764581Sgblack@eecs.umich.edu                false, false, false, false,
1774688Sgblack@eecs.umich.edu                _src1, _src2, _dest, _dataSize, _ext,
1784581Sgblack@eecs.umich.edu                %(op_class)s)
1794519Sgblack@eecs.umich.edu    {
1804519Sgblack@eecs.umich.edu        buildMe();
1814519Sgblack@eecs.umich.edu    }
1824519Sgblack@eecs.umich.edu
1834519Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
1844519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
1854519Sgblack@eecs.umich.edu            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
1864519Sgblack@eecs.umich.edu            RegIndex _src1, RegIndex _src2, RegIndex _dest,
1874712Sgblack@eecs.umich.edu            uint8_t _dataSize, uint16_t _ext) :
1884519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
1894581Sgblack@eecs.umich.edu                isMicro, isDelayed, isFirst, isLast,
1904688Sgblack@eecs.umich.edu                _src1, _src2, _dest, _dataSize, _ext,
1914581Sgblack@eecs.umich.edu                %(op_class)s)
1924519Sgblack@eecs.umich.edu    {
1934519Sgblack@eecs.umich.edu        buildMe();
1944519Sgblack@eecs.umich.edu    }
1954519Sgblack@eecs.umich.edu}};
1964519Sgblack@eecs.umich.edu
1974519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{
1984519Sgblack@eecs.umich.edu
1994951Sgblack@eecs.umich.edu    inline void %(class_name)s::buildMe()
2004519Sgblack@eecs.umich.edu    {
2014519Sgblack@eecs.umich.edu        %(constructor)s;
2024519Sgblack@eecs.umich.edu    }
2034519Sgblack@eecs.umich.edu
2044951Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
2054519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
2064951Sgblack@eecs.umich.edu            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
2074712Sgblack@eecs.umich.edu            uint8_t _dataSize, uint16_t _ext) :
2084519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
2094581Sgblack@eecs.umich.edu                false, false, false, false,
2104688Sgblack@eecs.umich.edu                _src1, _imm8, _dest, _dataSize, _ext,
2114581Sgblack@eecs.umich.edu                %(op_class)s)
2124519Sgblack@eecs.umich.edu    {
2134519Sgblack@eecs.umich.edu        buildMe();
2144519Sgblack@eecs.umich.edu    }
2154519Sgblack@eecs.umich.edu
2164951Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
2174519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
2184519Sgblack@eecs.umich.edu            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
2194951Sgblack@eecs.umich.edu            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
2204712Sgblack@eecs.umich.edu            uint8_t _dataSize, uint16_t _ext) :
2214519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
2224581Sgblack@eecs.umich.edu                isMicro, isDelayed, isFirst, isLast,
2234688Sgblack@eecs.umich.edu                _src1, _imm8, _dest, _dataSize, _ext,
2244581Sgblack@eecs.umich.edu                %(op_class)s)
2254519Sgblack@eecs.umich.edu    {
2264519Sgblack@eecs.umich.edu        buildMe();
2274519Sgblack@eecs.umich.edu    }
2284519Sgblack@eecs.umich.edu}};
2294519Sgblack@eecs.umich.edu
2304519Sgblack@eecs.umich.edulet {{
2314688Sgblack@eecs.umich.edu    class X86MicroMeta(type):
2324688Sgblack@eecs.umich.edu        def __new__(mcls, name, bases, dict):
2334688Sgblack@eecs.umich.edu            abstract = False
2344688Sgblack@eecs.umich.edu            if "abstract" in dict:
2354688Sgblack@eecs.umich.edu                abstract = dict['abstract']
2364688Sgblack@eecs.umich.edu                del dict['abstract']
2374688Sgblack@eecs.umich.edu
2384688Sgblack@eecs.umich.edu            cls = type.__new__(mcls, name, bases, dict)
2394688Sgblack@eecs.umich.edu            if not abstract:
2404688Sgblack@eecs.umich.edu                allClasses[name] = cls
2414688Sgblack@eecs.umich.edu            return cls
2424688Sgblack@eecs.umich.edu
2434688Sgblack@eecs.umich.edu    class XXX86Microop(object):
2444688Sgblack@eecs.umich.edu        __metaclass__ = X86MicroMeta
2454688Sgblack@eecs.umich.edu        abstract = True
2464688Sgblack@eecs.umich.edu
2474528Sgblack@eecs.umich.edu    class RegOp(X86Microop):
2484688Sgblack@eecs.umich.edu        abstract = True
2494701Sgblack@eecs.umich.edu        def __init__(self, dest, src1, src2, flags, dataSize):
2504519Sgblack@eecs.umich.edu            self.dest = dest
2514519Sgblack@eecs.umich.edu            self.src1 = src1
2524519Sgblack@eecs.umich.edu            self.src2 = src2
2534688Sgblack@eecs.umich.edu            self.flags = flags
2544701Sgblack@eecs.umich.edu            self.dataSize = dataSize
2554688Sgblack@eecs.umich.edu            if flags is None:
2564688Sgblack@eecs.umich.edu                self.ext = 0
2574688Sgblack@eecs.umich.edu            else:
2584688Sgblack@eecs.umich.edu                if not isinstance(flags, (list, tuple)):
2594688Sgblack@eecs.umich.edu                    raise Exception, "flags must be a list or tuple of flags"
2604688Sgblack@eecs.umich.edu                self.ext = " | ".join(flags)
2614688Sgblack@eecs.umich.edu                self.className += "Flags"
2624519Sgblack@eecs.umich.edu
2634519Sgblack@eecs.umich.edu        def getAllocator(self, *microFlags):
2644560Sgblack@eecs.umich.edu            allocator = '''new %(class_name)s(machInst, mnemonic
2654539Sgblack@eecs.umich.edu                    %(flags)s, %(src1)s, %(src2)s, %(dest)s,
2664688Sgblack@eecs.umich.edu                    %(dataSize)s, %(ext)s)''' % {
2674519Sgblack@eecs.umich.edu                "class_name" : self.className,
2684519Sgblack@eecs.umich.edu                "flags" : self.microFlagsText(microFlags),
2694519Sgblack@eecs.umich.edu                "src1" : self.src1, "src2" : self.src2,
2704519Sgblack@eecs.umich.edu                "dest" : self.dest,
2714519Sgblack@eecs.umich.edu                "dataSize" : self.dataSize,
2724519Sgblack@eecs.umich.edu                "ext" : self.ext}
2734539Sgblack@eecs.umich.edu            return allocator
2744519Sgblack@eecs.umich.edu
2754528Sgblack@eecs.umich.edu    class RegOpImm(X86Microop):
2764688Sgblack@eecs.umich.edu        abstract = True
2774701Sgblack@eecs.umich.edu        def __init__(self, dest, src1, imm8, flags, dataSize):
2784519Sgblack@eecs.umich.edu            self.dest = dest
2794519Sgblack@eecs.umich.edu            self.src1 = src1
2804560Sgblack@eecs.umich.edu            self.imm8 = imm8
2814688Sgblack@eecs.umich.edu            self.flags = flags
2824701Sgblack@eecs.umich.edu            self.dataSize = dataSize
2834688Sgblack@eecs.umich.edu            if flags is None:
2844688Sgblack@eecs.umich.edu                self.ext = 0
2854688Sgblack@eecs.umich.edu            else:
2864688Sgblack@eecs.umich.edu                if not isinstance(flags, (list, tuple)):
2874688Sgblack@eecs.umich.edu                    raise Exception, "flags must be a list or tuple of flags"
2884688Sgblack@eecs.umich.edu                self.ext = " | ".join(flags)
2894688Sgblack@eecs.umich.edu                self.className += "Flags"
2904519Sgblack@eecs.umich.edu
2914519Sgblack@eecs.umich.edu        def getAllocator(self, *microFlags):
2924560Sgblack@eecs.umich.edu            allocator = '''new %(class_name)s(machInst, mnemonic
2934539Sgblack@eecs.umich.edu                    %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
2944688Sgblack@eecs.umich.edu                    %(dataSize)s, %(ext)s)''' % {
2954519Sgblack@eecs.umich.edu                "class_name" : self.className,
2964519Sgblack@eecs.umich.edu                "flags" : self.microFlagsText(microFlags),
2974519Sgblack@eecs.umich.edu                "src1" : self.src1, "imm8" : self.imm8,
2984519Sgblack@eecs.umich.edu                "dest" : self.dest,
2994519Sgblack@eecs.umich.edu                "dataSize" : self.dataSize,
3004519Sgblack@eecs.umich.edu                "ext" : self.ext}
3014539Sgblack@eecs.umich.edu            return allocator
3024519Sgblack@eecs.umich.edu}};
3034519Sgblack@eecs.umich.edu
3044519Sgblack@eecs.umich.edulet {{
3054519Sgblack@eecs.umich.edu
3064519Sgblack@eecs.umich.edu    # Make these empty strings so that concatenating onto
3074519Sgblack@eecs.umich.edu    # them will always work.
3084519Sgblack@eecs.umich.edu    header_output = ""
3094519Sgblack@eecs.umich.edu    decoder_output = ""
3104519Sgblack@eecs.umich.edu    exec_output = ""
3114519Sgblack@eecs.umich.edu
3124688Sgblack@eecs.umich.edu    # A function which builds the C++ classes that implement the microops
3134951Sgblack@eecs.umich.edu    def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";", imm=False):
3144519Sgblack@eecs.umich.edu        global header_output
3154519Sgblack@eecs.umich.edu        global decoder_output
3164519Sgblack@eecs.umich.edu        global exec_output
3174528Sgblack@eecs.umich.edu        global microopClasses
3184595Sgblack@eecs.umich.edu
3194612Sgblack@eecs.umich.edu        iop = InstObjParams(name, Name, base,
3204612Sgblack@eecs.umich.edu                {"code" : code,
3214688Sgblack@eecs.umich.edu                 "flag_code" : flagCode,
3224708Sgblack@eecs.umich.edu                 "cond_check" : condCheck,
3234708Sgblack@eecs.umich.edu                 "else_code" : elseCode})
3244951Sgblack@eecs.umich.edu        if imm:
3254951Sgblack@eecs.umich.edu            header_output += MicroRegOpImmDeclare.subst(iop)
3264951Sgblack@eecs.umich.edu            decoder_output += MicroRegOpImmConstructor.subst(iop)
3274951Sgblack@eecs.umich.edu            exec_output += MicroRegOpImmExecute.subst(iop)
3284951Sgblack@eecs.umich.edu        else:
3294951Sgblack@eecs.umich.edu            header_output += MicroRegOpDeclare.subst(iop)
3304951Sgblack@eecs.umich.edu            decoder_output += MicroRegOpConstructor.subst(iop)
3314951Sgblack@eecs.umich.edu            exec_output += MicroRegOpExecute.subst(iop)
3324595Sgblack@eecs.umich.edu
3334595Sgblack@eecs.umich.edu
3344688Sgblack@eecs.umich.edu    checkCCFlagBits = "checkCondition(ccFlagBits)"
3354798Sgblack@eecs.umich.edu    genCCFlagBits = \
3364823Sgblack@eecs.umich.edu        "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
3374798Sgblack@eecs.umich.edu    genCCFlagBitsSub = \
3384823Sgblack@eecs.umich.edu        "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
3394798Sgblack@eecs.umich.edu    genCCFlagBitsLogic = '''
3404798Sgblack@eecs.umich.edu        //Don't have genFlags handle the OF or CF bits
3414798Sgblack@eecs.umich.edu        uint64_t mask = CFBit | OFBit;
3424823Sgblack@eecs.umich.edu        ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
3434798Sgblack@eecs.umich.edu        //If a logic microop wants to set these, it wants to set them to 0.
3444798Sgblack@eecs.umich.edu        ccFlagBits &= ~(CFBit & ext);
3454798Sgblack@eecs.umich.edu        ccFlagBits &= ~(OFBit & ext);
3464798Sgblack@eecs.umich.edu    '''
3474688Sgblack@eecs.umich.edu
3484809Sgblack@eecs.umich.edu    regPick = '''
3494823Sgblack@eecs.umich.edu        IntReg psrc1 = pick(SrcReg1, 0, dataSize);
3504823Sgblack@eecs.umich.edu        IntReg psrc2 = pick(SrcReg2, 1, dataSize);
3514809Sgblack@eecs.umich.edu    '''
3524809Sgblack@eecs.umich.edu    immPick = '''
3534823Sgblack@eecs.umich.edu        IntReg psrc1 = pick(SrcReg1, 0, dataSize);
3544809Sgblack@eecs.umich.edu    '''
3554809Sgblack@eecs.umich.edu
3564688Sgblack@eecs.umich.edu
3574688Sgblack@eecs.umich.edu    # This creates a python representations of a microop which are a cross
3584688Sgblack@eecs.umich.edu    # product of reg/immediate and flag/no flag versions.
3594798Sgblack@eecs.umich.edu    def defineMicroRegOp(mnemonic, code, flagCode=genCCFlagBits, \
3605028Sgblack@eecs.umich.edu            cc=False, doImm=True, elseCode=";"):
3614519Sgblack@eecs.umich.edu        Name = mnemonic
3624519Sgblack@eecs.umich.edu        name = mnemonic.lower()
3634519Sgblack@eecs.umich.edu
3644519Sgblack@eecs.umich.edu        # Find op2 in each of the instruction definitions. Create two versions
3654519Sgblack@eecs.umich.edu        # of the code, one with an integer operand, and one with an immediate
3664519Sgblack@eecs.umich.edu        # operand.
3674519Sgblack@eecs.umich.edu        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
3684823Sgblack@eecs.umich.edu        regCode = regPick + matcher.sub("psrc2", code)
3694809Sgblack@eecs.umich.edu        immCode = immPick + matcher.sub("imm8", code)
3704519Sgblack@eecs.umich.edu
3714688Sgblack@eecs.umich.edu        if not cc:
3724688Sgblack@eecs.umich.edu            condCode = "true"
3734688Sgblack@eecs.umich.edu        else:
3744688Sgblack@eecs.umich.edu            flagCode = ""
3754688Sgblack@eecs.umich.edu            condCode = checkCCFlagBits
3764688Sgblack@eecs.umich.edu
3774823Sgblack@eecs.umich.edu        regFlagCode = matcher.sub("psrc2", flagCode)
3784688Sgblack@eecs.umich.edu        immFlagCode = matcher.sub("imm8", flagCode)
3794688Sgblack@eecs.umich.edu
3804519Sgblack@eecs.umich.edu        class RegOpChild(RegOp):
3814688Sgblack@eecs.umich.edu            mnemonic = name
3824688Sgblack@eecs.umich.edu            className = Name
3834798Sgblack@eecs.umich.edu            def __init__(self, dest, src1, src2, \
3844798Sgblack@eecs.umich.edu                    flags=None, dataSize="env.dataSize"):
3854798Sgblack@eecs.umich.edu                super(RegOpChild, self).__init__(dest, src1, src2, \
3864798Sgblack@eecs.umich.edu                        flags, dataSize)
3874519Sgblack@eecs.umich.edu
3884688Sgblack@eecs.umich.edu        microopClasses[name] = RegOpChild
3894519Sgblack@eecs.umich.edu
3904714Sgblack@eecs.umich.edu        setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
3914809Sgblack@eecs.umich.edu        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp",
3924809Sgblack@eecs.umich.edu                regCode, flagCode=regFlagCode,
3934809Sgblack@eecs.umich.edu                condCheck=condCode, elseCode=elseCode);
3944688Sgblack@eecs.umich.edu
3955028Sgblack@eecs.umich.edu        if doImm:
3965028Sgblack@eecs.umich.edu            class RegOpChildImm(RegOpImm):
3975028Sgblack@eecs.umich.edu                mnemonic = name + 'i'
3985028Sgblack@eecs.umich.edu                className = Name + 'Imm'
3995028Sgblack@eecs.umich.edu                def __init__(self, dest, src1, src2, \
4005028Sgblack@eecs.umich.edu                        flags=None, dataSize="env.dataSize"):
4015028Sgblack@eecs.umich.edu                    super(RegOpChildImm, self).__init__(dest, src1, src2, \
4025028Sgblack@eecs.umich.edu                            flags, dataSize)
4034519Sgblack@eecs.umich.edu
4045028Sgblack@eecs.umich.edu            microopClasses[name + 'i'] = RegOpChildImm
4054519Sgblack@eecs.umich.edu
4065028Sgblack@eecs.umich.edu            setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
4075028Sgblack@eecs.umich.edu                    immCode, imm=True);
4085028Sgblack@eecs.umich.edu            setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm",
4095028Sgblack@eecs.umich.edu                    immCode, flagCode=immFlagCode,
4105028Sgblack@eecs.umich.edu                    condCheck=condCode, elseCode=elseCode, imm=True);
4114688Sgblack@eecs.umich.edu
4124592Sgblack@eecs.umich.edu    # This has it's own function because Wr ops have implicit destinations
4134708Sgblack@eecs.umich.edu    def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
4144592Sgblack@eecs.umich.edu        Name = mnemonic
4154592Sgblack@eecs.umich.edu        name = mnemonic.lower()
4164592Sgblack@eecs.umich.edu
4174592Sgblack@eecs.umich.edu        # Find op2 in each of the instruction definitions. Create two versions
4184592Sgblack@eecs.umich.edu        # of the code, one with an integer operand, and one with an immediate
4194592Sgblack@eecs.umich.edu        # operand.
4204592Sgblack@eecs.umich.edu        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
4214823Sgblack@eecs.umich.edu        regCode = regPick + matcher.sub("psrc2", code)
4224809Sgblack@eecs.umich.edu        immCode = immPick + matcher.sub("imm8", code)
4234592Sgblack@eecs.umich.edu
4244592Sgblack@eecs.umich.edu        class RegOpChild(RegOp):
4254688Sgblack@eecs.umich.edu            mnemonic = name
4264688Sgblack@eecs.umich.edu            className = Name
4274701Sgblack@eecs.umich.edu            def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
4284701Sgblack@eecs.umich.edu                super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
4294688Sgblack@eecs.umich.edu
4304688Sgblack@eecs.umich.edu        microopClasses[name] = RegOpChild
4314688Sgblack@eecs.umich.edu
4324714Sgblack@eecs.umich.edu        setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
4334714Sgblack@eecs.umich.edu        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
4344714Sgblack@eecs.umich.edu                condCheck = checkCCFlagBits, elseCode = elseCode);
4354688Sgblack@eecs.umich.edu
4364688Sgblack@eecs.umich.edu        class RegOpChildImm(RegOpImm):
4374708Sgblack@eecs.umich.edu            mnemonic = name + 'i'
4384708Sgblack@eecs.umich.edu            className = Name + 'Imm'
4394701Sgblack@eecs.umich.edu            def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
4404701Sgblack@eecs.umich.edu                super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
4414592Sgblack@eecs.umich.edu
4424688Sgblack@eecs.umich.edu        microopClasses[name + 'i'] = RegOpChildImm
4434592Sgblack@eecs.umich.edu
4444951Sgblack@eecs.umich.edu        setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", \
4454951Sgblack@eecs.umich.edu                immCode, imm=True);
4464951Sgblack@eecs.umich.edu        setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", \
4474951Sgblack@eecs.umich.edu                immCode, condCheck = checkCCFlagBits, elseCode = elseCode, \
4484951Sgblack@eecs.umich.edu                imm=True);
4494592Sgblack@eecs.umich.edu
4504592Sgblack@eecs.umich.edu    # This has it's own function because Rd ops don't always have two parameters
4514592Sgblack@eecs.umich.edu    def defineMicroRegOpRd(mnemonic, code):
4524592Sgblack@eecs.umich.edu        Name = mnemonic
4534592Sgblack@eecs.umich.edu        name = mnemonic.lower()
4544592Sgblack@eecs.umich.edu
4554592Sgblack@eecs.umich.edu        class RegOpChild(RegOp):
4564951Sgblack@eecs.umich.edu            className = Name
4574951Sgblack@eecs.umich.edu            mnemonic = name
4584701Sgblack@eecs.umich.edu            def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
4594701Sgblack@eecs.umich.edu                super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
4604592Sgblack@eecs.umich.edu
4614688Sgblack@eecs.umich.edu        microopClasses[name] = RegOpChild
4624688Sgblack@eecs.umich.edu
4634714Sgblack@eecs.umich.edu        setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
4644592Sgblack@eecs.umich.edu
4654950Sgblack@eecs.umich.edu    def defineMicroRegOpImm(mnemonic, code, flagCode=""):
4664595Sgblack@eecs.umich.edu        Name = mnemonic
4674595Sgblack@eecs.umich.edu        name = mnemonic.lower()
4684809Sgblack@eecs.umich.edu        code = immPick + code
4694595Sgblack@eecs.umich.edu
4704595Sgblack@eecs.umich.edu        class RegOpChild(RegOpImm):
4714951Sgblack@eecs.umich.edu            className = Name
4724951Sgblack@eecs.umich.edu            mnemonic = name
4734951Sgblack@eecs.umich.edu            def __init__(self, dest, src1, src2, \
4744951Sgblack@eecs.umich.edu                    flags=None, dataSize="env.dataSize"):
4754951Sgblack@eecs.umich.edu                super(RegOpChild, self).__init__(dest, \
4764951Sgblack@eecs.umich.edu                        src1, src2, flags, dataSize)
4774595Sgblack@eecs.umich.edu
4784688Sgblack@eecs.umich.edu        microopClasses[name] = RegOpChild
4794688Sgblack@eecs.umich.edu
4804951Sgblack@eecs.umich.edu        setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True);
4814951Sgblack@eecs.umich.edu        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \
4824951Sgblack@eecs.umich.edu                code, flagCode=flagCode, imm=True);
4834951Sgblack@eecs.umich.edu
4844951Sgblack@eecs.umich.edu    def defineMicroRegOpRdImm(mnemonic, code, flagCode=""):
4854951Sgblack@eecs.umich.edu        Name = mnemonic
4864951Sgblack@eecs.umich.edu        name = mnemonic.lower()
4874951Sgblack@eecs.umich.edu        code = immPick + code
4884951Sgblack@eecs.umich.edu
4894951Sgblack@eecs.umich.edu        class RegOpChildRdImm(RegOpImm):
4904951Sgblack@eecs.umich.edu            className = Name
4914951Sgblack@eecs.umich.edu            mnemonic = name
4924951Sgblack@eecs.umich.edu            def __init__(self, dest, imm, flags=None, \
4934951Sgblack@eecs.umich.edu                    dataSize="env.dataSize"):
4944951Sgblack@eecs.umich.edu                super(RegOpChildRdImm, self).__init__(dest, \
4954951Sgblack@eecs.umich.edu                        "NUM_INTREGS", imm, flags, dataSize)
4964951Sgblack@eecs.umich.edu
4974951Sgblack@eecs.umich.edu        microopClasses[name] = RegOpChildRdImm
4984951Sgblack@eecs.umich.edu
4994951Sgblack@eecs.umich.edu        setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True);
5004951Sgblack@eecs.umich.edu        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \
5014951Sgblack@eecs.umich.edu                code, flagCode=flagCode, imm=True);
5024595Sgblack@eecs.umich.edu
5034823Sgblack@eecs.umich.edu    defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)')
5044823Sgblack@eecs.umich.edu    defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);',
5054798Sgblack@eecs.umich.edu            flagCode = genCCFlagBitsLogic)
5064732Sgblack@eecs.umich.edu    defineMicroRegOp('Adc', '''
5074732Sgblack@eecs.umich.edu            CCFlagBits flags = ccFlagBits;
5084823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize);
5094732Sgblack@eecs.umich.edu            ''')
5104732Sgblack@eecs.umich.edu    defineMicroRegOp('Sbb', '''
5114732Sgblack@eecs.umich.edu            CCFlagBits flags = ccFlagBits;
5124823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize);
5134798Sgblack@eecs.umich.edu            ''', flagCode = genCCFlagBitsSub)
5144798Sgblack@eecs.umich.edu    defineMicroRegOp('And', \
5154823Sgblack@eecs.umich.edu            'DestReg = merge(DestReg, psrc1 & op2, dataSize)', \
5164798Sgblack@eecs.umich.edu            flagCode = genCCFlagBitsLogic)
5174798Sgblack@eecs.umich.edu    defineMicroRegOp('Sub', \
5184823Sgblack@eecs.umich.edu            'DestReg = merge(DestReg, psrc1 - op2, dataSize)', \
5194798Sgblack@eecs.umich.edu            flagCode = genCCFlagBitsSub)
5204798Sgblack@eecs.umich.edu    defineMicroRegOp('Xor', \
5214823Sgblack@eecs.umich.edu            'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)', \
5224798Sgblack@eecs.umich.edu            flagCode = genCCFlagBitsLogic)
5234809Sgblack@eecs.umich.edu    defineMicroRegOp('Mul1s', '''
5244809Sgblack@eecs.umich.edu            int signPos = (dataSize * 8) / 2 - 1;
5254823Sgblack@eecs.umich.edu            IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos);
5264823Sgblack@eecs.umich.edu            IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos);
5274809Sgblack@eecs.umich.edu            DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
5284809Sgblack@eecs.umich.edu            ''')
5294809Sgblack@eecs.umich.edu    defineMicroRegOp('Mul1u', '''
5304809Sgblack@eecs.umich.edu            int halfSize = (dataSize * 8) / 2;
5314823Sgblack@eecs.umich.edu            IntReg srcVal1 = psrc1 & mask(halfSize);
5324809Sgblack@eecs.umich.edu            IntReg srcVal2 = op2 & mask(halfSize);
5334809Sgblack@eecs.umich.edu            DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
5344809Sgblack@eecs.umich.edu            ''')
5354809Sgblack@eecs.umich.edu    defineMicroRegOp('Mulel', \
5364823Sgblack@eecs.umich.edu            'DestReg = merge(DestReg, psrc1 * op2, dataSize)')
5374809Sgblack@eecs.umich.edu    defineMicroRegOp('Muleh', '''
5384809Sgblack@eecs.umich.edu            int halfSize = (dataSize * 8) / 2;
5394823Sgblack@eecs.umich.edu            uint64_t psrc1_h = psrc1 >> halfSize;
5404823Sgblack@eecs.umich.edu            uint64_t psrc1_l = psrc1 & mask(halfSize);
5414823Sgblack@eecs.umich.edu            uint64_t psrc2_h = op2 >> halfSize;
5424823Sgblack@eecs.umich.edu            uint64_t psrc2_l = op2 & mask(halfSize);
5434809Sgblack@eecs.umich.edu            uint64_t result =
5444823Sgblack@eecs.umich.edu                ((psrc1_l * psrc2_h) >> halfSize) +
5454823Sgblack@eecs.umich.edu                ((psrc1_h * psrc2_l) >> halfSize) +
5464823Sgblack@eecs.umich.edu                psrc1_h * psrc2_h;
5474809Sgblack@eecs.umich.edu            DestReg = merge(DestReg, result, dataSize);
5484809Sgblack@eecs.umich.edu            ''')
5494823Sgblack@eecs.umich.edu    defineMicroRegOp('Div1', '''
5504823Sgblack@eecs.umich.edu            int halfSize = (dataSize * 8) / 2;
5514823Sgblack@eecs.umich.edu            IntReg quotient = (psrc1 / op2) & mask(halfSize);
5524823Sgblack@eecs.umich.edu            IntReg remainder = (psrc1 % op2) & mask(halfSize);
5534823Sgblack@eecs.umich.edu            IntReg result = quotient | (remainder << halfSize);
5544823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, result, dataSize);
5554823Sgblack@eecs.umich.edu            ''')
5564823Sgblack@eecs.umich.edu    defineMicroRegOp('Divq', '''
5574823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, psrc1 / op2, dataSize);
5584823Sgblack@eecs.umich.edu            ''')
5594823Sgblack@eecs.umich.edu    defineMicroRegOp('Divr', '''
5604823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, psrc1 % op2, dataSize);
5614823Sgblack@eecs.umich.edu            ''')
5624823Sgblack@eecs.umich.edu
5634809Sgblack@eecs.umich.edu    #
5644823Sgblack@eecs.umich.edu    # HACK HACK HACK HACK - Put psrc1 in here but make it inert to shut up gcc.
5654809Sgblack@eecs.umich.edu    #
5665028Sgblack@eecs.umich.edu    defineMicroRegOp('Mov',
5675028Sgblack@eecs.umich.edu            'DestReg = merge(SrcReg1, psrc1 * 0 + op2, dataSize)',
5684732Sgblack@eecs.umich.edu            elseCode='DestReg=DestReg;', cc=True)
5694732Sgblack@eecs.umich.edu
5705028Sgblack@eecs.umich.edu    defineMicroRegOp('Movfp',
5715028Sgblack@eecs.umich.edu            'FpDestReg = FpSrcReg2 + psrc1 * 0 + psrc2 * 0',
5725028Sgblack@eecs.umich.edu            elseCode='FpDestReg=FpDestReg;', cc=True, doImm=False)
5735028Sgblack@eecs.umich.edu
5744732Sgblack@eecs.umich.edu    # Shift instructions
5754732Sgblack@eecs.umich.edu    defineMicroRegOp('Sll', '''
5764756Sgblack@eecs.umich.edu            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
5774823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
5784732Sgblack@eecs.umich.edu            ''')
5794732Sgblack@eecs.umich.edu    defineMicroRegOp('Srl', '''
5804756Sgblack@eecs.umich.edu            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
5814732Sgblack@eecs.umich.edu            // Because what happens to the bits shift -in- on a right shift
5824732Sgblack@eecs.umich.edu            // is not defined in the C/C++ standard, we have to mask them out
5834732Sgblack@eecs.umich.edu            // to be sure they're zero.
5844732Sgblack@eecs.umich.edu            uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
5854823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
5864732Sgblack@eecs.umich.edu            ''')
5874732Sgblack@eecs.umich.edu    defineMicroRegOp('Sra', '''
5884756Sgblack@eecs.umich.edu            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
5894732Sgblack@eecs.umich.edu            // Because what happens to the bits shift -in- on a right shift
5904732Sgblack@eecs.umich.edu            // is not defined in the C/C++ standard, we have to sign extend
5914732Sgblack@eecs.umich.edu            // them manually to be sure.
5924732Sgblack@eecs.umich.edu            uint64_t arithMask =
5934732Sgblack@eecs.umich.edu                -bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
5944823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
5954732Sgblack@eecs.umich.edu            ''')
5964732Sgblack@eecs.umich.edu    defineMicroRegOp('Ror', '''
5974732Sgblack@eecs.umich.edu            uint8_t shiftAmt =
5984756Sgblack@eecs.umich.edu                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
5994732Sgblack@eecs.umich.edu            if(shiftAmt)
6004732Sgblack@eecs.umich.edu            {
6014823Sgblack@eecs.umich.edu                uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
6024823Sgblack@eecs.umich.edu                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
6034732Sgblack@eecs.umich.edu                DestReg = merge(DestReg, top | bottom, dataSize);
6044732Sgblack@eecs.umich.edu            }
6054732Sgblack@eecs.umich.edu            else
6064732Sgblack@eecs.umich.edu                DestReg = DestReg;
6074732Sgblack@eecs.umich.edu            ''')
6084732Sgblack@eecs.umich.edu    defineMicroRegOp('Rcr', '''
6094733Sgblack@eecs.umich.edu            uint8_t shiftAmt =
6104756Sgblack@eecs.umich.edu                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
6114733Sgblack@eecs.umich.edu            if(shiftAmt)
6124733Sgblack@eecs.umich.edu            {
6134733Sgblack@eecs.umich.edu                CCFlagBits flags = ccFlagBits;
6144733Sgblack@eecs.umich.edu                uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
6154733Sgblack@eecs.umich.edu                if(shiftAmt > 1)
6164823Sgblack@eecs.umich.edu                    top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
6174823Sgblack@eecs.umich.edu                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
6184733Sgblack@eecs.umich.edu                DestReg = merge(DestReg, top | bottom, dataSize);
6194733Sgblack@eecs.umich.edu            }
6204733Sgblack@eecs.umich.edu            else
6214733Sgblack@eecs.umich.edu                DestReg = DestReg;
6224732Sgblack@eecs.umich.edu            ''')
6234732Sgblack@eecs.umich.edu    defineMicroRegOp('Rol', '''
6244732Sgblack@eecs.umich.edu            uint8_t shiftAmt =
6254756Sgblack@eecs.umich.edu                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
6264732Sgblack@eecs.umich.edu            if(shiftAmt)
6274732Sgblack@eecs.umich.edu            {
6284823Sgblack@eecs.umich.edu                uint64_t top = psrc1 << shiftAmt;
6294732Sgblack@eecs.umich.edu                uint64_t bottom =
6304823Sgblack@eecs.umich.edu                    bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
6314732Sgblack@eecs.umich.edu                DestReg = merge(DestReg, top | bottom, dataSize);
6324732Sgblack@eecs.umich.edu            }
6334732Sgblack@eecs.umich.edu            else
6344732Sgblack@eecs.umich.edu                DestReg = DestReg;
6354732Sgblack@eecs.umich.edu            ''')
6364732Sgblack@eecs.umich.edu    defineMicroRegOp('Rcl', '''
6374733Sgblack@eecs.umich.edu            uint8_t shiftAmt =
6384756Sgblack@eecs.umich.edu                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
6394733Sgblack@eecs.umich.edu            if(shiftAmt)
6404733Sgblack@eecs.umich.edu            {
6414733Sgblack@eecs.umich.edu                CCFlagBits flags = ccFlagBits;
6424823Sgblack@eecs.umich.edu                uint64_t top = psrc1 << shiftAmt;
6434733Sgblack@eecs.umich.edu                uint64_t bottom = flags.CF << (shiftAmt - 1);
6444733Sgblack@eecs.umich.edu                if(shiftAmt > 1)
6454733Sgblack@eecs.umich.edu                    bottom |=
6464823Sgblack@eecs.umich.edu                        bits(psrc1, dataSize * 8 - 1,
6474809Sgblack@eecs.umich.edu                                   dataSize * 8 - shiftAmt + 1);
6484733Sgblack@eecs.umich.edu                DestReg = merge(DestReg, top | bottom, dataSize);
6494733Sgblack@eecs.umich.edu            }
6504733Sgblack@eecs.umich.edu            else
6514733Sgblack@eecs.umich.edu                DestReg = DestReg;
6524732Sgblack@eecs.umich.edu            ''')
6534732Sgblack@eecs.umich.edu
6544823Sgblack@eecs.umich.edu    defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
6554950Sgblack@eecs.umich.edu    defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;')
6564868Sgblack@eecs.umich.edu    defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2')
6574732Sgblack@eecs.umich.edu
6584732Sgblack@eecs.umich.edu    defineMicroRegOpRd('Rdip', 'DestReg = RIP')
6594868Sgblack@eecs.umich.edu    defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits')
6604951Sgblack@eecs.umich.edu    defineMicroRegOpRdImm('Ruflag', '''
6615011Sgblack@eecs.umich.edu            int flag = bits(ccFlagBits, imm8 + 0*psrc1);
6624951Sgblack@eecs.umich.edu            DestReg = merge(DestReg, flag, dataSize);
6635011Sgblack@eecs.umich.edu            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
6645011Sgblack@eecs.umich.edu                                       (ccFlagBits & ~EZFBit);
6654951Sgblack@eecs.umich.edu            ''')
6664732Sgblack@eecs.umich.edu
6674595Sgblack@eecs.umich.edu    defineMicroRegOpImm('Sext', '''
6684823Sgblack@eecs.umich.edu            IntReg val = psrc1;
6694595Sgblack@eecs.umich.edu            int sign_bit = bits(val, imm8-1, imm8-1);
6705007Sgblack@eecs.umich.edu            uint64_t maskVal = mask(imm8);
6715007Sgblack@eecs.umich.edu            val = sign_bit ? (val | ~maskVal) : (val & maskVal);
6725007Sgblack@eecs.umich.edu            DestReg = merge(DestReg, val, dataSize);
6735007Sgblack@eecs.umich.edu            ''')
6744714Sgblack@eecs.umich.edu
6754823Sgblack@eecs.umich.edu    defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);')
6764519Sgblack@eecs.umich.edu}};
677