xref: /gem5/src/arch/x86/isa/microops/regop.isa

// Copyright (c) 2007 The Hewlett-Packard Development Company
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// Authors: Gabe Black

//////////////////////////////////////////////////////////////////////////
//
// RegOp Microop templates
//
//////////////////////////////////////////////////////////////////////////

def template MicroRegOpExecute {{
        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                Trace::InstRecord *traceData) const
        {
            Fault fault = NoFault;

            %(op_decl)s;
            %(op_rd)s;

            if(%(cond_check)s)
            {
                %(code)s;
                %(flag_code)s;
            }
            else
            {
                %(else_code)s;
            }

            //Write the resulting state to the execution context
            if(fault == NoFault)
            {
                %(op_wb)s;
            }
            return fault;
        }
}};

def template MicroRegOpImmExecute {{
        Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc,
                Trace::InstRecord *traceData) const
        {
            Fault fault = NoFault;

            %(op_decl)s;
            %(op_rd)s;

            if(%(cond_check)s)
            {
                %(code)s;
                %(flag_code)s;
            }
            else
            {
                %(else_code)s;
            }

            //Write the resulting state to the execution context
            if(fault == NoFault)
            {
                %(op_wb)s;
            }
            return fault;
        }
}};

def template MicroRegOpDeclare {{
    class %(class_name)s : public %(base_class)s
    {
      protected:
        void buildMe();

      public:
        %(class_name)s(ExtMachInst _machInst,
                const char * instMnem,
                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
                RegIndex _src1, RegIndex _src2, RegIndex _dest,
                uint8_t _dataSize, uint16_t _ext);

        %(class_name)s(ExtMachInst _machInst,
                const char * instMnem,
                RegIndex _src1, RegIndex _src2, RegIndex _dest,
                uint8_t _dataSize, uint16_t _ext);

        %(BasicExecDeclare)s
    };
}};

def template MicroRegOpImmDeclare {{

    class %(class_name)sImm : public %(base_class)s
    {
      protected:
        void buildMe();

      public:
        %(class_name)sImm(ExtMachInst _machInst,
                const char * instMnem,
                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
                uint8_t _dataSize, uint16_t _ext);

        %(class_name)sImm(ExtMachInst _machInst,
                const char * instMnem,
                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
                uint8_t _dataSize, uint16_t _ext);

        %(BasicExecDeclare)s
    };
}};

def template MicroRegOpConstructor {{

    inline void %(class_name)s::buildMe()
    {
        %(constructor)s;
    }

    inline %(class_name)s::%(class_name)s(
            ExtMachInst machInst, const char * instMnem,
            RegIndex _src1, RegIndex _src2, RegIndex _dest,
            uint8_t _dataSize, uint16_t _ext) :
        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                false, false, false, false,
                _src1, _src2, _dest, _dataSize, _ext,
                %(op_class)s)
    {
        buildMe();
    }

    inline %(class_name)s::%(class_name)s(
            ExtMachInst machInst, const char * instMnem,
            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
            RegIndex _src1, RegIndex _src2, RegIndex _dest,
            uint8_t _dataSize, uint16_t _ext) :
        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                isMicro, isDelayed, isFirst, isLast,
                _src1, _src2, _dest, _dataSize, _ext,
                %(op_class)s)
    {
        buildMe();
    }
}};

def template MicroRegOpImmConstructor {{

    inline void %(class_name)sImm::buildMe()
    {
        %(constructor)s;
    }

    inline %(class_name)sImm::%(class_name)sImm(
            ExtMachInst machInst, const char * instMnem,
            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
            uint8_t _dataSize, uint16_t _ext) :
        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                false, false, false, false,
                _src1, _imm8, _dest, _dataSize, _ext,
                %(op_class)s)
    {
        buildMe();
    }

    inline %(class_name)sImm::%(class_name)sImm(
            ExtMachInst machInst, const char * instMnem,
            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
            uint8_t _dataSize, uint16_t _ext) :
        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                isMicro, isDelayed, isFirst, isLast,
                _src1, _imm8, _dest, _dataSize, _ext,
                %(op_class)s)
    {
        buildMe();
    }
}};

let {{
    class X86MicroMeta(type):
        def __new__(mcls, name, bases, dict):
            abstract = False
            if "abstract" in dict:
                abstract = dict['abstract']
                del dict['abstract']

            cls = type.__new__(mcls, name, bases, dict)
            if not abstract:
                allClasses[name] = cls
            return cls

    class XXX86Microop(object):
        __metaclass__ = X86MicroMeta
        abstract = True

    class RegOp(X86Microop):
        abstract = True
        def __init__(self, dest, src1, src2, flags, dataSize):
            self.dest = dest
            self.src1 = src1
            self.src2 = src2
            self.flags = flags
            self.dataSize = dataSize
            if flags is None:
                self.ext = 0
            else:
                if not isinstance(flags, (list, tuple)):
                    raise Exception, "flags must be a list or tuple of flags"
                self.ext = " | ".join(flags)
                self.className += "Flags"

        def getAllocator(self, *microFlags):
            allocator = '''new %(class_name)s(machInst, mnemonic
                    %(flags)s, %(src1)s, %(src2)s, %(dest)s,
                    %(dataSize)s, %(ext)s)''' % {
                "class_name" : self.className,
                "flags" : self.microFlagsText(microFlags),
                "src1" : self.src1, "src2" : self.src2,
                "dest" : self.dest,
                "dataSize" : self.dataSize,
                "ext" : self.ext}
            return allocator

    class RegOpImm(X86Microop):
        abstract = True
        def __init__(self, dest, src1, imm8, flags, dataSize):
            self.dest = dest
            self.src1 = src1
            self.imm8 = imm8
            self.flags = flags
            self.dataSize = dataSize
            if flags is None:
                self.ext = 0
            else:
                if not isinstance(flags, (list, tuple)):
                    raise Exception, "flags must be a list or tuple of flags"
                self.ext = " | ".join(flags)
                self.className += "Flags"

        def getAllocator(self, *microFlags):
            allocator = '''new %(class_name)s(machInst, mnemonic
                    %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
                    %(dataSize)s, %(ext)s)''' % {
                "class_name" : self.className,
                "flags" : self.microFlagsText(microFlags),
                "src1" : self.src1, "imm8" : self.imm8,
                "dest" : self.dest,
                "dataSize" : self.dataSize,
                "ext" : self.ext}
            return allocator
}};

let {{

    # Make these empty strings so that concatenating onto
    # them will always work.
    header_output = ""
    decoder_output = ""
    exec_output = ""

    # A function which builds the C++ classes that implement the microops
    def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"):
        global header_output
        global decoder_output
        global exec_output
        global microopClasses

        iop = InstObjParams(name, Name, base,
                {"code" : code,
                 "flag_code" : flagCode,
                 "cond_check" : condCheck,
                 "else_code" : elseCode})
        header_output += MicroRegOpDeclare.subst(iop)
        decoder_output += MicroRegOpConstructor.subst(iop)
        exec_output += MicroRegOpExecute.subst(iop)


    checkCCFlagBits = "checkCondition(ccFlagBits)"
    genCCFlagBits = \
        "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, op2);"
    genCCFlagBitsSub = \
        "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, ~op2, true);"
    genCCFlagBitsLogic = '''
        //Don't have genFlags handle the OF or CF bits
        uint64_t mask = CFBit | OFBit;
        ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, SrcReg1, op2);
        //If a logic microop wants to set these, it wants to set them to 0.
        ccFlagBits &= ~(CFBit & ext);
        ccFlagBits &= ~(OFBit & ext);
    '''


    # This creates a python representations of a microop which are a cross
    # product of reg/immediate and flag/no flag versions.
    def defineMicroRegOp(mnemonic, code, flagCode=genCCFlagBits, \
            cc=False, elseCode=";"):
        Name = mnemonic
        name = mnemonic.lower()

        # Find op2 in each of the instruction definitions. Create two versions
        # of the code, one with an integer operand, and one with an immediate
        # operand.
        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
        regCode = matcher.sub("SrcReg2", code)
        immCode = matcher.sub("imm8", code)

        if not cc:
            condCode = "true"
        else:
            flagCode = ""
            condCode = checkCCFlagBits

        regFlagCode = matcher.sub("SrcReg2", flagCode)
        immFlagCode = matcher.sub("imm8", flagCode)

        class RegOpChild(RegOp):
            mnemonic = name
            className = Name
            def __init__(self, dest, src1, src2, \
                    flags=None, dataSize="env.dataSize"):
                super(RegOpChild, self).__init__(dest, src1, src2, \
                        flags, dataSize)

        microopClasses[name] = RegOpChild

        setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
                flagCode=regFlagCode, condCheck=condCode, elseCode=elseCode);

        class RegOpChildImm(RegOpImm):
            mnemonic = name + 'i'
            className = Name + 'Imm'
            def __init__(self, dest, src1, src2, \
                    flags=None, dataSize="env.dataSize"):
                super(RegOpChildImm, self).__init__(dest, src1, src2, \
                        flags, dataSize)

        microopClasses[name + 'i'] = RegOpChildImm

        setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
        setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
                flagCode=immFlagCode, condCheck=condCode, elseCode=elseCode);

    # This has it's own function because Wr ops have implicit destinations
    def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
        Name = mnemonic
        name = mnemonic.lower()

        # Find op2 in each of the instruction definitions. Create two versions
        # of the code, one with an integer operand, and one with an immediate
        # operand.
        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
        regCode = matcher.sub("SrcReg2", code)
        immCode = matcher.sub("imm8", code)

        class RegOpChild(RegOp):
            mnemonic = name
            className = Name
            def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
                super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)

        microopClasses[name] = RegOpChild

        setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
                condCheck = checkCCFlagBits, elseCode = elseCode);

        class RegOpChildImm(RegOpImm):
            mnemonic = name + 'i'
            className = Name + 'Imm'
            def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
                super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)

        microopClasses[name + 'i'] = RegOpChildImm

        setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
        setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
                condCheck = checkCCFlagBits, elseCode = elseCode);

    # This has it's own function because Rd ops don't always have two parameters
    def defineMicroRegOpRd(mnemonic, code):
        Name = mnemonic
        name = mnemonic.lower()

        class RegOpChild(RegOp):
            def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
                super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
                self.className = Name
                self.mnemonic = name

        microopClasses[name] = RegOpChild

        setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);

    def defineMicroRegOpImm(mnemonic, code):
        Name = mnemonic
        name = mnemonic.lower()

        class RegOpChild(RegOpImm):
            def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
                super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize)
                self.className = Name
                self.mnemonic = name

        microopClasses[name] = RegOpChild

        setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);

    defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
    defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)',
            flagCode = genCCFlagBitsLogic)
    defineMicroRegOp('Adc', '''
            CCFlagBits flags = ccFlagBits;
            DestReg = merge(DestReg, SrcReg1 + op2 + flags.CF, dataSize);
            ''')
    defineMicroRegOp('Sbb', '''
            CCFlagBits flags = ccFlagBits;
            DestReg = merge(DestReg, SrcReg1 - op2 - flags.CF, dataSize);
            ''', flagCode = genCCFlagBitsSub)
    defineMicroRegOp('And', \
            'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', \
            flagCode = genCCFlagBitsLogic)
    defineMicroRegOp('Sub', \
            'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', \
            flagCode = genCCFlagBitsSub)
    defineMicroRegOp('Xor', \
            'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', \
            flagCode = genCCFlagBitsLogic)
    defineMicroRegOp('Mul1s', \
            'DestReg = merge(DestReg, DestReg * op2, dataSize)')
    defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
            elseCode='DestReg=DestReg;', cc=True)

    # Shift instructions
    defineMicroRegOp('Sll', '''
            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
            DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize);
            ''')
    defineMicroRegOp('Srl', '''
            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
            // Because what happens to the bits shift -in- on a right shift
            // is not defined in the C/C++ standard, we have to mask them out
            // to be sure they're zero.
            uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
            DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) & logicalMask, dataSize);
            ''')
    defineMicroRegOp('Sra', '''
            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
            // Because what happens to the bits shift -in- on a right shift
            // is not defined in the C/C++ standard, we have to sign extend
            // them manually to be sure.
            uint64_t arithMask =
                -bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
            DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) | arithMask, dataSize);
            ''')
    defineMicroRegOp('Ror', '''
            uint8_t shiftAmt =
                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
            if(shiftAmt)
            {
                uint64_t top = SrcReg1 << (dataSize * 8 - shiftAmt);
                uint64_t bottom = bits(SrcReg1, dataSize * 8, shiftAmt);
                DestReg = merge(DestReg, top | bottom, dataSize);
            }
            else
                DestReg = DestReg;
            ''')
    defineMicroRegOp('Rcr', '''
            uint8_t shiftAmt =
                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
            if(shiftAmt)
            {
                CCFlagBits flags = ccFlagBits;
                uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
                if(shiftAmt > 1)
                    top |= SrcReg1 << (dataSize * 8 - shiftAmt - 1);
                uint64_t bottom = bits(SrcReg1, dataSize * 8, shiftAmt);
                DestReg = merge(DestReg, top | bottom, dataSize);
            }
            else
                DestReg = DestReg;
            ''')
    defineMicroRegOp('Rol', '''
            uint8_t shiftAmt =
                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
            if(shiftAmt)
            {
                uint64_t top = SrcReg1 << shiftAmt;
                uint64_t bottom =
                    bits(SrcReg1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
                DestReg = merge(DestReg, top | bottom, dataSize);
            }
            else
                DestReg = DestReg;
            ''')
    defineMicroRegOp('Rcl', '''
            uint8_t shiftAmt =
                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
            if(shiftAmt)
            {
                CCFlagBits flags = ccFlagBits;
                uint64_t top = SrcReg1 << shiftAmt;
                uint64_t bottom = flags.CF << (shiftAmt - 1);
                if(shiftAmt > 1)
                    bottom |=
                        bits(SrcReg1, dataSize * 8 - 1,
                                      dataSize * 8 - shiftAmt + 1);
                DestReg = merge(DestReg, top | bottom, dataSize);
            }
            else
                DestReg = DestReg;
            ''')

    defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;")

    defineMicroRegOpRd('Rdip', 'DestReg = RIP')

    defineMicroRegOpImm('Sext', '''
            IntReg val = SrcReg1;
            int sign_bit = bits(val, imm8-1, imm8-1);
            val = sign_bit ? (val | ~mask(imm8)) : val;
            DestReg = merge(DestReg, val, dataSize);''')

    defineMicroRegOpImm('Zext', 'DestReg = bits(SrcReg1, imm8-1, 0);')
}};